JPH0946378A - Transfer data modulation/demodulation system for serial data transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale of a short distance data transmission system, cost and current consumption. SOLUTION: Two data lines consisting of an 'H' data transmission line and an 'L' data transmission line are prepared and a data format including a clock component is attained without using an expensive modem. A receiving clock is extracted by finding out OR between the data of both the transmission lines. A conversion circuit 1 to NRZ(non-return to zero) data outputs 'H' data when the 'H' data transmission line is turned to 'H' and outputs 'L' data when the 'L' data transmission line is turned to 'H' and NRZ data can be recognized by sampling the data by the receiving clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transfer data modulation / demodulation system for a serial data transmission device in a microcomputer system.

[0002]

2. Description of the Related Art In a microcomputer system, there is a serial transmission method as a method for exchanging data with other devices and computer systems.

Normally, on the transmitting side, NRZ (Non Re
Data such as "turn to zero" and a transmission clock are given to a modem (modulation / demodulation device), where they are converted (modulated) into data having a clock component and transmitted. On the receiving side, the received data having the clock component is separated (demodulated) into data such as NRZ and the received clock by the PLL circuit of the modem. The schematic configuration of the transmission system is shown in FIG.
Shown in In the figure, 61 is a modulation circuit, 62 is a demodulation circuit, and 63.
Is a transmission path. The illustrated example is an example of transmitting data in one direction, and since most of the transmission systems are bidirectional, a modem is used for the modulation circuit 61 and the demodulation circuit 62.

As a coding method for data transmission that does not require the insertion of a synchronization clock, "DS Link" is used.
(Data / Strobe Link) method "(Nikkei Electronics 1994.7.4" Providing an isochronous transfer function for multimedia data ") is proposed, and the relationship between the data and strobe is shown in FIG.

[0005]

Modems for performing data modulation / demodulation are widely used in systems for transmitting data over long distances. The use of a modem solves the problems of signal distortion and delay in long-distance data transmission and increases the transmission efficiency, but increases the circuit scale of the modem section.

When this type of modem is applied to a system for performing in-board transmission or short-distance board-to-board transmission, the transmission distance is short but the function is too high, the circuit scale becomes large, and the cost is very high. It is a disadvantage.

Further, the "DS Link system" shown in FIG.
However, the configuration of the data transmission / reception circuit is slightly complicated.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to solve the above problems and to provide a transfer data modulation / demodulation system for a serial data transmission device which has a simple circuit configuration and which can reduce the circuit scale and cost. To do.

[0009]

SUMMARY OF THE INVENTION According to the present invention, a data line of a serial data transmission device is a two-wire system of an "H" data transmission line and an "L" data transmission line, and data having a clock component is provided.・ By implementing the format and taking the OR of the data of both transmission lines, the reception clock is extracted, while the "H" data from the NRZ data,
A circuit for converting to "L" data, outputs "H" when the "H" data transmission line becomes "H", and outputs "L" when the "L" data transmission line becomes "H". Output,
It is characterized in that a conversion circuit for converting to NRZ data is provided and the data is recognized by sampling the NRZ data with a reception clock.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. The present invention is premised on transmission within a panel or transmission between panels at a short distance, and the data line is a two-wire system of an "H" data transmission line and an "L" data transmission line, It is modulated into a data format as shown in FIG. 1 and transmitted.

That is, in the transmission format, "H" data exists in the A area and C area, "L" data exists in the B area and C area, respectively, and in the D area, "H" data and "L" data exist. If both do not exist, the area A is the data of “1”, the area B
The area has a structure of "0" data, and the areas C and D have a structure showing an "idle" state.

FIG. 2 shows an example of data reception. O of the data of the "H" data transmission line and the "L" data transmission line
The reception clock is extracted by taking R (logical sum). To convert to NRZ data, input the data of the "H" data transmission line as shown in FIG.
When the data of the "L" data transmission line is used as a reset input, "H" is output when the "H" data transmission line becomes "H", and when the "L" data transmission line becomes "H". The circuit 1 that outputs "L" is used. The data is recognized by sampling the NRZ data at the falling edge of the reception clock.

FIG. 4 shows a configuration example of the receiving circuit. The receiving circuit comprises a D-flip flop (LS74 or the like) 1A used as a latch circuit and a NOT circuit (LS04 or the like) 1B, a conversion circuit 1 for converting the above-mentioned NRZ data, a NOR circuit (LS02 or the like) for extracting a reception clock. ) 2, this NO
It is composed of an SP conversion circuit (LS164 etc.) 3 for sampling the NRZ data at the falling edge of the output (reception clock) of the R circuit 2 to obtain parallel data.

When the "H" data is input to the clock terminal of the D-flip-flop 1A, the data ("H") of the D terminal appears at the Q output terminal and the inverted signal (N) of the "L" data is input.
When the output of the OT circuit 1B) is input to the clear terminal, it is cleared and the Q output terminal becomes "L". That is, NRZ data is obtained at the Q output terminal. This NRZ data is NOR
The data is recognized by being sampled at the falling edge of the output (reception clock) of the circuit 2, and is converted into parallel data.

FIG. 5 shows an example of the structure of the transmission circuit. A circuit for converting the NRZ data into the data of the “H” data transmission line and the data of the “L” data transmission line by using the double transmission clock is provided on the “L” data side by a D-flip flop ( LS74) 11 and EX. OR circuit (LS
86, etc.) 12, and on the "H" data side with D-flip-flops (LS74, etc.) 13 and EX. The OR circuit (LS86, etc.) 14 and the NOT circuit (LS04, etc.) 15 are respectively configured.

Complementary output of Q of D-flip flop 11 and EX. The OR is added to the D terminal, and the D input before the arrival of the double transmission clock occurs at the Q output after the arrival. The complementary output of this Q output becomes "L" data. Further, the complementary output of Q of the D-flip flop 13 and the inverted signal of the NRZ data (the output of the NOT circuit 15)
EX. The OR is added to the D terminal, and the D input before the arrival of the double transmission clock occurs at the Q output after the arrival. This Q output becomes "H" data.

[0017]

As described above, according to the present invention, data
Since the line is a two-wire system of an “H” data transmission line and an “L” data transmission line, a data format having a clock component is realized, so a special DPLL
A modem having a circuit or the like is not necessary, so that the circuit scale of hardware can be reduced, and cost and current consumption can be reduced. Further, there is an advantage that the configurations of the transmission circuit and the reception circuit are simple. Especially, it is effective for short-distance data transmission such as intra-panel transmission and inter-panel transmission.

[Brief description of drawings]

FIG. 1 is a transmission format showing an embodiment of the present invention.

FIG. 2 is a time chart of a data pattern of a data reception example according to an embodiment of the present invention.

FIG. 3 is a block diagram for explaining a conversion operation into NRZ data according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration example of a receiving circuit according to an embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration example of a transmission circuit according to an embodiment of the present invention.

FIG. 6 is a schematic configuration diagram of a data transmission system.

FIG. 7 is a time chart showing the relationship between data and strobes in the DS Link system.

[Explanation of symbols]

 1 ... NRZ data conversion circuit 1A ... D-flip flop 1B ... NOT circuit 2 ... NOR circuit 3 ... SP conversion circuit 11, 13 ... D- flip flop 12, 14 ... EX. OR circuit 15 ... NOT circuit

Claims (1)

[Claims] 1. A data line having a clock component, wherein a data line of a serial data transmission device is a two-wire system of an "H" data transmission line and an "L" data transmission line.
Realize the format and OR the data of both transmission lines
While extracting the reception clock by taking
"H" When the transmission line for data becomes "H", "H"
Output, and outputs a “L” when the “L” data transmission line becomes “H”, a conversion circuit for NRZ data is provided, and the data is recognized by sampling the NRZ data with a reception clock. A transfer data modulation / demodulation method for a serial data transmission device characterized in that