JPS60204150A - Data transmission system - Google Patents

Abstract

PURPOSE:To attain low power consumption by transmitting two kinds of pulses having different pulse width in response to the rising and falling of a transmission data signal and allowing a reception side to invert the polarity of a binary level according to the pulse width of the reception pulse to eliminate the need for a complicated coding/decoding circuit. CONSTITUTION:An output signal (a) of a transmission circuit 1 for start-stop data is inputted to a signal converting circuit 2, and differentiation circuits 2a, 2b of the circuit 2 detect the rising and falling of the signal (a). An output of the circuits 2a, 2b triggers monostable multivibrator circuits 3a, 3b, an OR gate 5 generates two kinds of pulses in response to the rising falling of different pulse width and transmits it from a light emitting section 6 to a photodetection section 7. The signal is converted into an electric signal by the photodetector section 7 and the result is inputted to a signal regenerating circuit 3. Then monostable multivibrator circuits 6a, 6b, AND gates 7a, 7b and an FF9 of the circuit 3 process the signal, demodulates the signal in response to the pulse width of the reception pulse to simplify the system constitution thereby decreasing the power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a data transmission system for transmitting and receiving digital data between two devices.

Prior art The conventional data transmission method uses data logic "1" and °
There is a system in which data is transmitted using a start-stop cycle, etc., with binary levels (for example, high level and low level) corresponding to "θ'', and a pulse interval is changed in response to data "1'' and O°'. A pulse position modulation method is used.

Nowadays, remote control units that utilize infrared light are widely used in home appliances such as televisions and air conditioners. Although remote control has not yet become commonplace in general data terminals, it is increasingly being used. For example, data terminals and their keyboards were conventionally connected using multi-core cables, but due to aesthetic requirements, curl cord connections were adopted that reduced the number of data signal lines through serial data transmission. It is expected that there will be a shift to cordless connections.

In the case of cordless connection, it is important that at least one unit consumes little power because it is operated by a battery or the like. In particular, it is most important to reduce the power consumption of the optical output circuit, which consumes a high proportion of power.

In the above-mentioned method of transmitting binary level signals using start-stop synchronization, the power consumption of the transmitting section is greatly influenced by the number of 1' degrees in the data signal, and the lower the transmission speed, the lower the power consumption of the transmitting section. There is a disadvantage that the signal becomes large.Furthermore, even when there is no transmission information, the transmitter's IE power is consumed to transmit the mark signal.

On the other hand, in the conventional method of modulating the pulse interval, the data transmission method is special, so a special control circuit is required, and a start signal is required for each character block.

OBJECTS OF THE INVENTION An object of the present invention is to solve the conventional drawbacks mentioned above, and to reduce the power consumption of a data transmission transmitting section without requiring complicated line scrutinization circuits, decoding circuits, and their control sections. The objective is to provide a data transmission method that can

Structure of the Invention The data transmission system of the present invention is based on the logic of binary data signals.
A first conversion point detection circuit detects a conversion point from ``1'' to logic ``0'', and a second conversion point detection circuit detects a conversion point from logic ``O'' to logic ``1゛''. , a first pulse generation circuit that generates a wide pulse according to the output of the first conversion point detection circuit, and a second pulse that generates a narrow pulse according to the output of the second conversion point detection circuit described in +iiij. and a generating circuit, the output pulses of the first and second pulse generating circuits are sent out, and the receiving side reproduces the original data using two types of pulses.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be described in detail 1 with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In other words, the output signal a (see No. 21 (A)) of the transmission circuit 1 of the loss-of-scale data similar to the conventional one is input to the signal conversion circuit 2, and the signal conversion circuit 2 converts the signal as shown in FIG. 2(B). , a wide pulse is output at the falling edge of the input data a, and a narrow pulse is output at the rising edge of the input data a. The pulse train signal d output from the signal conversion circuit 2 is sent out directly as an electrical signal or after being converted into light. On the receiving side, the signal reproducing circuit 3 converts the received pulse from a low level to a low level or from a low level to a high level according to the width of the received pulse, and restores the original start-stop data signal as shown in FIG. 2(C). The regenerated signal g is output and the receiving circuit 4 is manually operated. The receiving circuit 4 is a start-stop type data signal receiving circuit similar to the conventional one.

FIG. 3 is a block diagram showing details of the signal conversion circuit 2 and signal regeneration circuit 3. As shown in FIG. The signal conversion circuit 2 includes a differentiating circuit 2a that detects the falling point of the input signal a, a differentiating circuit 2b that detects the falling point, and a detection signal of the differentiating circuit 2a that is already triturated to generate pulses N t t. A mono multi circuit 3a that generates a pulse with a pulse width t2 triggered by the detection signal C of the differentiating circuit 2b, and an OR circuit 5 that synthesizes and outputs the outputs of the mono multi circuits 3a and 3b. It consists of The output of the OR circuit 5 drives the light emitting section 6. The light emitting unit 6 may be used by switching modulation using a high frequency. In this embodiment, the differentiating circuits 2a and 2b constitute the first and @2 conversion point detection circuits, respectively, and the monomulti circuits 3a and 3b are first and second pulse generating circuits.

A light pulse output from the light emitting section 6 is received by the light receiving section 7, converted into an electric pulse signal, and supplied to the inverter circuit 8. Mono multi circuit 6 with the output of inverter circuit 8
a is triggered, and the monomulti circuit 6a generates a pulse e having a time width t3. Output pulse e of monomulti circuit 6a
At the trailing edge of , the mono multi-circuit 6b is tripped, and the mono multi-circuit 6b generates a pulse f having a time width t4.

The pulse r and the output of the inverter circuit 8 are connected to NAN
The pulse is input to the D gate 7a, and the flip-flop circuit 9 is set by the output pulse of the NAND gate 7a. On the other hand, the pulse f and the input signal of the input circuit 8 are
The output pulse from the NAND gate 7b resets the flip-flop circuit 9. The output signal g of the flip-flop circuit 9 is the original data signal a or the generated Nr signal (+1).

ε;) 4 (Tsukasa (A) to (G) are time charts 1 and 2 indicating the signals of each part. Now, if 1.>1., then +3 is t,>+3>+2 The mono multi-circuit 6b is tri-inputted by the falling of the output pulse e of the mono-multi circuit 6a, and has a time width t4 (ta is preferably about t - 3). Therefore, when the inverter circuit 8 has a large pulse or a wide pulse with a time width t1, the pulse f is NA
When the input pulse of the inverter circuit 8 has a narrow pulse width of 2, the pulse f passes through the NAND gate 7a and is input to the set terminal S of the flip-flop circuit 9, thereby setting the flip-flop circuit 9 in the set state. Therefore, the output signal g of the flip-flop circuit 9 becomes as shown in FIG. 4(G), which is a signal obtained by reproducing the data signal a shown in FIG. 4(A).

This embodiment can be applied to any 2-16 level signal, rather than the human input signal or the tonal data signal of the signal conversion circuit 2. In other words, it can be realized by adding a relatively simple signal conversion circuit 2 and signal regeneration circuit 3 to an existing transmitting/receiving circuit, and the existing transmitting/receiving circuit can be used as is regardless of the transmission format. be. Also, when there is no data information, there is no need to transmit anything, and when there is data information, there is no need to transmit anything at the data conversion point.
Since it only sends out different types of pulses, it is particularly effective in reducing the power consumption of the transmitting section. Another advantage is that even if a specific pulse miss occurs, it does not affect subsequent data.

Effects of the Invention As described above, in the present invention, two types of pulses with different pulse widths are sent out in response to the rising edge and falling edge of the transmitted data signal, and on the receiving side, the pulse width of the received pulse is Since the configuration is configured to invert the polarity of the binary signal according to the signal, it is possible to easily add a converter circuit and a signal generator circuit to the existing transmitter/receiver circuit. There is an effect that it is possible to reduce power consumption. If applied to a remote transmission method using infrared light or the like, the power required to drive light emission can be significantly reduced. Another advantage is that pulse misses do not affect subsequent data.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a time chart showing various signals of the embodiment described above, and Fig. 3 is a signal conversion circuit of the above embodiment. and a block diagram showing details of the signal reproducing circuit, and FIG. 4 is a time chart showing an example of signals of each part in the m3 diagram. In the figure, l: transmitting circuit, 2: signal converting circuit, 3: signal reproducing circuit, 4: receiving circuit, 5: OR circuit, 6: light emitting section, 7: light receiving section, 8: input differential circuit, 3a ,3b,
6a, 6b: Mono multi circuit, 7a, 7b:
NAND gate. Applicant: NEC Corporation Agent: Patent Attorney: Toshimune Sumita? ” 7 3 “1 Fang 4 diagram

Claims (1)

[Claims] a first conversion point detection circuit for detecting a conversion point of a binary data signal from logic "1°" to logic "OII";
a second conversion point detection circuit that detects a conversion point from ° to logic "l"; and a first pulse generation circuit that generates a wide pulse based on the output of the first conversion point detection circuit;
a second pulse generation circuit that generates narrow pulses based on the output of the second conversion point detection circuit, and transmits the output pulses of the first and second pulse generation circuits, and on the receiving side, ” - A data transmission system characterized by reproducing the original data signal using two types of pulses.