JPS62159174A - Synchronous signal processing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention provides an input consisting of a positive polarity signal with a low level in steady state and a high level synchronization pulse, and a negative polarity signal with a high level in steady state and a low level synchronization pulse. In a system that transmits information based on the polarity of a synchronization signal, it is installed on the receiving side of the input synchronization signal to determine the polarity of the synchronization signal and use this to derive a signal indicating this polarity and an output synchronization signal with a constant polarity. This invention relates to a synchronization signal processing circuit.

[Prior Art] When transmitting information from a device that generates or transmits a signal, such as a personal computer, to a device that receives the signal, or when controlling the function of the receiving device, there is a need for a signal for that purpose and for transmitting the signal. lines are required. For example, CR
If you want to change the deflection frequency, display size, brightness, etc. of the T-display from the personal computer, you will need signals and lines to control these in addition to the originally required video signals and synchronization signals. It becomes necessary.

[Problems to be Solved by the Invention] In the prior art, when attempting to perform new control or information transmission, it is necessary to add signals and lines.
The cost is high and there are problems with compatibility.

The present invention is intended to solve these problems, and aims to enable new control or information transmission by using signals and lines, that is, signal cables, connectors, etc., as they are without any addition.

[Means for Solving the Problems] A synchronization signal processing circuit according to the present invention receives a synchronization signal whose polarity is changed according to information, determines the polarity of the synchronization signal, and outputs the same as a signal. By using this to output a synchronization signal with a constant polarity, it is possible to transmit information based on the polarity of the synchronization signal. For example, in a system such as a personal computer and a CRT display that generates a synchronization signal using continuous pulses and consists of a device that transmits it and a device that operates by receiving it, information is transmitted depending on the polarity of the synchronization signal. For example, since a CRT display receives two synchronization signals, a horizontal synchronization signal and a vertical synchronization signal, it is possible to transmit 2-bit information, and this can be used to transmit information other than the normal display information. Transmission or function control can be performed.

Specifically, the synchronization signal processing circuit according to the present invention includes a polarity determination circuit having an integrating circuit for determining the polarity of a synchronization signal, and an exclusive OR circuit for obtaining a synchronization signal of constant polarity. Ru. Conventional synchronous circuits assume a signal with one polarity, either positive or negative, so this is for compatibility reasons.

It is necessary to keep the polarity of the output synchronization signal constant.

[Function] The integrator circuit in this invention has a time constant sufficiently large for the period of the synchronizing signal, and converts the synchronizing signal into its average value voltage. The average value voltage is converted into a logic level, ie, a high/low binary value, by a logic element with an appropriate threshold value. This logic level is a signal indicating polarity, and when it is high level, it is negative polarity, and when it is low level, it is positive polarity. This signal is added to an exclusive OR circuit together with a synchronizing signal to output a synchronizing signal with constant polarity.

[Embodiment] Fig. 1 is a circuit diagram showing an embodiment of the present invention. In Fig. 1, (1) is a polarity discrimination circuit which receives an input synchronization signal A and outputs a polarity output B; (2) (3) ) are buffers or inverters, (4) and (5) are resistors and capacitors that constitute the integrating circuit (6), and (7) receives the input synchronization signal A and polarity output B, and outputs an output synchronization signal C with a constant polarity. This is an exclusive OR circuit to derive.

FIG. 2 is a diagram for explaining the operation of FIG.
In the figure, A, B, and C indicate the voltage waveforms of each circuit part in Figure 1. 6 The human power interphase signal A is initially at a steady extremely low level, and the synchronization pulse is at a high level and positive polarity, and the point (a) , the synchronization pulse changes to a low level of negative polarity at a steady extra high level,
It depicts a state in which the polarity changes to positive again at point (G).

Now, the input synchronization signal A is integrated by the integrating circuit (6) to become an average value voltage, and this average value voltage depends on the logic level, that is, the polarity of the input synchronization signal A, by an appropriate threshold value of the buffer or inverter (3). It is converted into two values: high/low. This logic level becomes a signal indicating the polarity of the input synchronization signal A, as shown as polarity output B in Fig. 2, and is a low level when the input synchronization signal A has positive polarity, and a high level when it has negative polarity. level. This polarity output B is input to the exclusive OR circuit (7) together with the input synchronization signal A, and output synchronization signal C with a constant polarity corresponding to the synchronization pulse.
is derived.

FIG. 3 is a schematic circuit diagram showing an example of application of the present invention,
A case is shown in which horizontal and vertical resynchronization signals provided in a CRT display are used to select all four codes of the CRT display. In Fig. 3, Aa and Ab are horizontal and vertical input synchronization signals, respectively, (la) (lb
) is a polarity discrimination circuit that derives polarity outputs Ba and Bb, (7
a) (7b) is a polarity discrimination circuit that derives the output synchronization signals Ca and Cb; (8) is a decoder to which the polarity outputs Ba and Bb are input and derives a desired mode selection output circuit D-G; , Bb, one of the mode selection outputs DG is selected and output.

FIG. 4 is a detailed circuit diagram of FIG. 3 above. In FIG. 4, each synchronizing signal Aa, Ab inverted by the inverter (2a) (2b) is connected to the integrator circuit (6a) (6b).
becomes the average value voltage. The inverters (3a) (3b) convert this average value voltage into a logic level using a suitable threshold value and derive polarity outputs Ba, Bb. Inverter (9
a) (9b) and AND circuit (10) (11) (1
2) The decoder (8) consisting of (13) has a polarity output B
a, Bb are decoded, one of the output terminals DG is set to high level, and a desired mode selection output is derived.

[Effects of the Invention] As described above, the present invention enables stable synchronization by determining the polarity of a synchronization signal on the receiving side and converting it into a synchronization signal with constant polarity. Since it can be used for transmission and does not require new signals or lines, it has the advantage of being low cost and highly compatible with conventional systems.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of FIG. 1, FIG. 3 is a schematic circuit diagram showing an application example of the invention, and FIG. FIG. 4 is a detailed circuit diagram of FIG. 3; In the figure, (1) is a polarity discrimination circuit, (7) is an exclusive OR circuit, A is an input synchronization signal, B is a polarity output, and C is an output synchronization signal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] A polarity discrimination circuit that receives an input synchronization signal consisting of a positive polarity signal with a low level in steady state and a high level synchronization pulse, and a negative polarity signal with a high level in steady state and a low level synchronization pulse, and derives a polarity output according to the polarity. and an exclusive OR circuit which receives the polarity output of the polarity discrimination circuit and the input synchronization signal and derives an output synchronization signal with a constant polarity.