JPS62159175A - Polarity discriminator circuit for synchronous signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention provides synchronization consisting of a positive polarity signal with a low level in steady state and a high level synchronization pulse, and a negative polarity signal with a high level in steady state and a low level synchronization pulse. The present invention relates to a signal polarity determination circuit.

[Prior Art] In a system consisting of a device that operates in response to a synchronization signal in the form of continuous pulses and a device that supplies the synchronization signal, such as a personal computer and a CRT display, signals or information are transmitted from the supply side. Therefore, it is possible to give meaning to the polarity of the synchronization signal. For this purpose, a synchronizing signal polarity determination circuit is provided on the side of the device receiving the synchronizing signal.

FIG. 3 shows this type of conventional polarity discrimination circuit.

In FIG. 3, (1) and (2) are buffers or inverters, and (3) and (4) are resistors and capacitors that constitute an integrator (5). The input synchronization signal A is integrated by the integrator (5) to become an average value voltage, which becomes a logic level by an appropriate threshold value of the buffer or inverter (2), and the polarity output B according to the polarity is determined by the input synchronization signal A. In the case of positive polarity, a low level is output, and in the case of negative polarity, a high level is output. (6) is an exclusive OR circuit to which the polarity output B and the input synchronization signal A are input, and derives an output synchronization signal C having a constant polarity according to the synchronization pulse.

Generally, a synchronous circuit assumes either positive or negative polarity, so this circuit is necessary from the standpoint of compatibility.

[Problems to be Solved by the Invention] Here, the time constant To of the integrator (5) must be such that the ripple at the input of the buffer or inverter (2) is sufficiently small. If the ripple is large and the buffer or inverter (2) approaches the threshold value, the circuit may become unstable or malfunction. Conversely, the time constant To directly affects the response time of the circuit. When the period of the synchronization signal is long, it is necessary to increase the time constant TO, and in this case, the response time also increases. For example, when using the vertical synchronization signal of a CRT display, the response time is 1
In some cases, it becomes noticeable to humans. Also, the large capacitor (4) used to obtain a large time constant is
There is large variation in values and fluctuations due to temperature, and this causes a change in the time constant, potentially making the operation unstable.

This invention was made to solve this problem, and by detecting the voltage level immediately after the trailing edge of the synchronizing signal consisting of periodic pulses and holding it, the polarity of the synchronizing signal can be quickly changed. Moreover, it is possible to obtain a polarity discrimination circuit that can stably discriminate.

[Means for Solving the Problems] The polarity discrimination circuit according to the present invention detects the level immediately after the trailing edge of the synchronization pulse using two multivibrators,
By holding this, the polarity can be determined quickly and stably.

[Function] For example, a monomulticircuit is used as one of the multivibrators, and is triggered by the leading edge of the synchronizing signal to generate a pulse with a time width T□. The trailing edge of this pulse triggers the other multivibrator, for example a D-flip-flop circuit.

Latch the level of the input sync signal immediately after the sync pulse.

Therefore, the time width T□ needs to be sufficiently larger than the pulse width of the synchronizing signal. If the change in polarity of the synchronization signal occurs within the pulse width of the synchronization signal, the response time of this circuit is T□.

If this condition does not exist, the response time will be one cycle at most.

[Embodiment] Fig. 1 is a circuit diagram showing an embodiment of the present invention, where A is an input synchronization signal, and (7) this input synchronization signal A is input to one input terminal, and the polarity is changed according to the polarity. a first multivibrator that derives an output B;

For example, the D-flip-flop circuit (6) receives the polarity output B of this first multivibrator (7) and the above-mentioned manual synchronization signal A, and outputs the synchronization signal C according to the synchronization pulse.
The exclusive OR circuit (8) is driven by the output synchronization signal C of this exclusive OR circuit (6), and derives a pulse output with a width larger than the synchronization pulse width of the input synchronization signal A. a second multivibrator, for example a monomulticircuit, and this second multivibrator (8)
The pulse output of the above first multivibrator (7)
is input to the other input terminal. (9) and (10) are resistors and capacitors for providing a time constant that determines the output pulse width of the second multivibrator (8).

Mono multi circuit (8) which is the second multi vibrator
The trigger is not the input synchronization signal A, but the output synchronization signal C.
It is carried out in This is because the monomulti circuit (8) is triggered by the rising or falling edge of the pulse, so when using the input sync signal A, it may be triggered by the leading edge of the sync signal pulse or the trailing edge, and the pulse width may vary. This is because a corresponding error will occur.

Since the output synchronization signal C always has positive polarity in this case, the monomulti circuit (8) is always triggered by the leading edge of the synchronization signal. Note that Vcc in FIG. 1 is a power source for driving each multivibrator (7) (8).

FIG. 2 is a time chart for explaining the operation of FIG. 1, and A, B, C, and D in FIG. 2 indicate voltage waveforms of each circuit portion in FIG. 1. The input synchronization signal A initially has positive polarity, becomes negative polarity at point (f), and changes to positive polarity again at point (i). Mono multi circuit (8
] is triggered at the leading edge point <a> of the output synchronization signal C, and outputs pulses (b) to (c) with a width T1 as a pulse output. At the rising edge (c) of this pulse output, the D-flip-flop circuit (7) is triggered, reads the level (d) of the input synchronizing signal A, and holds it at the output (e).

When the input synchronization signal changes to load at point (f), the D-flip-flop circuit (7) changes the level of the input synchronization signal A (
g) is read, and the output changes as shown in (h).

The delay between (f) and (h) is approximately the same as the pulse width T1 of the monomulti circuit (8). When the polarity returns to positive again at point (i), the level at point (j) is read in the same way, and the output is (
k). The delay between (i) and (k) in this case is also T□.

[Effects of the Invention] As described above, according to the present invention, the polarity of the synchronization signal can be determined stably and at high speed.

The range of applications for information transmission using the polarity of synchronization signals will be expanded. Such use makes it possible to add functionality at low cost to a system that uses synchronous signals without adding new signals or lines.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is a circuit diagram showing a conventional polarity discrimination circuit. In the figure, (6) is an exclusive OR circuit, and (7) is a first
(8) is a second multivibrator, A is an input synchronization signal, B is a polar output, C is an output synchronization signal, and D is a pulse output. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (3)

[Claims] (1) An input synchronization signal consisting of a positive polarity signal with a low level in steady state and a high synchronization pulse and a negative polarity signal with a high level in steady state and a low synchronization pulse is input to one input terminal, and depending on the polarity a first multivibrator that derives a polarity output according to the synchronization pulse; an exclusive OR circuit that receives the polarity output of the first multivibrator and the input synchronization signal and derives an output synchronization signal according to the synchronization pulse; A second multivibrator is provided which is driven by the output synchronization signal of the OR circuit and derives a pulse output having a width larger than the synchronization pulse width of the input synchronization signal, and the pulse output of the second multivibrator is driven by the synchronization pulse width of the input synchronization signal. A polarity determination circuit for a synchronizing signal, which is input to the other input terminal of a multivibrator. (2) The synchronizing signal polarity determining circuit according to claim 1, wherein the first multivibrator is comprised of a D-flip-flop circuit. (3) The synchronizing signal polarity determination circuit according to claim 1, wherein the second multivibrator is composed of a monomulticircuit.