JPH0237148B2 - DEETADENSOSHISUTEMU - Google Patents

DEETADENSOSHISUTEMU

Info

Publication number
JPH0237148B2
JPH0237148B2 JP20183983A JP20183983A JPH0237148B2 JP H0237148 B2 JPH0237148 B2 JP H0237148B2 JP 20183983 A JP20183983 A JP 20183983A JP 20183983 A JP20183983 A JP 20183983A JP H0237148 B2 JPH0237148 B2 JP H0237148B2
Authority
JP
Japan
Prior art keywords
data
transmission system
transmission line
transmission
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP20183983A
Other languages
Japanese (ja)
Other versions
JPS6093850A (en
Inventor
Kenji Hara
Ikuo Furuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaskawa Electric Corp
Original Assignee
Yaskawa Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaskawa Electric Manufacturing Co Ltd filed Critical Yaskawa Electric Manufacturing Co Ltd
Priority to JP20183983A priority Critical patent/JPH0237148B2/en
Publication of JPS6093850A publication Critical patent/JPS6093850A/en
Publication of JPH0237148B2 publication Critical patent/JPH0237148B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、データ伝送システムに関し、特に工
場自動化(フアクトリー・オートメーシヨン)を
実現するための上位計算機と各制御装置間などの
データ伝送システムに関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transmission system, and particularly to a data transmission system between a host computer and each control device for realizing factory automation. .

〔背景技術〕 かかるデータ伝送システムとしては、信号中か
らクロツクを抽出するようにした単一信号よりな
る伝送方式を用いるシステムが知られている。
[Background Art] As such a data transmission system, a system using a transmission method consisting of a single signal in which a clock is extracted from the signal is known.

例えば、NRZI方式もその一例である。 For example, the NRZI method is one example.

この方式の長所としては、信号線数が少ないの
で、局間距離が長い場合にコスト的に有利である
ということが挙げられる。
An advantage of this system is that it has a small number of signal lines, so it is advantageous in terms of cost when the distance between stations is long.

NRZI方式については特開昭55−89912や特開
昭57−132461に詳しいので、ここでは省略する
が、この方式を用いた伝送システムでは全ての局
の受信部に復調回路(例えばPLL回路)を必要
とするという問題点がある。
The NRZI method is detailed in JP-A-55-89912 and JP-A-57-132461, so I will omit it here, but in a transmission system using this method, a demodulation circuit (for example, a PLL circuit) is installed in the receiving section of every station. The problem is that it is necessary.

第1図に示すような、伝送ライン1に局(モジ
ユールと称しても良い)2が接続される場合の、
具体的回路例を第2図に示す。
When a station (also called a module) 2 is connected to a transmission line 1 as shown in FIG.
A specific example of the circuit is shown in FIG.

第2図において、4がPLL復調部であり、各
局2ごとに、それを備えておかねばならない。
In FIG. 2, 4 is a PLL demodulator, which must be provided for each station 2.

つまり、局間距離が短い場合には、信号線を減
じることによりコストを下げることよりも、むし
ろ復調回路部のコストの方が大きくなつてくる。
In other words, when the distance between stations is short, the cost of the demodulation circuit increases rather than reducing the cost by reducing the number of signal lines.

〔発明の目的〕[Purpose of the invention]

本発明は、このような事情に鑑みてなされたも
のであり、局間を効率良く、しかも低コストで接
続するデータ伝送システムを提供することを目的
とする。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a data transmission system that connects stations efficiently and at low cost.

〔発明の要旨〕[Summary of the invention]

本発明の要旨となるところは、下位局間は一般
的で安価なクロツクとデータが平行して送られる
データ伝送システムとして構成し、これらの下位
局が上位伝送ラインとを結ぶインターフエースモ
ジユールを共有するようにした点にある。
The gist of the present invention is to configure a data transmission system in which a general and inexpensive clock and data are sent in parallel between lower stations, and to install an interface module that connects these lower stations with an upper transmission line. The point is that I decided to share it.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の具体的実施例を説明する。 Hereinafter, specific examples of the present invention will be described.

第3図は、本発明の概念を示すブロツク図であ
る。
FIG. 3 is a block diagram illustrating the concept of the present invention.

1は上位伝送ラインで、信号中からクロツクを
抽出できる形式の伝送信号(NRZI方式、マンチ
エスター方式等)が送られている。
1 is an upper transmission line, and a transmission signal (NRZI system, Manchester system, etc.) in a format that allows the clock to be extracted from the signal is sent.

2は局、3は下位伝送ライン、4はインターフ
エースモジユールである。
2 is a station, 3 is a lower transmission line, and 4 is an interface module.

第4図は本発明の具体的回路例であり、ここで
は半2重(Half−Duplex)バス方式としている。
第4図を用いて、具体的動作を説明する。
FIG. 4 shows a specific circuit example of the present invention, in which a half-duplex bus system is used.
The specific operation will be explained using FIG. 4.

主局(データ送信局)より、上位伝送ライン1
を通つて信号が送られてくると、ラインドライバ
ー4−aは、PLL回路4−bにデータを入力す
る。
From the main station (data transmitting station), upper transmission line 1
When a signal is sent through the line driver 4-a, the line driver 4-a inputs data to the PLL circuit 4-b.

PLL回路4−bは、信号中よりクロツクを抽
出し、ゲート4−cを通して下位伝送ライン3−
aにクロツクを送出するとともに、データを整型
しゲート4−dを通して下位伝送ライン3−bに
データを送出する。2次局(データ受信局)2
は、RXDに取り込む。このとき下位伝送ライン
3−cは“H”である。2次局2は、データを入
力し終わり自己が応答信号を発するときは、
SEND信号を出力し、下位伝送ライン3−cを
“L”にする。
The PLL circuit 4-b extracts the clock from the signal and passes it through the gate 4-c to the lower transmission line 3-c.
It sends out a clock to the lower transmission line 3-b through the gate 4-d, formats the data, and sends the data to the lower transmission line 3-b. Secondary station (data receiving station) 2
import into RXD. At this time, the lower transmission line 3-c is "H". When the secondary station 2 finishes inputting data and issues a response signal,
Output the SEND signal and set the lower transmission line 3-c to "L".

これによりゲート4−dは閉じ、PLL回路4
−bはFREE RUNとなり、所定の送信クロツク
を下位伝送ライン3−aに送出する。
This closes the gate 4-d, and the PLL circuit 4
-b becomes FREE RUN and sends a predetermined transmission clock to the lower transmission line 3-a.

2次局の送信データTXDは、このクロツクに
よつて下位伝送バス3−bに出力され、アクテイ
ブになつたラインドライバー4−eを通して上位
伝送ライン1に送出される。
Transmission data TXD from the secondary station is outputted to the lower transmission bus 3-b by this clock, and then sent to the upper transmission line 1 through the activated line driver 4-e.

このようにして、上位と下位の伝送ラインが接
続される。
In this way, the upper and lower transmission lines are connected.

なお、上位伝送ラインは光フアイバーケーブル
で構成しても良く、また下位伝送ラインは、フラ
ツトケーブル等で構成できる。
Note that the upper transmission line may be composed of an optical fiber cable, and the lower transmission line may be composed of a flat cable or the like.

つまり、複数の局をひとつの盤内に収納して、
各盤ごとに、ひとつの復調部を備えれば、盤間を
光フアイバーケーブル、盤内をフラツトケーブル
で接続することができる。
In other words, by storing multiple stations in one board,
If each panel is equipped with one demodulator, the panels can be connected by optical fiber cables and the panels can be connected by flat cables.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、高価な復調
部(PLL回路)を複数の局で共有できるので、
低コストで効率の良い、しかも融通性に富んだデ
ータ伝送システムが得られる。
As described above, according to the present invention, an expensive demodulator (PLL circuit) can be shared by multiple stations, so
A data transmission system that is low cost, efficient, and highly flexible can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例の概念図、第2図は従来例の回
路図、第3図は本発明の概念図、第4図は本発明
の具体的実施例である。
FIG. 1 is a conceptual diagram of a conventional example, FIG. 2 is a circuit diagram of a conventional example, FIG. 3 is a conceptual diagram of the present invention, and FIG. 4 is a specific embodiment of the present invention.

Claims (1)

【特許請求の範囲】 1 信号中よりクロツクを抽出することができる
形式の単一信号データの伝送方式で上位伝送シス
テムを構成し、 データとクロツクが並行して送られる形式のデ
ータ伝送方式で下位伝送システムを構成し、 前記上位伝送システム伝送線と前記下位伝送シ
ステムの伝送線を復調部を介して接続し、 下位の各局は、複数局ごとに前記復調部を共有
し、 前記復調部は、単一信号データ形式とデータと
クロツクが並行して送られる形式とを双方向に変
換するとともに、前記下位の各局の発する送信要
求信号で上位側からのデータを下位伝送線への送
出を停止し、その停止期間中も復調部から下位伝
送線へクロツクを送出し、下位の各局はこれを送
信クロツクとすることを特徴とするデータ伝送シ
ステム。
[Scope of Claims] 1. An upper level transmission system is constructed using a single signal data transmission system in which a clock can be extracted from a signal, and a lower level transmission system is constructed using a data transmission system in which data and clocks are sent in parallel. A transmission system is configured, the transmission line of the upper transmission system and the transmission line of the lower transmission system are connected via a demodulation section, each of the lower stations shares the demodulation section for each plurality of stations, and the demodulation section includes: It bidirectionally converts between a single signal data format and a format in which data and clocks are sent in parallel, and stops sending data from the upper side to the lower transmission line in response to a transmission request signal issued by each lower station. A data transmission system characterized in that the demodulator sends a clock to the lower transmission line even during the stop period, and each lower station uses this as a transmission clock.
JP20183983A 1983-10-26 1983-10-26 DEETADENSOSHISUTEMU Expired - Lifetime JPH0237148B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20183983A JPH0237148B2 (en) 1983-10-26 1983-10-26 DEETADENSOSHISUTEMU

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20183983A JPH0237148B2 (en) 1983-10-26 1983-10-26 DEETADENSOSHISUTEMU

Publications (2)

Publication Number Publication Date
JPS6093850A JPS6093850A (en) 1985-05-25
JPH0237148B2 true JPH0237148B2 (en) 1990-08-22

Family

ID=16447743

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20183983A Expired - Lifetime JPH0237148B2 (en) 1983-10-26 1983-10-26 DEETADENSOSHISUTEMU

Country Status (1)

Country Link
JP (1) JPH0237148B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62155645A (en) * 1984-12-17 1987-07-10 Takeshi Nakano Line converter

Also Published As

Publication number Publication date
JPS6093850A (en) 1985-05-25

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