JPS62282464A - Buried channel type thin-film transistor - Google Patents
Buried channel type thin-film transistorInfo
- Publication number
- JPS62282464A JPS62282464A JP12643386A JP12643386A JPS62282464A JP S62282464 A JPS62282464 A JP S62282464A JP 12643386 A JP12643386 A JP 12643386A JP 12643386 A JP12643386 A JP 12643386A JP S62282464 A JPS62282464 A JP S62282464A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate insulating
- region
- film
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 10
- 239000010408 film Substances 0.000 claims abstract description 34
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 abstract description 11
- 239000000969 carrier Substances 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 230000006866 deterioration Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
（産業上の利用分野）
アクティブマトリクス型液晶表示装置などに用いられる
非晶質半導体を使った薄膜トランジスタにおいて、その
使用時の経時特性劣化を軽減しデバイスの信頼性を向上
させる構造に関する。[Detailed description of the invention] 3. Detailed description of the invention (industrial application field) Reducing deterioration of characteristics over time during use in thin film transistors using amorphous semiconductors used in active matrix liquid crystal display devices, etc. and structures that improve device reliability.
（発明の概要）
この発明は、経時特性劣化の土原因と目されるゲート絶
縁膜内特に表面近傍にあるトラップ単位への電荷のトラ
ップげ現象を軽減する目的で、実質的なチャンネル領域
とゲート絶縁膜との間にごく薄いブロッキング領域（本
発明の場合チャンネル領域へａ−３ｉ：Ｈを使用するこ
とを仮定し、ブロッキング領域にａ−８ｉ：Ｈよりバン
ドギャップの広いａ−３Ｌ：Ｃ：Ｈを用いた）を挟み込
んだ形にすることにより、実質的なチャンネルを埋込み
型とした。(Summary of the Invention) This invention aims to reduce the phenomenon of charge trapping in trap units in the gate insulating film, especially near the surface, which is thought to be the cause of deterioration of characteristics over time. A very thin blocking region between the insulating film (in the case of the present invention, it is assumed that a-3i:H is used for the channel region, and the blocking region is a-3L:C: which has a wider band gap than a-8i:H). By sandwiching the channels (using H), the substantial channel was made into a buried type.
（従来の技術）
液晶表示装置の分野などでは、非晶質半導体（例えばア
モルファスシリコン）を用いた薄膜トランジスタ（以下
ＴＰＴと称す）を画素ごとのスイッヂング素子として用
い、幾分か１駆動、高コントラスト比の期待できる液晶
パネルを実現する目的で開発が進められている。前記ア
モルファスシリコンＴＰＴの基本的な構造としては、第
２図に示される様に、絶縁基板１１の上にゲート領域１
２を選択的に形成した後ゲート絶縁膜１３を全面に堆積
させ、ざらにその上に選択的にアモルファスシリコンＩ
！１１４と不純物添加されたアモルファスシリコン１５
を連続して形成した後、ソース・ドレイン領域１６を選
択的に形成しその領域をマスクとして前記不純物添加さ
れたアモルファスシリコン１５の一部を選択除去して出
来る構造が一般的である。(Prior Art) In the field of liquid crystal display devices, thin film transistors (hereinafter referred to as TPTs) using amorphous semiconductors (e.g. amorphous silicon) are used as switching elements for each pixel, and have a somewhat single drive and high contrast ratio. Development is progressing with the aim of realizing a liquid crystal panel that can provide promising results. The basic structure of the amorphous silicon TPT is as shown in FIG.
2 is selectively formed, a gate insulating film 13 is deposited on the entire surface, and amorphous silicon I is selectively deposited roughly on top of the gate insulating film 13.
! 114 and impurity-doped amorphous silicon 15
A typical structure is obtained by sequentially forming amorphous silicon 15, selectively forming source/drain regions 16, and selectively removing a portion of the impurity-doped amorphous silicon 15 using the regions as a mask.
但しこのようにして作成されたＴＰＴにおいて、基板に
は一般的にガラスが用いられるため工程温度は比較的低
温（３００℃程度）に押さえられていることが多い、こ
の際前記ゲート絶縁ＩＦＪ１３内及びアモルファスシリ
コン１４との界面には多くの固定電荷とともにトラップ
準位が存在することは良く知られており、前記トラップ
準位への電荷のトラップが原因と考えられる電流能力の
劣化現象が観察される。However, in the TPT created in this way, since glass is generally used for the substrate, the process temperature is often kept at a relatively low temperature (about 300°C). It is well known that a trap level exists along with many fixed charges at the interface with the amorphous silicon 14, and a phenomenon in which the current capacity deteriorates is observed, which is thought to be caused by the trapping of charges in the trap level. .
（発明が解決しようとする問題点）
非晶質半導体層ＦＴは、前述のごとく原則的に４００℃
以下の低温プロセスにおいて作成される場合がほとんど
で、その際前記ゲート絶縁ＩＩ！！１３（例えば窒化シ
リコン）は多層の表面固定電荷（例えば１０１２個／平
方センチメートル程度）と同時に寿命の比較的長い（例
えば常温で１０４秒以上）トラップ準位をもまた多口に
含んでる。このＴＰＴを動作させておくと、チャンネル
領域１４特にゲート絶縁膜との接触境界に近いところに
誘起されたキャリアが、ゲート領域に印加されている電
界に容易に加速され前記ゲート絶縁膜１３内のトラップ
単位にトラップされる。ゲート絶縁膜１３内にトラップ
された電荷はゲート領域に印加されている電界をチャン
ネル領域から克て相対的に減少させ、能力低下をもたら
す。この現象は、駆動トランジスタとしては決定的な短
所で、連続動作に用いるデバイスとしては使用できない
場合がある、液晶パネルなどに内蔵される駆動回路には
現状のまま使用することはできない。(Problems to be solved by the invention) As mentioned above, the temperature of the amorphous semiconductor layer FT is basically 400°C.
In most cases, the gate insulation II! ! No. 13 (for example, silicon nitride) contains multiple layers of surface fixed charges (for example, about 1012 charges/cm2) and a large number of trap levels with relatively long lifetimes (for example, 104 seconds or more at room temperature). When this TPT is operated, carriers induced in the channel region 14, especially near the contact boundary with the gate insulating film, are easily accelerated by the electric field applied to the gate region, and the carriers in the gate insulating film 13 are easily accelerated by the electric field applied to the gate region. Trapped in units of traps. The charges trapped in the gate insulating film 13 overcome the electric field applied to the gate region from the channel region and relatively decrease, resulting in a reduction in performance. This phenomenon is a decisive disadvantage as a drive transistor, and it may not be possible to use it as a device for continuous operation, and it cannot be used as it is in a drive circuit built into a liquid crystal panel or the like.
（問題点を解決するための手段）
本発明は、前述の問題点を解決するために、非晶質半導
体を用いたＴＰＴのチャンネル領域をゲート絶縁膜と接
触している面に３００Å以下のａ−３ｉ：Ｃ：Ｈ，その
上に実質的なチャンネル領域として一層以上の非晶質半
導体（例えばａ−＆：Ｈ）を積層させ、実質的なチャン
ネル領域を埋込みチャンネル型とすることによって、ゲ
ート絶縁膜内及び界面への電荷のトラップを軽減しデバ
イスの経時特性劣化を防止する。(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a channel region of a TPT using an amorphous semiconductor with an a -3i:C:H, on which one or more amorphous semiconductors (for example, a-&:H) are stacked as a substantial channel region, and the substantial channel region is made into a buried channel type. This reduces charge trapping within the insulating film and at the interface, and prevents deterioration of device characteristics over time.
（作用）
ａ−３ｉ二Ｃ：Ｈは、ａ−３ｉ：’Ｈに比べて充分広い
バンドギャップを有するためゲート絶縁膜とａ−シ二１
１の界面に挿入すれば、ａ −Ｓｒ ： Ｈの界面付近
に５吊に誘起されたキャリアが加速されゲート絶縁膜内
のトラップ準位に容易にトラップされるのを防ぐための
ブロッキング′Ｘｒ４１４として働く、またＳｉ ０２
のように８−３４：Ｈと極端にバンドギャップが異なる
ということはなく窒化シリコンとａ−８１の中間に位置
するためａ −８Ｌ： Ｈとの境界に歪を生じることは
少なく、新たなトラップ学位の増大にはつながらない。(Function) Since a-3i2C:H has a sufficiently wide bandgap compared to a-3i:'H, it is difficult to connect the gate insulating film with a-3i2C:H.
If it is inserted into the interface of Working again Si 02
The band gap is not extremely different from that of 8-34:H, and it is located between silicon nitride and a-81, so strain is unlikely to occur at the boundary with a-8L:H, creating new traps. It does not lead to increased degrees.
（実施例） 以下にこの発明の実施例を図面にもとづいて説明する。(Example) Embodiments of the present invention will be described below based on the drawings.
第１図において、絶縁基板１の上にゲート領域２を選択
的に形成した後ゲート絶縁膜３を全面に堆積させるまで
の工程は従来の構造に準じ、その上に連続形成により複
数の薄膜を堆積するわけだが、その際前記ゲート絶縁膜
３と直接接触する面に３００Å以下の極薄いａ−３ｉ：
Ｃ：Ｈ７をまず堆積させてから、従来のチャンネル領域
にあたる埋込みチャンネル領域４、不純物添加された非
晶質半導体層５を形成し選択的に除去する、その後ソー
ス・ドレイン領域６を選択的に形成しその領域をマスク
として前記不純物添加された非晶質半導体層５の一部を
選択除去してできる構造になっている。次に第３図は本
発明のＴＰＴにおけるゲート領域−ゲート絶縁膜−チャ
ンネル領域（ブロッキング領域と埋込みチャンネル領域
の多層構造）のエネルギーバンド図で、それぞれゲート
領ｔａａ、ゲート絶縁膜ｂ、ブロッキング領１ｉＩＣ１
埋込みチャンネル領域ｄで成り立っている、ゲート領［
ａとブロッキング領域Ｃ及び埋込みチャンネル領域ｄの
仕事関数の差及びゲート絶縁膜内の固定電荷１０の影響
で、ゲート領［ａに電界を印加しない場合でもゲート領
域ａと埋込みチャンネル領域ｄとの間には電位差が生じ
ている。埋込みチャンネル領域ｄの一部に誘起されたキ
ャリア８はブロッキング領［Ｃのエネルギーポテンシャ
ル障壁のために容易にゲート絶縁膜す内のトラップ準位
９にトラップされることはない。In FIG. 1, the process from selectively forming a gate region 2 on an insulating substrate 1 to depositing a gate insulating film 3 on the entire surface is similar to the conventional structure, and a plurality of thin films are sequentially formed thereon. At that time, an extremely thin layer of a-3i of 300 Å or less is deposited on the surface that is in direct contact with the gate insulating film 3:
C: H7 is first deposited, then a buried channel region 4 corresponding to a conventional channel region, an amorphous semiconductor layer 5 doped with impurities are formed and selectively removed, and then source/drain regions 6 are selectively formed. The structure is formed by selectively removing a portion of the impurity-doped amorphous semiconductor layer 5 using that region as a mask. Next, FIG. 3 is an energy band diagram of gate region-gate insulating film-channel region (multilayer structure of blocking region and buried channel region) in TPT of the present invention, and shows gate region taa, gate insulating film b, and blocking region 1iIC1, respectively.
The gate region [
Due to the difference in work function between a, the blocking region C, and the buried channel region d, and the influence of the fixed charge 10 in the gate insulating film, the difference between the gate region a and the buried channel region d occurs even when no electric field is applied to the gate region [a]. There is a potential difference between the two. The carriers 8 induced in a part of the buried channel region d are not easily trapped in the trap level 9 in the gate insulating film because of the energy potential barrier of the blocking region [C].
（発明の効果）
この発明は以上説明したように、実質的なブヤンネル領
域を埋込みチャンネルとしゲート絶縁膜との間に、キャ
リアのトラップを防止するブロッキング領域としてａ−
３ｉ：Ｃ：Ｈを挟む形にすることによってゲート絶縁膜
内及び界面への電荷のトラップを軽減し、デバイスの経
時特性劣化を改善することができる。またチャンネル領
域の連続薄膜形成は、同一チャンバ内で行なわれるため
ガスの切り換えだけで対応できコストアップになる要因
はない。また本発明の実施例はスタガ型の構造で説明し
たが、ゲート絶縁膜とチャンネル領域の間にブロッキン
グ領域を挿入することが主旨であるので、逆スタガ型や
コブラナー型でも同様の効果が得られることは言うまで
・もない。(Effects of the Invention) As described above, the present invention uses a substantial Bouyannel region as a buried channel and a blocking region between the gate insulating film and the gate insulating film to prevent trapping of carriers.
By sandwiching 3i:C:H, charge trapping within the gate insulating film and at the interface can be reduced, and deterioration of characteristics over time of the device can be improved. Furthermore, since the continuous thin film formation in the channel region is performed in the same chamber, it can be handled by simply switching the gas, and there is no cause for increased costs. Furthermore, although the embodiments of the present invention have been explained using a staggered structure, the main idea is to insert a blocking region between the gate insulating film and the channel region, so the same effect can be obtained with an inverted staggered structure or a cobraner structure. Needless to say.
第１図は、本発明にかかるＴＰＴの縦断面図、第２図は
、従来のＴＰＴの縦断面図、第３図は本発明のＴＰＴに
おけるゲート領域−ゲート絶縁膜−チャンネル領域のエ
ネルギーバンド図である。
１・１１・・・絶縁基板
２・１２・・・ゲート領域
３・１３・・・ゲート絶縁膜
４・・・埋込みチャンネル領域
５・１５・・・不純物添加された非晶質薄膜層６・１６
・・・ソース・ドレイン領域
７ ・ａ −８Ｌ： Ｃ： １−１
８・・・誘起されたキャリア
９・・・ゲート絶縁膜内のトラップ準位１０・・・ゲー
ト絶縁膜内の固定電荷
１４・・・チャンネル領域
ａ・・・ゲート領域
ｂ−・・ゲート絶縁膜
Ｃ・・・ブロッキング領域
ｄ・・・埋込みチャンネル領域
３３図FIG. 1 is a vertical cross-sectional view of the TPT according to the present invention, FIG. 2 is a vertical cross-sectional view of a conventional TPT, and FIG. 3 is an energy band diagram of the gate region-gate insulating film-channel region in the TPT of the present invention. It is. 1.11... Insulating substrate 2.12... Gate region 3.13... Gate insulating film 4... Buried channel region 5.15... Impurity-doped amorphous thin film layer 6.16
... Source/drain region 7 ・a -8L: C: 1-1 8 ... Induced carriers 9 ... Trap levels in the gate insulating film 10 ... Fixed charges in the gate insulating film 14 ...Channel region a...Gate region b...Gate insulating film C...Blocking region d...Buried channel region 33 diagram
Claims (1)
したゲート絶縁膜、さらにその上に選択的に設けられた
非晶質半導体層を含むチャンネル領域と不純物添加され
た非晶質半導体膜を介してその上に形成されたソース・
ドレイン領域を有する薄膜トランジスタにおいて、該チ
ャンネル領域はゲート絶縁膜と接触する面に３００Å以
下のａ−Ｓｉ：Ｃ：Ｈを挟んだ形の２層以上の薄膜によ
って構成されていることを特徴とする埋込みチャンネル
型薄膜トランジスタ。1) A gate region provided on an insulating substrate, a gate insulating film deposited thereon, a channel region including an amorphous semiconductor layer selectively provided thereon, and an amorphous semiconductor film doped with impurities. The source formed on it through
In a thin film transistor having a drain region, the channel region is composed of two or more thin films sandwiching a-Si:C:H of 300 Å or less on the surface in contact with the gate insulating film. Channel type thin film transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12643386A JPS62282464A (en) | 1986-05-30 | 1986-05-30 | Buried channel type thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12643386A JPS62282464A (en) | 1986-05-30 | 1986-05-30 | Buried channel type thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62282464A true JPS62282464A (en) | 1987-12-08 |
Family
ID=14935072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12643386A Pending JPS62282464A (en) | 1986-05-30 | 1986-05-30 | Buried channel type thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62282464A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02218166A (en) * | 1989-02-17 | 1990-08-30 | Toshiba Corp | Thin film transistor |
| JPH02284472A (en) * | 1989-04-25 | 1990-11-21 | Nec Corp | Thin film transistor |
| JPH0334457A (en) * | 1989-06-30 | 1991-02-14 | Semiconductor Energy Lab Co Ltd | Field effect semiconductor device |
| US5821559A (en) * | 1991-02-16 | 1998-10-13 | Semiconductor Energy Laboratory Co., Ltd. | Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors |
| US5894151A (en) * | 1992-02-25 | 1999-04-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having reduced leakage current |
| US6028333A (en) * | 1991-02-16 | 2000-02-22 | Semiconductor Energy Laboratory Co., Ltd. | Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors |
| US6709907B1 (en) | 1992-02-25 | 2004-03-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a thin film transistor |
-
1986
- 1986-05-30 JP JP12643386A patent/JPS62282464A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02218166A (en) * | 1989-02-17 | 1990-08-30 | Toshiba Corp | Thin film transistor |
| JPH02284472A (en) * | 1989-04-25 | 1990-11-21 | Nec Corp | Thin film transistor |
| JPH0334457A (en) * | 1989-06-30 | 1991-02-14 | Semiconductor Energy Lab Co Ltd | Field effect semiconductor device |
| US5821559A (en) * | 1991-02-16 | 1998-10-13 | Semiconductor Energy Laboratory Co., Ltd. | Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors |
| US6028333A (en) * | 1991-02-16 | 2000-02-22 | Semiconductor Energy Laboratory Co., Ltd. | Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors |
| US5894151A (en) * | 1992-02-25 | 1999-04-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having reduced leakage current |
| US6709907B1 (en) | 1992-02-25 | 2004-03-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a thin film transistor |
| US7148542B2 (en) | 1992-02-25 | 2006-12-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of forming the same |
| US7649227B2 (en) | 1992-02-25 | 2010-01-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of forming the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4372993B2 (en) | Manufacturing method of active matrix liquid crystal display device | |
| JPH06148685A (en) | Liquid crystal display device | |
| US5658808A (en) | Method of fabricating polycrystalline silicon thin-film transistor having symmetrical lateral resistors | |
| JPS62282464A (en) | Buried channel type thin-film transistor | |
| WO2019051864A1 (en) | Method for manufacturing active array switch | |
| WO2021041060A1 (en) | Hydrogen trap layer for display device and the same | |
| JPH06196703A (en) | Thin film transistor and manufacture thereof | |
| JPS62200767A (en) | Mos-type semiconductor device | |
| JPH01218070A (en) | Mos transistor | |
| CN100373633C (en) | Asymmetric thin-film transistor structure | |
| JPS61224360A (en) | Manufacture of field effect transistor | |
| KR0179066B1 (en) | Thin film transistor and manufacturing method of the same | |
| JPH04240733A (en) | Manufacture of thin film transistor | |
| JP2638685B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS6344769A (en) | Field effect transistor and manufacture of the same | |
| JP2856603B2 (en) | Method for manufacturing semiconductor device | |
| JP3075799B2 (en) | Method for manufacturing semiconductor device | |
| KR960014460B1 (en) | Manufacturing method for a semiconductor device | |
| JPH06132535A (en) | Film transistor and its manufacture | |
| KR100338090B1 (en) | Method for manufacturing semiconductor device | |
| KR100222898B1 (en) | Thin film transistor and method for manufacturing the same | |
| KR100399965B1 (en) | Method for forming storage node contact of semiconductor device | |
| JP2746500B2 (en) | MOS transistor | |
| JPH11186557A (en) | Semiconductor device and manufacture thereof | |
| JP2709214B2 (en) | Method for manufacturing thin film transistor |