JPS62281508A - Signal processor - Google Patents

Abstract

PURPOSE:To improve the S/N of a signal and waveform distortion by adopting the constitution that the 1st and 2nd basic circuits having a transfer function approximated by a specific function are connected in cascade to form a basic circuit and a means is used to form the titled unit combining the input signal via the basic circuit and the input signal not through the basic circuit in a prescribed ratio. CONSTITUTION:The 1st basic circuit 10 has a transfer function approximated by functions expressed in equation 1 or 2, where omegais an angular frequency of an input signal, T is a constant having the unit of time, and (k) is a constant. The 2nd end basic circuit 20 is constituted by connecting time axis conversion circuits 200, 300 before and after the circuit 10 in cascade. The circuits 10, 20 are connected in cascade to constitute the basic circuit 100. The input signal Si through the circuit 100 and a coefficient device 33 and the input signal not through them are added by an adder 34 and the said both signals are combined in a prescribed ratio to obtain an output signal So. Thus, a pre-emphasis circuit whose phase characteristic is linear emphasizing the amplitude of the signal at a middle or a high frequency and a de-emphasis circuit having an opposite amplitude characteristic to the amplitude characteristic of the pre-emphasis circuit and whose phase characteristic is matched with the said circuit over a wide frequency range are realized in this way.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a device for converting a signal such as a video signal into a signal having desired frequency characteristics, and particularly relates to a device for converting a signal such as a video signal into a signal having desired frequency characteristics, and particularly for converting a signal such as a video signal into a signal having desired frequency characteristics. The present invention relates to a signal processing method and apparatus suitable for improving the S/N and waveform distortion of a signal.

[Conventional technology]

In recording and reproducing devices such as video tape recorders and video disc players that record and reproduce video signals, and in signal transmission media such as satellite broadcasting, it is common to transmit (or record and reproduce) video signals at frequency f (pM). It is used in many ways.

In order to prevent the S/N of the signal received in such an FM transmission system from decreasing, so-called pre-emphasis is applied in advance to emphasize the high-frequency components of the modulated signal, and so-called de-emphasis is applied to suppress the high-frequency components after demodulating the FM signal. Conventionally, signal processing methods have been commonly used.

In such a signal processing method, in order to faithfully transmit the signal, the transfer function of the pre-emphasis circuit that emphasizes the high-frequency components of the signal described above must be used. When the transfer function of the de-emphasis circuit is Gt(5), the following equation must be satisfied regardless of one frequency.

Gl (S) X Gt (5) = k
・・・・・・・・・・Tap・+11 However, S=jω, and ω is the angular frequency of the signal.

k is a constant.

If this formula (1) b'- is not satisfied, phase distortion and amplitude distortion will occur in the transmitted (or recorded and reproduced) signal,
The reproduced signal will be distorted. this(
As pre-emphasis circuits and de-emphasis circuits that satisfy equation 1), circuit networks whose respective transfer functions are given by the following have been widely used since they can be easily and economically realized using resistors and capacitors.

However, this conventional method does not take into account the phase characteristics of the emphasis circuit and de-emphasis circuit.

Regarding the method of improving the phase characteristics of the above-mentioned emphasis circuit, please refer to JP-A-53-13+EN4 and JP-A-56-13.
1815 and Japanese Patent Publication No. 61-8632 are well known, but these methods do not give sufficient consideration to the de-emphasis method that satisfies the above-mentioned formula +11.

Regarding a method for improving the S/N of a signal using an emphasis circuit expressed by the above equation (2), Japanese Patent Application Laid-Open No. 59-221
126 and JP-A No. 60-7279 are well known, but none of these methods takes into account the linearity of the phase characteristic of the emphasis circuit itself in equation (2) above.

[Problem that the invention seeks to solve]

In the above conventional method, as is obvious from the above equation (2), the linearity of the phase characteristic of the emphasis circuit is poor. If a large level of overshading and undershoot occurs only in the direction, and if frequency modulation is performed using this as a modulation signal, the amount of frequency deviation will increase accordingly, the occupied band of the FM signal will increase, and a wider transmission band will be used. There are issues that require it. In recording and reproducing apparatuses such as the video tape recorder and video disc player described above, there is naturally a limit to the signal band that can be recorded on the medium. In the conventional pre-emphasis method described above, a large peak waveform in one direction occurs for the high-frequency components of the signal, so when overshooting occurs, the instantaneous frequency of the FM signal becomes extremely high, and the band limit of the medium causes a high frequency. It becomes impossible to reproduce the FM signal at a sufficient level, resulting in a so-called inversion phenomenon (black horizontal noise occurs at the edge of the video signal where it changes from black to white), and undershoot occurs when the FM signal The instantaneous frequency of the image becomes extremely low, and so-called spectral folding causes beat-like noise at the image contour, which significantly deteriorates the reproduced image quality. To prevent this, it is common to configure the overshoot and undershoot waveforms of the signal after emphasis to be forcibly clipped (amplitude limited), but this waveform clipping causes part of the signal to As a result, the above equation (1) no longer holds true, and there is a problem that the reproduced waveform is severely distorted. Furthermore, in order to prevent this, a method is generally used in which the amount of emphasis is reduced or the amount of frequency shift is reduced. However, although the waveform distortion may be improved, the S
The essential problem of deterioration of /N remains.

The object of the present invention is to eliminate the drawbacks of the prior art described above,
), provides an emphasis circuit and a de-emphasis circuit that can satisfy the equation, have good linearity of one-phase characteristics, do not cause amplitude distortion or phase distortion, and can increase the amount of emphasis to improve signal SZN. It's about doing.

[Means for solving problems]

In order to achieve the above object, the present invention constructs a ladder network with an inductance L and a capacitance C, so that a hyperbolic tangent function tα (ST) (T is a delay Focusing on the fact that it is possible to realize an impedance circuit Z and an admittance circuit Y, which have an impedance circuit Z6 and an admittance circuit Y, the amplitude characteristics of the impedance circuit Z6 and the admittance circuit Y can be expressed as -32(ωT )) Or (1+Kz ・sfn”
(ωT)) (Z, , z is a constant), constitutes a pre-emphasis circuit with a linear phase characteristic (that is, a flat group delay characteristic), and also uses the impedance circuit Z or admittance circuit Y described above. , the amplitude characteristic is an inverse function of the amplitude characteristic of the above pre-emphasis circuit (++2.・possible 2(
By configuring a de-emphasis circuit having linear phase characteristics, which has ωT)) or '/(++z,・2(ωT)), a signal processing device that satisfies the above equation +1) is realized. This is the first feature.

A second feature of the present invention is that the first pre-emphasis circuit composed of the impedance circuit Z or the admittance circuit Y is provided with a function G expressed by the above equation (2).
A second pre-emphasis circuit having 1(5) is connected in cascade and is also connected to the first de-emphasis circuit constituted by the impedance circuit Z or admittance circuit Y as expressed by the above equation (2). Function Gt (s
The second de-emphasis circuit is configured to be connected in series.

A third feature of the present invention is that the pre-emphasis circuit or de-emphasis circuit is configured by a digital filter using distal signal processing means.

[Effect]

The first pre-emphasis circuit has an amplitude characteristic of '/(
++x,, U2(ωT)) or (++z2・m”
(ωT )l''), it operates to emphasize the level of the mid-range component or high-range component of the human input signal
Moreover, since its phase characteristic is near IJ, an output waveform that maintains the waveform symmetry b'' of the input signal can be obtained.More specifically, for the above-mentioned rectangular pulse signal, Before and after each descending edge, produce a preroot and a boost shoot oddly symmetrically at approximately the same peak level.In this way, the high-frequency components of the input signal are emphasized at the rising and falling edges of the signal. Because it is almost evenly distributed as a print sheet and a post sheet in the front and back,
The peak value (peak-to-peak value) is significantly smaller than that of the conventional emphasis method, where the phase characteristic shown by equation (2) above is not linear. Therefore, when performing FM transmission, the transmission band can be In addition, it is possible to suppress the occurrence of beat noise due to the inversion phenomenon and spectrum folding due to overmodulation described above, and there is no need to forcibly clip the waveform after emphasis, so waveform distortion can be avoided. do not have.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a basic circuit TOO for configuring a pre-emphasis circuit or a de-emphasis circuit according to an embodiment of the present invention.

Transfer function F of this basic circuit 100. <s), the signal supplied to input terminal 1 is Vi, and the signal output from output terminal 2 is V. It is given by the following equation.

FG(5)=-=□□ ・・・・・・(3)Vi
I-(&-tanhθ)2 However, θ=sr=)ωT, and T corresponds to the delay time and is a constant. Further, k is also a constant.

This basic circuit 100 has a transfer function p+ expressed by the following equation.
<s) and a transfer function 12 (
S) and the second basic circuit 20 having the basic circuit S) are connected in cascade.

From this, the transfer function FO(5) of the basic circuit 100 can be expressed by the following equation using the transfer functions F, (5) and F2C5> of the two first and second basic circuits 10.20.

Fo (S) -F+ (s) XFz (S)
・・・・・・・・・・・・・・・・・・・・・(5) Second
The figure shows a four-terminal circuit network showing one embodiment of the first basic circuit 10 described above. In the figure (α), 11 indicates an impedance circuit 2, and 13 indicates a resistor R1. In the same figure (bl), 14 resistances R, +2 indicate an admittance circuit Y. The above impedance circuit Z and admittance circuit Y are two-share circuits that are actually marked by the hyperbolic tangent function tαnhθ. is given by the following formula, with the basic switching resistance being R8.

The two-terminal circuit networks 11 and 12 that approximately realize these Z and Y values are as described in the document (Japanese Patent Publication No. 6G-5548!S) disclosed by the inventor.
An LC ladder network having the configuration shown in FIG. 5 is known. For reference, in (, 1 and (b) of Figure 3, the above (6)
) The values of inductance L and capacitance C to satisfy the equation are given by the following equations. For the impedance 2 in FIG. 3(α), and for the admittance Y in FIG. 3(S), however, the value is an integer greater than or equal to 1.

In the four-terminal network 10 shown in FIG. 2 (α), the input terminal V
The transfer function F, (5) of the output voltage V with respect to l can be expressed by the following equation using the above equation (6).

=□ ・・・・・・・・・(9) 1 + (Ro /B) ・tankθ From this, k
= Ro/R1, one function F1 of the above equation (4)
(S), and this function has been realized. Similarly, as shown in FIG.
is expressed by the following formula using the above formula (6), =□ ......α mouth 1 + (Rx / R,) ・tanhθ Therefore, k
; If R2/R0, then the functions p, (s) of the above equation (4)
This means that this function has been realized.

Next, the other function FtC5) of the above equation (4), that is, an embodiment for realizing the second basic circuit 20 shown in FIG.
As shown in the figure.

Generally, regarding the hyperbolic tangent function, tanh (−〇) = −tanh (θ)9010
39.1510098111. Since αυ holds true, if we transform θ→−θ (that is, S→−5) in the above equation (4), Ft(−5)=□ 1− becomes −tα1hθ = pt <s> ・・・・・－・・・・・・－・
It is clear that α2 holds true. Fourth
Based on this, the illustrated embodiment performs a conversion of S→-5 (so-called time axis conversion) and then filters the function F! (
5) (that is, the second basic circuit 20).

In FIG. 4, 21 is an input terminal for the signal Ei, and 22 is the signal E processed by the circuit 20. This is the output terminal of Reference numeral 200 denotes a time axis conversion circuit that converts the time axis of the input signal Ei so that it has a time series in the opposite direction. The time axis conversion circuit 200 is composed of a memory for time axis buffering, and converts the input signal Ei in appropriate unit periods. For example, when a video signal is input as the signal Ei, the unit period is the horizontal direction of the video signal. Data is sequentially written to the memory at the scanning period or an integer multiple thereof, or at the field period or frame period, which is the vertical scanning period of the video signal, and after the writing is completed, data is written every unit time in the reverse order of the writing order. Reads and outputs sequentially from memory. The time series is converted in the opposite direction by this time axis conversion, and the signal output from the circuit 200 is generated by the first basic circuit having the transfer function Fl(S) realized in the embodiment shown in FIG. After the filter processing is performed in step 10, the time axis is again converted into the reverse time series in the time axis conversion circuit 300. This time axis conversion circuit 300 is composed of a memory for time axis buffering, similar to the circuit 200 described above, and is similar to the circuit 200 described above.
The output signals from the memory are sequentially written into the memory every unit cycle, and after the writing is completed, they are sequentially read and output from the memory in the reverse order of the writing order. Therefore, the output signal ε from this time axis conversion circuit 600. 1@L, has the same original correct time series as the input signal Ei. Through the above series of signal processing, the conversion from S→-5 and the functional operation corresponding to Ft(-s) will be performed, and therefore the basic circuit 2o described above will be performed.
The transfer function from the input terminal 21 to the output terminal 22 is equal to Ft (5) as shown in equation 12 above,
This function has been realized.

The first basic circuit IQ realized by the above embodiment
FIG. 5 shows an embodiment of a signal processing circuit 3° that uses all of the basic circuit 100 shown in FIG.

In the figure, the signal Si input to the terminal j1 is as described above (
3) Transfer function F of Eq. (5) and is also input to the + side input terminal of the adder 34.

The output from the basic circuit 100 is passed through the coefficient unit 53 to k.

After being amplified twice, it is supplied to one input terminal of the adder 64. The adder 54 subtracts the input signal Si from the terminal 31 and the output signal from the coefficient multiplier 33, resulting in an output signal S. is output to terminal 32.

With the above configuration, the transfer function y, (5) from the input terminal 31 to the output terminal 32 is given by the following equation.

H+ (S) = I ko -F6 (S) Here, set 0 to the coefficient value of the coefficient multiplier 63 as Ao=I k
・・・・・・・・・・・・・・・・・・・・・
......If α4 is set, the term cos'' (ωT) in the numerator of the above α1 equation disappears, and the transfer function HI(5) of the signal processing circuit 30 is simplified as shown in the following equation. be done.

Alternatively, the frequency characteristics of the signal processing circuit 30 shown in FIG. 5, determined by this transfer function H1(5>), are shown in FIG.

From this, the signal processing circuit 30 can process the middle or high frequency components of the input signal Si when k = 1 (i.e., 2+>0 in the US system). It operates as a pre-emphasis circuit that emphasizes, and when k>1 (that is, the above (2.>0 in the IS formula) is 0, it operates as a de-emphasis circuit that suppresses the middle or high frequency components of the input signal S1. is clear.

Next, FIG. 7 shows a response waveform to a rectangular pulse input signal Si when the signal processing circuit 60 is operated as a pre-emphasis circuit by setting &<I. In the figure, (α) shows the waveform of the input signal Si, and (b) shows the output signal S. The waveform of is shown. In this manner, the response waveform to a rectangular pulse signal produces preshoot and postshoot oddly symmetrically at approximately the same peak level before and after each rising and falling edge of the signal. That is, since the high-frequency components of the input signal Si are almost evenly distributed between the preshoot and postshade by emphasis, the peak-to-peak value of the output signal S0 is equal to the peak-to-peak value of the conventional emphasis shown in equation (2) above. It is smaller compared to the method.

Therefore, the signal S that is processed and output in this way.

When transmitting (or recording and reproducing) by modulating all frequencies, the amount of deviation per frequency can be kept small, so the occupied band of the FM signal can be narrowed accordingly, making it difficult to be subject to restrictions on the transmission band. Furthermore, since overmodulation can be prevented, the occurrence of spurious signals due to inversion phenomena and spectrum folding can be suppressed, and there is no need for forced clipping of the waveform, so that waveform distortion can be prevented.

Next, an embodiment of a signal processing circuit 40 that can be applied complementary to the signal processing circuit 30 to almost completely match the pre-emphasis characteristics Toddier 77 assist characteristics and correctly restore the original signal. is shown in Figure 8.

The circuit shown in FIG. 8 operates as a de-emphasis circuit that suppresses mid-range or high-range components of a signal.

In the figure, 46 is a raised cosine circuit having a linear phase characteristic and a field of view characteristic approximated by a raised cosine characteristic;
4 is a coefficient unit, 45 is an adder, and 90 is a delay unit. Here, one embodiment of the above-mentioned raised cosine circuit 45 is shown in FIG.

In FIG. 9, 11 is the impedance circuit 2 shown in FIG. 6 (α) above, and 12 is the admittance circuit Y shown in FIG. 3 (b) above, which are functions of equation (6) above. It goes without saying that it will be displayed. 15 is a resistor having a value of -RO/2 with respect to the reference resistor R0.

The transfer function ps<s) of the output voltage V2 to the input voltage V of the raised cosine circuit 43 shown in FIG.
) can be expressed as the following equation.

= cm” (ωT)・g-2TS ・・・・・・
・・・・・・・・・・・・・・・α → In Figure 8,
The input signal Si from the terminal 41 is filtered by the raised cosine circuit 45 having the transfer function J'3(S) of the above-mentioned AS type, and the output thereof is amplified by a factor of 1 by the coefficient multiplier 44. The output of the coefficient unit 44 is supplied to one + side input of an adder 45. On the other hand, the input signal Sik from the terminal 41 is input to the delay device 9.
0 and is delayed by time 2T. As is well known, the transfer function D (5) of this delay device 90 can be expressed by the following equation.

() (5) =, -2T S ・・・・・・・・・
The output of the 0 delay device 90 is supplied to the other + side input of the adder 45, and is added to the output from the coefficient multiplier 44 to produce an output signal S. is output to terminal 42.

From the input terminal 41 to the output terminal 4 of the above signal processing circuit 40
The transfer function Hz(S) up to 2 is given by the following equation using the above α-kashi equation and Kan equation.

K2 (5) = D (S) + K1-Fs (S)
= C"f+ ・cas'(ωT) ] , , -2r
s , , , , , , .

FIG. 10 shows the frequency characteristics of the signal processing circuit 40 determined by this transfer function Hz(S). It is clear from this that the signal processing circuit 40 operates as a de-emphasis circuit that suppresses the middle or high frequency components of the input signal Si.

Here, the coefficient unit 44 in this signal processing circuit 40
Match the coefficient value X1 with the value of , in the above αη formula, and
>0 (therefore, k minus 1 from the αη equation), and uses the signal processing circuit 50 shown in FIG. After pre-emphasizing the signal (to be reproduced) by the signal processing circuit 50, the FM
If the system is configured so that the signal is modulated and transmitted (or recorded), the received signal (or reproduced signal) is FM demodulated, and then the signal processing circuit 40 performs de-emphasis to restore the original signal. , the overall transfer characteristic of this transmission system is given by the following equation using the above (US equation and Kan equation).

J(S) x Ht(5) = e-2rs...
・・・・・・・・・・・・・・・・・・・・・C! υ
In other words, the overall transfer characteristics of this system are such that one phase characteristic is near IJ with a constant (2T) transfer time, no equivalent phase distortion occurs, and the amplitude characteristics are constant regardless of frequency. Therefore, the same amplitude distortion does not occur, and therefore the signal can be transmitted extremely faithfully without waveform distortion, and the above-mentioned X.

It is clear that the S/N can be improved by suppressing the noise received on the transmission path in accordance with the amount of emphasis corresponding to the value of .

The above has described an embodiment in which the signal processing circuit 30 is applied as a pre-emphasis circuit, but next, the signal processing circuit 30 is used as a de-emphasis circuit, and signal processing that operates as a pre-emphasis circuit in a complementary manner. One embodiment of circuit 50 is shown in FIG.

In Fig. 8), 55 is a squared sine circuit having a linear phase customization and an amplitude characteristic approximated by a squared sine characteristic, 54 is a coefficient unit, 55 is an adder, and 90 is 9 in Fig. 8 above.
This is the same delay device as 0.

An embodiment of the squared sine circuit 53 is shown in FIG.

In FIG. 12, 11 and 12 are the impedance circuit Z and admittance circuit Y shown in FIGS. 5(α) and (b), respectively. 15 is for the above reference resistance R0,
It is a resistor with a value of Ro / 2. The transfer function F4 (5) of the output voltage V to the input voltage V of the squared sine circuit 530 shown in FIG. 12 can be expressed by the following equation using the above equation (6).

= −−2(ωT)・, −275・・・・・・・・・
......■ In FIG. 11, the input signal Si from the terminal 51 is filtered by the squared sine circuit 55 having the transfer function F4(S) of the above-mentioned formula, and the output thereof is filtered by the coefficient multiplier 54. .

Be amplified twice. The output of the coefficient multiplier 54 is supplied to one side input of an adder 55. On the other hand, the input signal Si from the terminal 51 is delayed by the delay device 90 by a time of 2T.

The transfer function D (5) of this delay device 90 is given by the above dI formula. The output of the delay device 90 is the other + of the adder 55.
The output signal S is supplied to the side input and is subtracted from the output from the coefficient multiplier 54. is output to terminal 52.

From the input terminal 51 to the output terminal 5 of the above signal processing circuit 50
The transfer function H5(S) up to 2 is given by the following equation using the above four equations and α1 equation.

K3 (5) = D (S) -f2・F4(5)=
(1+Kz ・m"(ωT)] ・e−"' ・−
...-E The frequency characteristics of the signal processing circuit 50 determined by this transfer function 13(5) are shown in FIG.

From this, it is clear that the signal processing circuit 50 operates as a pre-emphasis circuit that emphasizes the middle or high frequency components of the input signal Si.

Here, the coefficient unit 54 in this signal processing circuit 50
The coefficient value of xt>
oc Therefore, from αη formula〉1), the above (119
The signal processing circuit 3° shown in FIG. After that, the system performs FM modulation, transmits (or records), demodulates the received signal (or reproduced signal), and then performs de-emphasis 2 by the signal processing circuit 50 to restore the original signal. , the overall transfer characteristic of this transmission system is
Using the above equation (c) and equation 00, it is given by the following equation.

H8(S)XH, (S)=2・t-2TS...
・Song... (Foundation) In other words, the overall transfer characteristics of this system only has a constant (2T) delay time, and the phase characteristics are linear, and no phase distortion will occur. Moreover, since the amplitude characteristics are constant regardless of the frequency, there is no amplitude distortion, and therefore the signal can be transmitted extremely faithfully without waveform distortion, and as mentioned above,
It is clear that the S/N can be improved by suppressing the noise received on the transmission path in accordance with the amount of emphasis corresponding to the value of .

As described above, by complementary applying the signal processing circuit 60 shown in FIG. 5 and the signal processing circuit 40 shown in FIG. 8, or the signal processing circuit 50 shown in FIG. Emphasis characteristics can be almost completely matched.

Furthermore, as shown in Figure 7 above, the pre-emphasized waveform is evenly distributed into the brishade and post-shade by emphasizing the high frequencies of the signal, and the peak-to-peak value of the signal is This is smaller than the conventional emphasis method shown in equation (2). In other words, assuming that the peak-to-peak value of the high-frequency emphasized signal, which is determined by conditions such as the band of the transmission path, is constant, the method of the present invention can increase the amount of emphasis even more than the conventional method. This makes it possible to increase the S/N ratio, and the S/N ratio can be improved accordingly.

The easiest way to increase this amount of emphasis is to increase the coefficient value Kl or
A conventionally known pre-emphasis circuit having the transfer functions Gl(S) and G2(s) of the above equation (2) may be used in combination with the signal processing circuit of the present invention. More specifically, when the signal processing circuit 30 shown in FIG. 5 is operated as a pre-emphasis circuit and this and the signal processing circuit (i.e. de-emphasis circuit) 40 shown in FIG. 8 are applied complementary to each other, , a pre-emphasis circuit having the transfer function Gl(S) of the above equation (2) is connected in cascade with the signal processing circuit 60, and the transfer function G! of the above equation (2) is obtained. (s) A de-emphasis circuit having * is connected in series with the signal processing circuit 40.

Similarly, when the signal processing circuit 30 in FIG. 5 is operated as a de-emphasis circuit, and the signal processing circuit (i.e., pre-emphasis circuit) 5° in FIG. , the transfer function G of the above equation (2),
(5) A pre-emphasis circuit having 'r is connected in cascade with the signal processing circuit 50, and a de-emphasis circuit having the transfer function 02 (5) of the above equation (2) is connected in cascade with the signal processing circuit 60. configured.

According to the above configuration, the time constant 71 and T of the above equation (2).

If is set to a relatively large value, one transfer function Gl(
The pre-emphasis circuit 5) can be used mainly for emphasizing the low range of the signal, and the signal processing circuit 30 or 50 operating as the other pre-emphasis circuit is used mainly for emphasizing the mid-range or high range of the signal. Therefore, the S/N ratio can be improved over a wide frequency range without waveform distortion.

Next, another embodiment of the basic circuit according to the present invention is shown in FIG.

This basic circuit 100' has a transfer function F1 expressed by the following equation.
'(5)' and a transfer function p
t(l) are connected in cascade.

Therefore, the transfer function F≦(S) from the input terminal 1 to the output terminal 2 of the basic circuit 100' is given by the following equation.

F o (s) = p', (s) x bar (S) An embodiment of the third basic circuit 10' is shown in FIG. (α) in FIG. 15 is constructed by replacing the impedance circuit ZU in FIG. It is given by the following equation.

From this, k = Fo7. Then, the above (c)
This matches the function F+'(5) of the equation, and this function has been realized.

Similarly, (a) in Fig. 15 is constructed by replacing the admittance circuit y a2 and the resistor Rza4 in Fig. 2 (6) above, and its transfer function Fl' (S) is given by the following equation. .

Therefore, if k=R2/R0, it matches the function F+'(S) of the above equation (c), and this function has been realized.

Next, the other transfer function p of the above equation (c); (s)ff
16th embodiment of the fourth basic circuit 20' having:
As shown in the figure. 16 is constructed using the third basic circuit 10' in place of the first basic circuit 10 in FIG. 4, and the time axis conversion circuit 200 and 50 in FIG.
0 is exactly the same as that in FIG. 4 above and is indicated by the same reference numeral. By the same operation as described in FIG. 4 above, the basic circuit 20' in FIG. 16 performs the conversion from S→-5 and the functional operation corresponding to 7i', '(-5). , Therefore, the transfer function from the input terminal 21 to the output terminal 22 of the basic circuit 20' is the function F of the above equation (c).
; (5) (= F, 'C-3)),
This function has been realized.

The sixth basic circuit to realized by the above embodiment
' and the fourth basic circuit 20'.
FIG. 17 shows an embodiment of a signal processing circuit 30' using the basic circuit 100' shown in FIG.

This FIG. 17 is constructed using the basic circuit 100' in place of the basic circuit 1000 in FIG. 5, and the other coefficients and adder 34 are exactly the same as those in FIG. 5, All are indicated by the same reference numerals.

From this, the transfer function H+(S) from the input terminal 31 to the output terminal 52 of this signal processing circuit 30' is given by the following equation.

g,' (5) = I -ha -Fo (5) Here, the coefficient value k of the coefficient unit 33. io=+−−...
・・・・・・・・・・・・・・・・・・ If ■ is set to 2, the term th2(ωT) in the numerator of the above equation disappears, and the signal processing circuit 30' Transfer function H1'
(s) is simplified as shown in the following equation.

Or, however, K, = -7-1, K, = A”-1 old story...
(To) The frequency characteristic of the signal processing circuit 60' shown in FIG. 17, which is determined by this transfer function H+'(S), is shown in FIG.

As is clear from a comparison between FIG. 18 and FIG. 6, the signal processing circuit 30' differs from the signal processing circuit 30 only in the value in the DC region (that is, the DC gain).
The basic frequency characteristics are exactly the same, and this signal processing circuit 50' has a preamplifier that emphasizes all middle or high frequency components of the input signal Si. It is clear that the &)+ gate operates as an emphasis circuit and as a de-emphasis circuit that suppresses the middle or high frequency components of the input signal s1.

In the above embodiments, the LC ladder circuit network shown in FIG. It is also possible to use a so-called digital filter.

FIG. 19 shows an embodiment of a digital processing basic circuit 100D in which the basic circuit 100 shown in FIG. 1 is constructed from a digital filter.

In the figure, 3 is an A/D converter, and 4 is a geo-converter. Both 10D1 and 10D2 are digital filters that realize the transfer function FI (5) of equation (4) above, and correspond to the first basic circuit 10 in FIG. 1 above.

Both 200D and 300D are memories composed of RAM and the like, and correspond to the time axis conversion circuits 200 and 600 shown in FIG. The block 20D shown in FIG. 1 corresponds to the second basic circuit 20 in FIG. 1, and the transfer function of this block 20D is given by 12(S) of the above equation (4).

The input signal Vi from the terminal 1 is input to the A/D converter 3 at a sampling period T. The signal is sequentially converted into a digital signal and the output thereof is supplied to a digital filter 10D1. Take note of the output filtered by digital filter 10D1! The data is sequentially written to 7200D every unit period. The signals convoluted in the memory 200D are sequentially read and output every unit cycle in the reverse order to the order of vows. The signal read from memory 200D is filtered by digital filter 10D2. The output from the digital filter 10D2 is sequentially written to the memo 1J500D in each unit period, and the signals written in the memo 1J50[]DiC are read out sequentially in each unit period in the reverse order of the writing order. It will be done. The signal read from Memo 1J300D is converted into an analog signal by VA converter 4 and sent to terminal 2.
It should be output to .

Next, the above digital filter +0D+ (and 10Z)
An example of 2) is shown in FIG.

As a method of converting an analog filter into a digital filter, a method using a linear equation, so-called bilinear Z-conversion, is known.

2 1-Z-” S=-・□ ・・・・・・・・・・・・・・・・・・・
...(B) To I+Z-' However, z = , Sr1 (7o is the sampling period)...(To) Transfer function p of the above equation (4), (S) is the above equation (B) By substituting, we get the following formula.

The embodiment of FIG. 20 has a transfer function equal to p+(Z) in the equation (to) above.

In the figure, 101 is a terminal to which the digital signal from the A/D converter 3 is input, 110 and ) are adders, 112 and 114 are coefficient units, and 111 is a delay unit. The input signal from the terminal 101 is subtracted by the output from the coefficient multiplier 112 at the adder 110. The output from the adder +10 is delayed by N bits (delayed by 2T in time) by a delay device 111. The output from the delay device 111 is amplified by m times in the coefficient multiplier N2, and the output is supplied to the adder 110.

A negative feedback loop is formed by the adder 110, delay device 111, and coefficient device 112 described above.

An adder 115 adds the output from the adder 110 and the output from the delay device 111, and the output is amplified four times by a coefficient multiplier 114. The output from the coefficient multiplier 114 is supplied to the memory 200D via the terminal 102.

The same circuit as shown in FIG. 20 is also applied to the digital filter 10D2 shown in FIG. 19.

With the above configuration, the transfer function from input terminal 1 to output terminal 2 is the function F of the above equation (3). It goes without saying that this is consistent with (5).

The embodiment shown in FIG. 20 has the transfer function F of the above equation (4),
(s).

Similarly, FIG. 21 shows an embodiment of a digital filter having the transfer function p: (S) of the above equation (c).

In FIG. 21, circuits having the same functions and operations as those in FIG. 20 are given the same reference numerals.

115 is an adder, 116 is a coefficient unit, and the adder 115
At , the output from the adder 110 and the output from the delay device 111 are subtracted, and the output is amplified by a factor of R' at the coefficient unit 116.

The transfer function F; (Z) from the input terminal 101 to the output terminal 102 in FIG. 21 is given by the following equation.

The above 0η equation matches the function obtained by substituting the above equation (b) into the transfer function p:<s> of the above equation (c). Therefore,
If the digital filter shown in FIG. 21 is applied in place of the f-isotal filters 10D1 and 10D20 in FIG. ), and the 14th above
A digital processing type basic circuit 100D' corresponding to the figure can be constructed.

Note that the coefficient multiplier 114 shown in FIG. 20 above and the coefficient multiplier 116 shown in FIG. 2j above can be omitted.

The above digital processing type basic circuit +00D, and T
By using OOD', it is possible to construct a digital processing type signal processing circuit corresponding to the above-mentioned FIG. 5 and a digital processing type signal processing circuit corresponding to the above-described @+7 diagram.

Furthermore, digital signal processing circuits corresponding to those shown in FIGS. 8 and 11 can also be easily constructed by using the bilinear transformation of equation (b) above.

〔Effect of the invention〕

As described above, according to the present invention, a signal to be transmitted or recorded/reproduced is converted into a signal having a linear phase characteristic and a desired amplitude characteristic, and in particular, the amplitude of the mid-range or high-frequency range of the signal is emphasized. A comparison of a pre-emphasis circuit with a linear phase characteristic and a de-emphasis circuit with a characteristic opposite to its amplitude characteristic, a linear phase characteristic, and which can be sufficiently matched with the pre-emphasis circuit over a wide frequency range. This can be realized with a simple configuration.

Additionally, these can be easily constructed using digital circuits, increasing the precision and stability of signal processing.
It also facilitates circuit integration. Furthermore, if this is applied to an FM transmission system, the amount of frequency deviation can be minimized without widening the transmission band, and there is no need for waveform clipping to prevent overmodulation, resulting in no waveform distortion. N can be improved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the basic circuit according to the present invention, Fig. 2 is a wiring diagram showing an embodiment of the first basic circuit constituting the basic circuit, and Fig. 3 is a block diagram showing an embodiment of the basic circuit used in the present invention. A wiring diagram showing a specific example of the impedance circuit 2 and the admittance circuit Y shown in FIG.
A block diagram showing an example of a basic circuit; FIG. 5 is a block diagram showing an example of a signal processing circuit configured with the basic circuit; FIG. 6 is a characteristic diagram showing amplitude characteristics of the signal processing circuit;
FIG. 7 is a waveform diagram showing the response waveform of the signal processing circuit, and FIG.
9 is a block diagram showing another embodiment of the signal processing circuit of the present invention, and FIG. 9 is a wiring diagram showing one embodiment of a raised cosine circuit constituting the signal processing circuit. FIG. 10 is a diagram showing the amplitude of the signal processing circuit. Characteristic diagrams showing characteristics FIG. 11 is a block diagram showing another embodiment of the signal processing circuit of the present invention, FIG. 12 is a wiring diagram showing one embodiment of the squared sine circuit constituting the signal processing circuit, and FIG.
Figure 5 is a characteristic diagram showing the amplitude characteristics of the signal processing circuit;
15 is a block diagram showing another embodiment of the basic circuit according to the present invention, FIG. 15 is a wiring diagram showing an embodiment of the third basic circuit constituting the basic circuit, and FIG. 16 is a block diagram showing the basic circuit configuring the basic circuit. 17 is a block diagram showing an example of a signal processing circuit configured with the basic circuit, and *+S diagram shows the amplitude characteristics of the signal processing circuit. 19 is a block diagram showing an embodiment of a digital processing type basic circuit according to the present invention, FIG. 20 is a block diagram showing an embodiment of a digital filter constituting the basic circuit, and FIG. FIG. 7 is a block diagram showing another embodiment of the digital filter constituting the basic circuit. TOo, 100'・・・・・・・・・・・・・・・
...Song...Basic circuit for drumming 10...
・・・・・・・・・・・・・・・・・・・・・・・・
......First basic circuit 20...
・－・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・Second basic circuit 10'・
・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・Four points 5 basic circuit 20'
・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・−・・・・・・・・・・4th basic circuit 30.40, 50.50'・・・・・・・・・・・・
・・・・・・Moaning signal processing circuit 11・・・・・・−・−・
・・・・・・・・・・・・・・・・・・ Song... River...
...... Impedance circuit 12...
・・・・・・・・・・・・・・・River・・・Song・・・・・・
・・・・・・・・・Admittance circuit 200j00
・・・・・・・・・・・・・・・・・・・・・・・・
......Time axis conversion circuit 55, Ail, 5A
, 112, 114, 116...coefficient machine! 54, 15,
55,110. N3. N5...adder 90, II+
・・・・・・Song・・・・・・・・・・・・・・・Tap・
・・・・・・Delay device agent Patent attorney Masaru Ogawa Male 11 Rowe 2 mouths' T, +<s> “ L−−−−−−−・−−−−−−1 33 mouths (Q) Wataru 4 mouth 2゜Wx (s) J, 5 concave) ζ et al times 17 times - wf.

Claims (1)

[Claims] 1. In a device for converting an input signal into a signal having predetermined frequency characteristics, where ω is the angular frequency of the input signal, T is a constant having a unit of time, and k is a constant, 1/{1 −[k・tanh(jωT)]＾2} or {[k・tanh(jωT)]＾2}/{1−[k・t
Signal processing consisting of a means for synthesizing at a predetermined ratio an input signal that has passed through a basic circuit that has a transfer function approximated by the function anh(jωT)]^2} and an input signal that has not passed through this basic circuit. Device. 2. The above basic circuit is 1/[1+k・tanh(jωT)] or [k・t
anh(jωT)]/[1+k・tanh(jωT)]
a first basic circuit having a transfer function approximated by a function, 1/[1-k・tanh(jωT)] or [-k・
tanh(jωT)]/[1-k・tanh(jωT)
2. The signal processing device according to claim 1, wherein the signal processing device is configured by cascade-connecting a second basic circuit having a transfer function approximated by a function. 3. The above first basic circuit has R_0 as the reference resistance and t
Impedance circuit Z approximated by the function anh(jωT)×R_0 or tanh(jωT)/R_0
2. The signal processing device according to claim 1, wherein an admittance circuit Y approximated by a function and a resistor R are connected in series. 4. The second basic circuit includes means for sequentially writing the input signal into the first memory every unit period, and sequentially reading the input signal from the first memory every unit period in the opposite order to the writing order; The read output from the first memory is sequentially written to the second memory every unit period through a circuit having the same transfer function as the first basic circuit, and the unit period is written in the opposite order to the writing order. 2. The signal processing apparatus according to claim 1, further comprising means for sequentially reading from said second memory for each signal processing apparatus. 5. The first basic circuit described above undergoes Z transformation (Z
=e^(jωT_0)), T_0 is the sampling period, m is the coefficient, and N=2T/T_0, (1+Z^-^N)/(1+m・Z^-^N) or (1-Z^- 2. The signal processing device according to claim 1, comprising a digital filter having a transfer function approximated by the function ^N)/(1+m·Z^-^N). 6. In a device that converts an input signal into a signal having predetermined frequency characteristics, 1/{1-[k・tanh( jωT)]＾2} Or, {k・tanh(jωT)]＾2}/{1−[k・ta
A first circuit comprising means for synthesizing an input signal via a basic circuit having a transfer function approximated by a function nh(jωT)]^2} and an input signal not via this basic circuit at a predetermined ratio. and a signal processing device of 1+K・cos^2(ωT) or 1+K・sin^, where k is a constant.
1. A signal processing device characterized in that a second signal processing device having an amplitude characteristic approximated by a function of 2(ωT) and a second signal processing device having a linear phase characteristic are connected in cascade. 7. Let T_1 and T_2 both be constants having the unit of time (T_1≠T_2), and define the circuit having a transfer function approximated by the function (1+jωT_1)/(1+jωT_2) as described above in the first circuit.
The second circuit is connected in cascade to the signal processing device of
7. The signal processing device according to claim 6, wherein the signal processing device is configured to be cascade-connected to the signal processing device.