JPH041975A - Method and device for signal processing - Google Patents

Abstract

PURPOSE:To simplify the constitution of both a pre-emphasis circuit and a de-emphasis circuit which improve the S/N by converting a signal which performs the transmission or the record/reproduction into a signal that has the desired amplitude characteristic together with the linear phase characteristic. CONSTITUTION:A basic circuit 10 needed for constitution of a pre-emphasis circuit or a de-emphasis circuit consists of an impedance circuit Z11, an admittance circuit Y12, and a resistor R1 13. The signal processing is performed with a 1st transmission function with which an input signal is approximated by a function serving as an equation I within a prescribed frequency band with an angle frequency of the input signal shown by omega, a complex angle frequency shown by S, the constants having the time units shown by (S=jomega) and T, a real number of >=0 shown by K, and an integer shown by (m) respectively. Then the signals are continuously processed with a 2nd transmission function with which the signal processing output of the 1st transmission function is approximated by a function serving as an equation II. The value of K is changed with both the 1st and 2nd transmission functions in response to the level of a high band component of the input signal. Thus both the pre-emphasis and de-emphasis circuits are obtained for improvement of the signal S/N.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method and apparatus for converting a signal such as a video signal into a signal having desired frequency characteristics, and particularly relates to a method and an apparatus for converting a signal such as a video signal into a signal having desired frequency characteristics. The present invention also relates to a signal processing method and apparatus suitable for improving waveform distortion.

[Conventional technology]

In recording and reproducing devices such as video tape recorders and video disk players that record and reproduce video signals, and in signal transmission media such as satellite broadcasting, it is common to record, reproduce, or transmit video signals by changing the frequency of the video signal (FM). It is used in In order to prevent signal S/N degradation that occurs in such FM transmission systems, the high-frequency components of the video signal are emphasized (pre-emphasis) before frequency modulation of the video signal.
However, signal processing methods that suppress (de-emphasize) high-frequency components after demodulating the FM signal have been commonly used.

In such a signal processing method, in order to faithfully transmit the signal, the transfer function of the pre-emphasis circuit must be set to G□(
S), and when the transfer function of the de-emphasis circuit is 02(S), the following equation must be satisfied regardless of frequency.

Gyu(S)XG,(S)=k ・・・・・・(
1) However, S=jω, and ω is the angular frequency of the signal.

k is a constant.

If the formula (1) is not satisfied, the recorded/reproduced or transmitted signal will have phase distortion and amplitude distortion, and the signal will not be recorded, reproduced, or transmitted faithfully.

As pre-emphasis circuits and de-emphasis circuits that satisfy equation (1), circuit networks each having a transfer function have been widely used since they can be easily and economically realized using resistors and capacitors. However, this conventional method does not take into consideration the linearity of the phase characteristics of the pre-emphasis circuit and de-emphasis circuit.

Regarding the method of improving the phase characteristics of the above-mentioned pre-emphasis circuit, Japanese Patent Laid-Open Nos. 53-131814 and 5
Although the methods described in Japanese Patent Publication No. 3-131815 and Japanese Patent Publication No. 61-8632 are known, sufficient consideration has not been given to the de-emphasis system satisfying formula (1).

Furthermore, regarding the method of improving the S/N of a signal using a pre-emphasis circuit and a de-emphasis circuit expressed by equation (2), Japanese Patent Laid-Open Nos. 59-221126 and 60-7279 disclose Although methods are known,
In none of these, consideration has been given to the linearity of the phase characteristics of the pre-emphasis circuit and de-emphasis circuit of formula (2) themselves.

[Problem to be solved by the invention]

In the above conventional technology, as is clear from equation (2), the linearity of the phase characteristics of the pre-emphasis circuit is poor. Large levels of overshoot and undershoot occur only in the direction. Therefore, when a pre-emphasized signal is frequency modulated, the amount of frequency deviation increases by the amount of overshoot and undershoot, which widens the occupied band of the FM signal, necessitating a wider transmission band. Ta.

In recording and reproducing apparatuses such as video tape recorders and video disc players, there is naturally a limit to the signal band that can be recorded on the medium. In the conventional pre-emphasis method described above, a large peak waveform in one direction occurs in the high frequency components of the signal. Therefore, for overshoot, F
The instantaneous frequency of the M signal becomes extremely high, and due to the band limitations of the above-mentioned media, high frequency signals cannot be reproduced at a sufficient level. horizontal pulling noise) occurs. Furthermore, in response to undershoot, the instantaneous frequency of the FM signal is extremely reduced, and so-called spectral folding causes beat-like noise at the image contour, which significantly deteriorates the reproduced image quality. To prevent this, generally the overshoot waveform and undershoot waveform of the signal after pre-emphasis are forcibly clipped (amplitude limited). However, because a part of the signal is lost due to this waveform clipping, equation (1) does not hold, and there is a problem in that the reproduced waveform is greatly distorted. Also, in order to prevent these,
A method of reducing the amount of pre-emphasis or reducing the amount of frequency shift is also commonly used. However, even if these methods are used, although the waveform distortion is improved, the essential problem remains that the S/N is degraded accordingly.

The purpose of the present invention is to (1) eliminate the problems of the prior art described above;
To provide a pre-emphasis circuit and a de-emphasis circuit that satisfy the formula, have good linearity of phase characteristics, do not cause amplitude distortion or phase distortion, can increase the amount of pre-emphasis, and can improve signal-to-noise ratio. be.

[Means to solve the problem]

is approximately a real number greater than or equal to 0), the value of K changes according to the level of the input signal, and a pre-emphasis circuit is constructed in which the phase characteristic is linear (that is, the 5th group delay characteristic is flat). For the emphasis circuit, the amplitude characteristic is an inverse function of the amplitude characteristic of the pre-emphasis circuit 1/(1+K
sin2(c,+T)), and the value of K is
The first point is that, like the pre-emphasis circuit, a de-emphasis circuit that changes according to the level of the input signal and has a linear one-phase characteristic realizes a signal processing device that fully satisfies the above equation (1). The characteristics of

A second feature of the present invention is that in realizing the de-emphasis circuit, the function 17 (1+Ksin'' (
Focusing on the following function obtained by expanding and approximating ωT)),
(1-to sin2(ωT))X(1-to 2sin
2(2(LIT))
)) However, the function of this first term (1-Kis
in2(ωT)), the value of K changes according to the level of the input signal, and the first phase characteristic is linear; and the second term function (1 -K2si
a second circuit network which approximately has an amplitude characteristic of n2 (2ωT)), whose value of 2 changes according to the level of the input signal and whose phase characteristic is linear; and a function of the third term (1 −to□s
in2(2ωT)), and the value of K3 changes depending on the level of the input signal.

A third circuit network having a linear phase characteristic is formed, and these first
Another feature is that the second and third circuit networks are connected in cascade to form the de-emphasis circuit.

The third feature of the present invention is that by configuring a ladder network with an inductance L and a capacitance C, the hyperbolic tangent function tanh(S
T) (T is a delay time constant). Focusing on the fact that an impedance circuit 2 and an admittance circuit Y can be realized,
This impedance circuit Z and admittance circuit Y
and a nonlinear element such as a diode, the amplitude characteristic is approximately given by the above function (1-Ksin2(ωT)), and the K(7) value changes depending on the level of the input signal,
The present invention resides in that the pre-emphasis circuit described above has a linear phase characteristic.

A fourth feature of the present invention is that by using the impedance circuit Z, admittance circuit Y, and nonlinear elements, the amplitude characteristic is approximately given by the function (1-K, sin'' (ωT)), and □ The above first circuit network whose value changes according to the level of the input signal and whose phase characteristic is linear, and whose amplitude characteristic is the function (1- to 2 sin 2 (2 (1) T)
), the value of 2 changes according to the level of the input signal, the phase characteristic is linear, and the amplitude characteristic is the function (1-K2sin2(2ωT))
The value of K3 changes according to the level of the input signal, and the third circuit network whose one-phase stability is linear is formed, and these first, second, and third circuit networks are The reason is that they are connected in cascade to form a de-emphasis circuit.

A fifth feature of the present invention is that the pre-emphasis circuit or de-emphasis circuit is configured by a digital filter using digital signal processing means.

A sixth feature of the present invention is that a second pre-emphasis circuit having a function G(S) expressed by the above equation (2) is connected in cascade to the above-mentioned pre-emphasis circuit, and the above-mentioned de-emphasis circuit is connected in series. Function 02 expressed by formula (2)
The point is that the second de-emphasis circuits having (S) are connected in cascade.

[Effect]

The pre-emphasis circuit and the de-emphasis circuit have opposite amplitude characteristics, and both have linear phase characteristics.The overall transfer characteristics of this system are linear in phase characteristics, and therefore do not cause any phase distortion. Since the amplitude characteristics are constant regardless of the frequency,
No amplitude distortion occurs, so signals can be transmitted extremely faithfully without waveform distortion.

Further, the pre-emphasis circuit operates to emphasize the level of high-frequency components of the input signal, and its phase characteristic is linear, so that an output waveform that maintains the waveform symmetry of the input signal can be obtained. More specifically, for the above-mentioned rectangular pulse signal, pre-shoot and post-shoot occur oddly symmetrically at approximately the same peak level before and after each rising and falling edge of the signal. In this way, the high-frequency components of the input signal are almost evenly distributed as pre-shoots and post-shoots before and after each rising and falling edge of the signal due to emphasis, so their peak value (peak vs. peak value) ) is significantly smaller than the conventional emphasis method where the phase characteristic shown by equation (2) above is not linear. Therefore, when performing FM transmission, the transmission band can be narrowed, and the inversion due to overmodulation described above can be narrowed. It is possible to suppress the generation of beat-like noise due to phenomena and spectrum folding, and there is no need to forcibly clip the waveform after emphasis, so that waveform distortion can be prevented. Further, the pre-emphasis circuit and the de-emphasis circuit change the amount of emphasis according to the level of the high-frequency component of the input signal, that is, increase the amount of emphasis when the level of the high-frequency component of the input signal is small. Therefore, when the level of the high frequency component of the input signal is small, further S/N improvement can be achieved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a four-terminal circuit network showing an embodiment of a basic circuit 10 for configuring a pre-emphasis circuit or a de-emphasis circuit according to an embodiment of the present invention. In the figure, 11 is an impedance circuit z, 12 is an admittance circuit Y, and 13 is a resistor R□. Both the impedance circuit Z and the admittance circuit Y are two-terminal circuit networks that approximately realize the hyperbolic tangent function tanh (ST), and are given by the following equation, with Ro as the reference resistance.

Two-terminal network 1 that approximately realizes these 2 and Y
1 and 12, as described in the document disclosed by the inventors (Japanese Patent Publication No. 60-53483),
An LC ladder network having the configuration shown in FIG. 2 is known. For reference, in (a) and (b) of Figure 2, the above (3)
) The values of inductance L and capacitance C to satisfy the equation are given by the following equations. For the impedance Z in Figure 2 (2), for the admittance Y in Figure 2 (b).

However, n is an integer of 1 or more.

In the four-terminal network 10 of FIG. 1, the transfer function po(s) of the output voltage 2 with respect to the input voltage v1 is expressed by
It is expressed as the following formula using the formula.

v2 z−Y 2(S””V, :1+(R,/R,)Z+Z−Y Here, especially if R□=R@/2, the above equation is simplified as follows.

=-sin2(ωT)・exp(-2ST) −(
7) As is clear from equation (7), since the amplitude characteristic is given by a squared sine function, the above basic circuit is hereinafter referred to as a squared sine circuit.

FIG. 3 shows a block diagram of an embodiment of the pre-emphasis circuit according to the present invention, which is constituted by a squared sine circuit 10 having the transfer function pa(s) of the above equation (7). In FIG. 3, 21 is an input terminal for a signal, 22 is an output terminal for a signal processed by the pre-emphasis circuit @33, and 25 is for compressing the signal by -2 times according to the input level. That is, a compressor compresses the amplitude level by two times, inverts the phase, and outputs it, 23 is a delay device, and 26 is an adder. Input terminal 2
The signal input to 1 has the transfer function Fo(
s) and then input to the compressor 25. The compressor 25 compresses the signal.

A signal whose amplitude is doubled according to the input level and whose phase is inverted is output. The output signal from compressor 25 is supplied to one input of adder 26. Adder 26
The input signal from the input terminal 21 is input to the other side of the delay device 23.
A signal delayed by the time 2T is supplied at . This adder 26 adds the output from the compressor 25 and the output from the delay device 23, and the output signal is output to the output terminal 22. Here, the compressor 25 is, for example, as shown in FIG. 4(a).
It has the compression characteristics shown in . An embodiment of this compressor 25 is shown in FIG. 4(b). In FIG. 4(b), 27
．． 29 is a coefficient unit.

28 is a nonlinear circuit. The input signal in FIG. 2B is amplitude-adjusted by a factor of '' by the coefficient multiplier 27 and is input to the nonlinear circuit Jl 128. As the nonlinear circuit 28, for example, a circuit shown in FIG. 2(c) is used. In the same figure (C), 30 is a resistor, and 31 and 32 are diodes. The above nonlinear cycle Jl! The signal input to 2g is due to the nonlinear characteristics of diodes 31 and 32.

Amplitude compression is applied according to the input level. Nonlinear circuit 28
The amplitude of the signal subjected to amplitude compression is adjusted by a factor of 1 in a coefficient multiplier 29, and then output. Here, by adjusting the coefficients of the coefficient multiplier 27 and the coefficient multiplier 29, the compression characteristics of the compressor 25 can be arbitrarily set. That is, the value of -, which is the compression characteristic of the compressor 25, is arbitrarily set depending on the level of the signal input to the compressor 25, for example, when the level of the high frequency component of the input signal is small, the value of - is increased. When the level of the above-mentioned high frequency component is high, it is possible to change it so as to make it smaller.

With the above configuration, the transfer function H(S) of the pre-emphasis circuit 33 is changed to the transfer function of the delay device 23 by D(S)=e
As xp(-2S T) - (8), equation (7),
Using equation (8), it is given by the following equation.

H□(S)=D(S)+F, (S)・(-K)=(1+
Niichi sin2(ωT)) ・exp(-2S T)・・
・(9) This transfer function) It is clear that by changing 2, the pre-emphasis circuit operates as a pre-emphasis circuit in which the amount of emphasis changes according to the level of the high-frequency component of the input signal.

Next, the amplitude term (1+Ksin2(ωT)
A method of realizing a de-emphasis circuit having an amplitude characteristic 1/(1+Ksin2(ωT)) which is opposite to the pre-emphasis characteristic represented by ) will be described.

The amplitude characteristics H, (S) of the de-emphasis circuit described above are expressed by the following equation.

Ha(S)=1/(1+Ksin2(ωT))
However, L=2+E...(11)
As described above, since K is set to a positive value, L is less than or equal to 1, and the following equation holds true.

l L-cos(2ωT) I < 1 - (12)
Therefore, the above equation (10) can be expanded into a geometric series.

Ho(S)=(1-L)・(1-L,cos(2wT
))= (1-L)-Σ(L-cos(2ωT)i and=(1-L)・rI(1+(L-cos(2c,+T)
(13) In the above equation (13), if up to the third item are regarded as effective terms, the above amplitude characteristic H1l(S) can be approximated as shown in the following equation.

He(S)2(1-L)(1+Laos(2(, J T
))・(1+ (Laos(2ωT))”)・(1+
(Lcos(2ωT))')=(1-L")(1-to 1
sin2(ωT))・(1-K2sin2(2(LI
T)) to.

・(1-K2sin2(2ωT)-7in2(4ωT)
) -(14) Here, since L is less than or equal to 1, it can be further approximated as shown in the following equation.

no(s)2(1-K2sin2(ωT)) x(1-
, sun2(2ωT))X(1-K2sin2(2ω
T)) - (16) Therefore, for the pre-emphasis circuit 33 having the transfer function H(S) expressed by the above equation (9), the transfer function H2(S) expressed by the following equation
It can be seen that it is sufficient to configure a de-emphasis circuit having the following.

Hl (S) = (1-Ksin” (,T)) Xex
p(rn S T) = (1-, sin” ((&)
t)) X (1-, sin2 (20 guns))
-K2sin2(2ωT))Xexp(-msT)
-(17) Here, when m=10, the following equation is obtained.

H2(S) = [(1-to 1sin2(ωT))・e
xp(-2ST)]X[(1-, sin2(2(L
I T)) ・exp(-4ST)]X [(1-to 3
sin” (2(1)T)) ・exp(-4ST)]
...(18) FIG. 6 shows the transfer function H2(
s) shows a block diagram of an embodiment of a de-emphasis circuit.

In FIG. 6, 41 is a signal input terminal, 42 is a de-emphasized signal output terminal, and 63 is a de-emphasis circuit. The de-emphasis circuit 63 includes a first circuit block 60, a second circuit block 61,
It is constructed by cascading third circuit blocks 62. The first circuit pro above.

In the rotor F, 10 is a squared sine circuit composed of the four-terminal network shown in FIG. 1, and its transfer function is given by equation (7). 43 is a delay device having a delay time of 2T, and its transfer function is given by equation (8). 44 is a compressor having the configuration shown in FIG. 4(b), for example, and by adjusting the coefficient of the coefficient unit 27 to ' and the coefficient of the coefficient unit 29 to 1,
1 is realized in the compression characteristic determined from equations (11) and (15). 45 is an adder.

The signal input from the input terminal 41 is supplied to the squared sine circuit 10 having the transfer function p o (s) of equation (7), and its output is supplied to the compressor 44, which increases the amplitude by 0 times according to the input level. undergo compression. The output from compressor 44 is fed to one of adders 45. The other side of the adder 45 is supplied with the signal input to the input terminal 41 after being delayed by the time 2T by the delay device 43 . Adder 45
The signals fed to the second
is supplied as an input to the circuit block 61 of. Transfer functions P from the input of the above first circuit block 60 to eight factors
The force (S) is given by the following equation using equation (7).

Pl(S)=exp(-2S T)1-1-FO(S
) = (1-, 5un2((2ωT)) ・exp(
-2ST) (19) This transfer function P□(S) coincides with the first term on the right side of the transfer function H2(S) in equation (18) above.

Next, in the second circuit block 61 of FIG.

46a is the transfer function Fi(S
) is a squared sine circuit.

F, (S)=-sin2(2(2ωT)・exp(
-4ST)=(20) 47 is a delay device having a delay time of 4T, and 49 is an adder. Reference numeral 48 denotes a compressor having the configuration shown in FIG.
The compression characteristics determined from equations (11) and (15) are
Realize.

The signals received from the first circuit block 60 are as follows.

The signal is supplied to a squared sine circuit 46a having a transfer function F (S) expressed by the above equation (20), and its output is supplied to a compressor 48 where it undergoes amplitude compression by a factor of two in accordance with the input level. The output from compressor 48 is fed to one of adders 49. The other side of the adder 49 is supplied with the signal output from the first circuit block 60 after being delayed by a time 4T in the delay device 47 . The signals supplied to the adder 49 are summed here and the output thereof is supplied as an input to the third circuit block 62. The transfer function P2(S) from the input to the output of the second circuit block 61 is given by the following equation using equation (20).

Pg(S)=exp(-4ST)+, ・F□(S)
:= (1-to, sin2(2(1)T))・exp
(-4ST)...(21) This transfer function P'! (S) matches the second term on the right side of the transfer function H, (s) in equation (18) above.

Next, in the third circuit block 62 of FIG.
b is a squared sine circuit having the transfer function F□(S) of the above equation (20), 50 is a delay device having a delay time of 4T,
52 is an adder. 51 is a compressor having the configuration shown, for example, in FIG. A compression characteristic K3 determined by is realized.

The signal output from the second circuit block 61 is supplied to the squared sine circuit 46b having the transfer function F(S) of the above equation (20), and the output thereof is sent to the compressor 51 according to the input level. The amplitude is compressed by a factor of 3. The output from compressor 51 is supplied to one of adders 52. Adder 52
The signal output from the second circuit block 61 is supplied to the other terminal after being delayed by a time 4T in the delay device 50. The signals supplied to the adder 52 are added here, and the output is output to the output terminal 42. The transfer function pJs) of the third circuit block 62 of 0 or more is expressed by the following equation using equation (20). Given.

P, (S)" exp (-4S T) + K3- F, (
S)=(1-to3sin2(2ωT))・exp(-4
S T)...(22) This transfer function P3(S) matches the third term on the right side of the transfer function HX(S) in equation (18) above.

The de-emphasis circuit 63 shown in FIG.
), a first circuit block 60 having a transfer function P□(S) of the above equation (21), a second circuit block 61 having a transfer function P2(S) of the above equation (21), and a transfer function of the above equation (22). Since the third circuit block 62 having pa(s) is cascade-connected, the overall transfer function H! of this de-emphasis circuit 63 is cascaded. (S) is given by the following equation.

H, (S)=P□(S)・Pl(S)・Pl(S)=
[(1-to 1sin2(ωT))exp(-2ST)
]X [(1-, sin” (2(2ωT))・ex
p(-4ST)]X [(1- to 3sin” (2(L
I T))・exp(-4ST)]...(23) This equation matches the above equation (18), and therefore the desired de-emphasis circuit, that is, the transfer function H□( This means that a de-emphasis circuit having an amplitude characteristic 1/(1+Ksin2(ωT)) opposite to the amplitude characteristic (1+Ksin2(ωT)) of the pre-emphasis circuit having S) has been realized.

In the de-emphasis circuit 63 of FIG. 6, each compression characteristic of the compressor 44, 48, 51 is as follows
), but in reality, the above (18
) (and equation (23)) approximates equation (13) by truncating it at the third term, which causes an error.

In order to reduce this error, 1. K2
．． K may also be set, thereby making it possible to more accurately approximate the inverse characteristic of the pre-emphasis characteristic. The amplitude characteristics of the de-emphasis circuit 63 shown in FIG. 6 are shown in FIG.

Next, FIG. 8 shows a response waveform of the pre-emphasis circuit llll33 shown in FIG. 3 to the rectangular pulse input signal Si. In the figure, (a) shows the waveform of the input signal Si, and (b)
) indicates the waveform of the output signal So. In this way, the response waveform to a rectangular pulse signal is before and after each rising and falling edge of the signal.

The pre-shoot and post-shoot occur in an oddly symmetrical manner at the same peak level. In other words, the high-frequency components of the input signal Si are almost evenly distributed between the preshoot and the postshoot due to emphasis, so the peak-to-peak value of the output signal So is equal to that of the conventional emphasis shown in equation (2) above. It is smaller compared to the method.

Therefore, the signal SO that is processed and output in this way is
When frequency-modulating and transmitting (or recording and reproducing) the frequency, the amount of deviation per frequency can be kept small, so the occupied band of the FM signal can be narrowed accordingly, making it difficult to be subject to restrictions on the transmission band. Furthermore, since overmodulation can be prevented, the occurrence of spurious signals due to inversion phenomena and spectrum folding can be suppressed, and there is no need for forced clipping of the waveform, so that waveform distortion can be prevented.

Furthermore, in the emphasis method of the present invention, the amount of emphasis can be increased for a signal with a low level of high-frequency components, so the transmission band can be used more efficiently.

The pre-emphasis cycle [3] in FIG. 3 according to the present invention described above
3, after applying pre-emphasis to the signal to be transmitted (or recorded or reproduced).

The received signal (or reproduced signal) is FM modulated and transmitted (or recorded and reproduced), and then the received signal (or reproduced signal) is FM demodulated, and then subjected to de-emphasis by the de-emphasis circuit 63 shown in FIG. If the system is configured to restore , the overall transfer characteristic of this transmission system will be
Using equations (9) and (17), it is given by the following equation.

Hz(S)×Hz(S)=exp((2+m)ST)
−=(24) In other words, the overall transfer characteristic of this system is that it only has a constant delay time (2+ m )・T, the phase characteristic is linear and does not cause any phase distortion, and the amplitude characteristic is Since it is constant regardless of the amplitude, it does not cause any amplitude distortion, and therefore the signal can be transmitted extremely faithfully without waveform distortion, and the noise received on the transmission path can be reduced in proportion to the amount of emphasis according to the above value. It is clear that the S/N can be improved by suppressing the noise. In addition, in the present invention, the value of K is changed in accordance with the change in the level of the high-frequency component of the input signal (if the level of the high-frequency component is low by JJ%, the value of K is increased). It is possible to reduce the influence of noise on small amplitude signals in the range.

In each of the above embodiments, the LC shown in FIG.
Although a ladder circuit network is used, the present invention is not limited thereto, and may be configured using a delay device.6 and below. FIG. 9 shows an embodiment configured using a delay device. In FIG. 9, 21 is a signal input terminal, 33 is a pre-emphasis circuit, 97 is a circuit block having a delay device, 22 is an output terminal for a signal processed by the pre-emphasis circuit 33, and 91.92 is a delay time of 2T. a delay device having 93.
94.95 is -1/4 respectively. -1/4. +1/
2 is a coefficient multiplier having a coefficient of 2, 25 is a compressor whose amplitude compression characteristic is -, and 26 is an adder. The signal input to the input terminal 21 is amplitude-adjusted by a factor of 1/4 by a coefficient multiplier 93 and is supplied to an adder 96 . Further, the signal input to the input terminal 21 is delayed by the time limit by the delay device 91.

The amplitude is adjusted by +172 times by the coefficient unit 95 and the adder 9
6. On the other hand, the signal delayed for a time of 2T by the delay device 91 is also supplied to the delay device 92, and after being further delayed by a time of 2T, the amplitude is adjusted by a factor of 1174 by a coefficient multiplier 94, and the signal is supplied to an adder 96.

The signals supplied to the adder 96 are added here, and the output signal 9A thereof is supplied to the compressor 25, where the amplitude is compressed to -2 according to the input level. The output from compressor 25 is provided to adder 26. The other end of the adder 26 is supplied with an input signal delayed by a time 2T by a delay device 91. The signals supplied to the adder 26 are added and sent to the output terminal 2.
Output to 2. In the figure, when the input signal is Vi, the signal 9A processed by the circuit block 97 is expressed by the following equation.

=-sin” ((1)T) ・exp (-2ST)
-Vi - (24) The above equation (24) is given by the following equation using the above equation (7).

9A = FIl(S)・Vi −(24a) Also,
At this time, 9B is expressed by the following formula.

9 B = exp(-2S T) ・Vi -(
25) Therefore, the transfer function H of the pre-emphasis circuit 33
The engineering (S) is given by the following formula.

)1. (S) = exp (-2ST) + one sin”
((LI T) ・exp(-2ST)= (1+K
sin2(ωT))・exp(-2ST)...(26
) The above equation (26) coincides with the above equation (9), and it is clear that a desired pre-emphasis circuit can be realized thereby. Further, the circuit block 97 using a delay device in the pre-emphasis circuit 33 specifically includes:
For example, as shown in FIG. 10, it can also be constructed using reflection of an analog delay line.

In FIG. 10, 101 is a buffer amplifier with an output impedance of zero, 102 is a resistor with a resistance value of R3, 103 is a characteristic impedance of R3, and analog delay lines 104 and 106 with a delay time of 2T are sufficiently connected. Buffer amplifier with high input impedance, 105
．． 107 is a coefficient multiplier having coefficients of 1/2.1/4, and 108 is a differential amplifier having a differential gain of 1. In FIG. 10, the input signal is transmitted to the buffer amplifier 10.
1 and connected to the analog delay line 10 through a resistor 102.
It is input to the input terminal of 3. The signal delayed by the time 2T by the analog delay line 103 is outputted as a signal 9B via the buffer amplifier 104. At this time, the output signal 9B is
Using the input signal Vi, it is given by the following formula: 9B = exp(-2S T) ・Vi =
(27) The output of the buffer amplifier 104 is also supplied to the coefficient multiplier 105, where the amplitude is adjusted by a factor of 172 and input to the positive phase input of the differential amplifier 108. on the other hand.

Since the input impedance of the buffer amplifier 104 is high, in-phase reflection occurs at the output end of the delay line 103. Therefore, a signal obtained by combining the output of the buffer amplifier 101 via the resistor 102 and the signal reflected at the output end of the delay line, that is, the signal delayed by a time of 4T, is input to the buffer amplifier 106. Therefore, the output signal 9C of the buffer amplifier 106 is expressed by the following equation.

9C=Vi+exp(-4ST)・Vi-(28
) This output signal 9C is amplitude-adjusted by a factor of 174 by the coefficient multiplier 107 and inputted to the negative phase input of the differential amplifier 108.

The differential amplifier 108 outputs the difference between the positive phase input and the negative phase input as an output signal 9A. Therefore, the output signal 9A is expressed by the following equation.

9A=--・9C+-・9B=-sin" (ωT)・exp(-2ST)・Vi
-・(z9) The above equations (27) and (29) match the above equations (25) and (24), respectively, and therefore the input signal is the transfer function F.

Circuit block 9 is a circuit that outputs the signal 9A processed by (S) and the signal 9B obtained by delaying the input signal by time 2T.
It is clear that 7 may be configured as shown in FIG. 10.8 Next, FIG. 11 shows an example of a de-emphasis circuit 63 configured using a delay device. , 41 is a signal input terminal, and 42 is a signal output terminal processed by the de-emphasis circuit 63.

It is constructed by cascading a first circuit block 60, a second circuit block 61, and a third circuit block 62. In the first circuit block 60, 110 is
The input signal is transferred to the transfer function F. This is a first signal processing circuit that outputs the signal processed in (S) and a signal obtained by delaying the input signal by a time of 2T, and has the same configuration as the circuit block 97 shown in FIG. 9. 44 is a compressor whose compression characteristic is 1,
45 is an adder.

The signal input to the input terminal 41 is supplied to the first circuit block 60 and input to the first signal processing circuit 110. In the first signal processing circuit 110, transfer function F6(S
) is supplied to a compressor 44, where the amplitude is compressed by a factor of 1 in accordance with the input level, and then supplied to an adder 45. The other input of the adder 45 is supplied with an input signal that is one output of the first signal processing circuit 110 and is delayed by a time of 2T. The signals supplied to the adder 45 are added here and output to the second circuit block 61. Therefore, the transfer function Pyu(
S) matches the above equation (19) and is given by the following equation.

P, (S) = (1-K2sin2(c, +T))・
exp(-2ST) ・=(30) Next, in the second circuit block 61, 1lla converts the input signal to the above (
20) A second signal processing circuit that outputs a signal processed by the transfer function F (S) of the equation and a signal obtained by delaying the input signal by a time of 4T, 48 is a compressor with a compression characteristic of 2, and 49
is an adder. Here, the second signal processing circuit 111a has the same configuration as the circuit block 97 shown in FIG.
This is realized by setting the delay time of each of the delay devices 91 and 92 to 4T.

In the second circuit block 61, the signal supplied from the first circuit block 60 is transmitted to the second signal processing circuit 111.
input to a. In the second signal processing circuit 111a, the input signal processed by the transfer function F□(S) is sent to the compressor 4
8, the amplitude is compressed to twice the amplitude according to the input level, and then the signal is supplied to an adder 49. On the other hand, the signal delayed by the time 4T in the second signal processing circuit is input to the other side of the adder 49. The signals supplied to the adder 49 are added here and output to the third circuit block 62. Therefore, the transfer function p2(s) of the second circuit block 61
coincides with the above equation (21) and is given by the following equation.

P, (S)=(1-K2sin2(2ωT))exp(
-4ST)...(31) Next, in the third circuit block, 111b processes the input signal using the transfer function F of equation (20) (S), and the input signal is delayed by 4T. 3rd output signal
51 is a compressor having a compression characteristic of -1, and 52 is an adder.

Here, the third signal processing circuit 111b can be realized with the same configuration as the second signal processing circuit 111a. In the third circuit block 62, the signal supplied from the second circuit block 61 is transmitted to the third signal processing circuit 11.
1b. In the third signal processing circuit 111b, the input signal processed by the transfer function F (S) is supplied to the compressor 51, and the amplitude is compressed by three times according to the input level. supplied to Adder 5
The signals supplied to the terminals 2 and 2 are summed here and output to the output terminal 42.

Therefore, the transfer function P3(
S) coincides with the above equation (22) and is given by the following equation.

P3(S) = (1-K2sin2(2ωT))・e
xp(-4ST)...(32) The de-emphasis circuit 63 in FIG. 11 has the first circuit block 60, the second circuit block 61, and the third circuit block connected in cascade. .

The transfer function Ha(S) of the de-emphasis circuit 63 is given by the following equation.

H, (S) = P engineering (s) xp, (s) x P3 (S) =
[(1-to 1sin2(ωT))・exp(-2ST)
]X [(1- to 2sin2(2ωT))exp(-4
ST)]X [(1-K2sin2(2ωT))ex
p(-4ST)]...(33) The above equation (33) matches the above equation (18), and it is clear that the desired de-emphasis circuit can be realized by the configuration shown in FIG. 11. .

In the above embodiment, the de-emphasis circuit 63 only needs to have the circuit blocks 60, 61, and 62 connected in series, and the connection order does not matter, and any order may be used. Further, in the above embodiment, the diodes 31 and 32 were used in the nonlinear circuit 28 in order to obtain compression characteristics, but the present invention is not limited to this, but the relationship between the emitter voltage and the collector current of the transistor in the differential amplifier is You may also use it.

In all of the above embodiments, the pre-emphasis circuit and the de-emphasis circuit are configured using analog processing circuits, but the present invention is not limited to this. You can also do this.

1 as a method of converting analog circuits to digital circuits
A method using the following standard Z transformation is known.

Z = expCS To) ・=
(34) However, Tll is the period of the sampling clock signal of the digital signal processing system.

FIG. 12 shows a digital pre-emphasis circuit 33D in which the pre-emphasis circuit 33 of FIG. 9 is constructed by a digital circuit using the standard Z-transform of equation (34) above.

In FIG. 12, 21 is a signal input terminal, 22 is a signal output terminal, 71 is an A/D converter, 72 is a D/A converter, and 91D and 92D are input signals each having a time of 2T. This is a digital delay device. This digital delay device 92D uses the above sampling clock signal to clock the input signal by 2N clocks (however, N
=T/To). 93D
, 94D, 95D are digital coefficient multipliers, each with a coefficient value of -1/4. -1/4°172. 96D,
26D is a digital adder. 25D is a digital compressor and has compression characteristics of -. This digital compressor 2'5D is a coefficient unit composed of, for example, a ROM, and performs signal processing to change the value of -, which is the ratio of the output level to the input level, according to the level of the input signal. .

The digital circuit block 97D in FIG. 12 is a digital signal processing circuit obtained by converting the circuit block 97 in FIG. 9 to a digital signal processing circuit, so the basic operation thereof is the same, and the explanation thereof will be omitted. Therefore, the digital circuit block 97D has the transfer function Fs(s
) using the standard 2 conversion and processed by the transfer function Fo (z) shown by the following equation, and a signal delayed by 2N clocks (2T in time) by the sampling clock are output.

Furthermore, regarding the digital pre-emphasis circuit 33D in FIG. 12 and the pre-emphasis circuit 33 in FIG. 9, their basic operations are the same, only that the signal processing is changed from analog processing to digital processing. , the explanation is omitted.

In FIG. 12, the signal input to terminal 21 is A/D
After being converted into a digital signal in the converter 71,
The signal is input to the digital pre-emphasis circuit 33D.

The signal subjected to digital signal processing in the digital pre-emphasis circuit 33D is supplied to the D/A converter 72, where it is converted into an analog signal and output to the terminal 22.

Similarly, in contrast to the de-emphasis circuit 63 of FIG. 11, FIG. 13 shows an embodiment of a de-emphasis circuit using digital signal processing that is converted using the standard 2 conversion of equation (34). In FIG. 13, 41 is a signal input terminal, 42 is a de-emphasized signal terminal, 73 is an A/D converter, 74 is a D/A converter, and 63D
is a digital de-emphasis circuit. The digital de-emphasis circuit 63D includes a first digital circuit block 60D and a second digital circuit block 61D.
and a third digital circuit block 62D are connected in cascade, and the first digital circuit block 60
In D.

110D performs the above (35
This is a digital signal processing circuit that outputs a signal processed by the transfer function Pa(Z) of the equation ) and a signal delayed by 2N clocks (2T in time), and has the same configuration as the digital circuit block 97D in FIG. 12.

44D is a digital compressor and has excellent compression characteristics. 45D is a digital adder. Second digital circuit block 61D and third circuit block 62
In D, 49D, 52D are digital adders. 48D and 51D have compression characteristics, K
It is a digital compressor having 1, for example, a coefficient multiplier composed of a ROM, etc., and depending on the level of the input signal, the ratio of the output level to the input level is K,
Signal processing is performed to change the values of . 111Da
, 111Db are all obtained by using the standard Z transformation of the input signal from the transfer function F
A signal processed by a transfer function Fl(Z) shown by the following equation,
This is a digital signal processing circuit that outputs a 4N clock (4T in time) delayed signal.

A circuit block 60D based on the above digital signal processing,
61D, 62D and a digital de-emphasis circuit 63D configured by cascading these are respectively connected to circuit blocks 60, 61, 62, . . . in FIG. and a de-emphasis circuit 63 configured by cascading these, and the only difference is that the signal processing is changed from an analog processing method to a digital processing method, and the basic operation is the same in both. Explanation will be omitted. In FIG. 13, the signal input to the terminal 41 is
The signal is converted into a digital signal by the A/D converter 73 and supplied to the digital de-emphasis circuit 63D. The digital signal supplied to the digital de-emphasis circuit 63D is supplied to the digital circuit blocks 60D and 61D.

The signals are sequentially processed at 62D, converted into analog signals at p/A converter 74, and output to terminal 42. It is clear that by using the digital circuits shown in FIGS. 12 and 13 above, the pre-emphasis circuit and de-emphasis circuit having desired characteristics can be constructed entirely from digital signal processing circuits.

As described above, the feature of the present invention is to focus on the basic function of the above equation (10), expand this equation (10), and develop the above equation (10).
By approximating as shown in equation (6), for the basic function H(S) of the pre-emphasis circuit in equation (9) above,
The basic numerical value H (S) of the de-emphasis circuit of the above equation (18), which has opposite amplitude characteristics and a linear phase characteristic, is realized, and thereby the overall transfer characteristic of the above equation (24) is obtained, resulting in high fidelity. The key point is that it realizes the transmission of signals. Another embodiment of the pre-emphasis circuit and de-emphasis circuit according to the present invention, which maintains this basic idea, is shown in FIG.

Here, the basic function H1(S) of the pre-emphasis circuit of the above equation (9) realized in the embodiment of FIG. 3, FIG. 9 or FIG.
The above (18) realized by the embodiment shown in FIG.
By substituting the basic functions H, (S) of the de-emphasis circuit in the equation (24) above, the following relational expression is obtained.

H□'(S)xH,'(S)"exp(-12ST
) − (37) However, H1' (S) = [(10 to sin” ((LI
T)) ・exp(-2ST)]X [(1-, s
in” (2(11■)lexp(-4ST)]X [
(3sin” (2ωT))・exp(−4ST
)]H,' (s)= (1-K1sin2(ωT
))・exp(-2ST)]m ” 10
...(38).

That is, instead of using the above basic functions H(S) and H2(S), even if the new basic functions H′(S) and H22(S) defined by the above equation (38) are used, the high Condition (37), which allows faithful signal transmission, is satisfied. This new first
The basic function H,' (S) has a pre-emphasis characteristic in which the amplitude is emphasized in the high frequency range as in FIG. 5 above, and the degree of amplitude emphasis changes depending on the level of the high frequency component of the input signal, and , the new second basic function H,' (s) has a de-emphasis characteristic in which the amplitude is suppressed in the high frequency range and the degree of amplitude suppression changes depending on the level of the high frequency component of the input signal, as in Fig. 7 above. have

In FIG. 14, (a) is a block diagram showing an example of a pre-emphasis circuit that realizes the above function H,' (S), and (b) is a block diagram showing an example of a pre-emphasis circuit that realizes the above function H,' (S). FIG. 2 is a block diagram showing an example of an emphasis circuit.

H□'(S) in the above equation (38) is H(S) in the above equation (9), p2(s) in the above equation (21), and P in the above equation (22).

(S) corresponds to the product (H,' (S) = H(S)
・P, (S) - P3 (S)) Therefore, the above figure 14 (
The pre-emphasis circuit 64 in a) includes the circuit block 33 in FIG. 3 above and the circuit blocks 61 and 6 in FIG. 6 above.
2 (which may be in any order), and therefore are designated by the same reference numerals.

Also, H2' (S) in the above equation (38) is the above (19)
Matches P□(S) in the equation (H2' (S)=P□(S
)) Therefore, the de-emphasis circuit shown in FIG. 14(b) can be realized with exactly the same configuration as the circuit block 60 shown in FIG. 6, and therefore is indicated by the same reference numeral.

The embodiment shown in FIG. 14 shows the case of analog processing, but in the same way as the embodiments shown in FIGS. 12 and 13 above,
Each circuit block in Fig. 14 above 33.61.62゜60
Instead of the digital processing circuit block 33D,
By using 61D, 62D, and 60D, respectively,
It is possible to construct a digital processing type pre-emphasis circuit and de-emphasis circuit which can obtain exactly the same functions and effects as those shown in FIG.

As described above, in the present invention, both the pre-emphasis circuit and the de-emphasis circuit can be realized by both analog processing and digital processing. (
As shown in the embodiment b), the de-emphasis circuit can be realized with a relatively simple configuration, especially by using an analog processing method, and this has the effect of configuring a system with the most stable operation.

That is, considering the case where a video signal is supplied to the above pre-emphasis circuit and de-emphasis circuit, if these pre-emphasis circuit and de-emphasis circuit are configured with a digital processing circuit, the above-mentioned sampling for signal processing, which is not shown in the figure, can be performed. It is necessary to generate the clock signal in synchronization with the synchronization signal of the video signal, and therefore it is necessary to be able to stably separate the synchronization signal of the video signal. It is easy to stably separate the synchronization signal from the video signal input to the pre-emphasis circuit, so configuring the pre-emphasis circuit with a digital processing circuit poses no problem in terms of operational stability. Digital processing has the effect of obtaining desired characteristics with high precision. However, the video signal pre-emphasized by this pre-emphasis circuit has sharp peak waveforms with large levels before and after the rising and falling edges, as shown in FIG. 8(b) above. It is generally difficult to identify and stably separate the synchronization signal from such pre-emphasized video signals. However, the de-emphasis circuit which inputs this pre-emphasized video signal is shown in FIG. 6, 11 or 14 (b).
) If the system is configured with an analog processing circuit as in the embodiment, it becomes unnecessary to identify and separate synchronizing signals, and the problem of operational stability associated with this is eliminated, resulting in the ability to configure a highly faithful and stable system.

As shown in FIG. 8(b), the waveform pre-emphasized by the pre-emphasis circuit according to the present invention is evenly distributed to the pre-shoot and post-shoot by emphasizing the high frequencies of the signal, resulting in a sharp peak of the signal. The head to peak value is
This is smaller than the conventional emphasis method shown in equation (2) above. In other words, assuming that the peak-to-peak value of the high-frequency emphasized signal, which is determined by conditions such as the band of the transmission path, is constant, the method of the present invention has a higher emphasis than the conventional method. It becomes possible to further increase the amount, and the S/N ratio can be improved accordingly.

The easiest way to increase this amount of emphasis is to increase the value of K in the compression characteristic -K, but the transfer function GW(S) in equation (2) and a2
(s) A conventionally known pre-emphasis circuit 90a and de-emphasis circuit 90b, an embodiment of which is shown in FIG. 15, may be used in combination with the pre-emphasis circuit and de-emphasis circuit of the present invention. More specifically, in FIG. 15, 91.92 is a capacitor,
93, 94, 95, 96 are resistors, and the pre-emphasis circuit 90a of FIG. 15(a) is shown in the embodiment of FIG. 3 or 91 or node 12 or FIG. 14(a). A pre-emphasis system is constructed by connecting the pre-emphasis circuit of the present invention in cascade, and the de-emphasis circuit 90b shown in FIG. A de-emphasis system is constructed by cascading the de-emphasis circuit of the present invention shown in the embodiment (b).

According to the above configuration, the time constant T and 'r of the above equation (2)
z (capacitor 91.92 and resistor 93.94 in Figure 15)
95.96) is set to a relatively large value, the pre-emphasis circuit for one transfer function a1(S) can be used primarily for emphasizing the low frequency range of the signal, and the pre-emphasis circuit for the other transfer function H1(S) or HA'
The pre-emphasis circuit (S) can be used mainly for emphasizing the high frequency range of the signal, so the amount of emphasis can be increased over a wide frequency range, and the S/N ratio can be improved without waveform distortion.

In addition, in the above embodiment, approximation was performed by regarding the third item in the above equation (13) as an effective term, but the present invention is not limited to this. For example, if you want to change the value by a small value, specifically change the value from 0.25 to 2.16 depending on the level of the high frequency component of the input signal (i.e., change the amount of emphasis (1+K) from 2 dB to 2.16). 10d
B), K3 changes from 0.000152 to 0.0676, which is a sufficiently smaller value than 1. In such cases.

In the above equation (13), up to the second term may be considered as effective terms, and the transfer function H2(S) of the above equation (18) is only the first and second terms on the right side of the above equation (18). .

Therefore, the circuit block 62 in FIGS. 6, 11, and 14 and the circuit block 62D in FIG. included in the scope of the invention. Furthermore, when K is small, the transfer function H of the above equation (18)
a(S) may be approximated only by the first term on the right side of equation (18) above, and it is clear that in such a case it can be realized with a simpler configuration, and this is not in accordance with the gist of the present invention. be.

〔Effect of the invention〕

As described above, according to the present invention, a signal to be transmitted or recorded/reproduced is converted into a signal having a linear phase characteristic and a desired amplitude characteristic, and in particular, the amplitude of the mid-range or high-frequency range of the signal is emphasized. A comparison of a pre-emphasis circuit with a linear phase characteristic and a de-emphasis circuit with a characteristic opposite to its amplitude characteristic, a linear phase characteristic, and which can be sufficiently matched with the pre-emphasis circuit over a wide frequency range. This can be realized with a simple configuration.

In addition, these can be easily constructed using digital circuits, increasing the precision and stability of signal processing.
It also facilitates circuit integration. Furthermore, if this is applied to an FM transmission system, it is possible to increase the amount of frequency deviation without widening the transmission band, eliminate the need for waveform clipping to prevent overmodulation, and eliminate S/N without waveform distortion. can be improved. Furthermore, in the present invention, since the amount of emphasis can be made variable, the transmission band can be effectively utilized by increasing the amount of emphasis when the level of the high frequency component of the input signal is small.

Further improvement in S/N can be achieved.

[Brief Description of the Drawings] Fig. 1 is a wiring diagram showing an embodiment of the squared sine circuit according to the present invention, and Fig. 2 is a wiring diagram showing a specific example of the impedance circuit Z and admittance circuit Y used in the present invention. 3 is a block diagram showing an embodiment of a pre-emphasis circuit constructed of the squared sine circuit, and FIG. 4 is a block diagram showing one embodiment of a pre-emphasis circuit constructed from the squared sine circuit, and FIG. FIG. 5 is a characteristic diagram showing the amplitude characteristics of the pre-emphasis circuit, FIG. 6 is a block diagram showing an embodiment of the de-emphasis circuit configured with the squared sine circuit, and FIG. 7 is a diagram showing a specific example. 8 is a characteristic diagram showing the amplitude characteristics of the de-emphasis circuit, FIG. 8 is a diagram showing the response waveform of the pre-emphasis circuit, FIG. 9 is a block diagram showing another embodiment of the pre-emphasis circuit of the present invention, and FIG. 10 is a diagram showing the response waveform of the pre-emphasis circuit. FIG. 9 is a wiring diagram showing a specific example of the circuit blocks used, FIG. 11 is a block diagram showing another embodiment of the de-emphasis circuit of the invention, and FIG. 12 is another example of the pre-emphasis circuit of the invention. FIG. 13 is a block diagram showing another embodiment of the de-emphasis circuit of the present invention; FIG. 14 is a block diagram showing another embodiment of the pre-emphasis circuit and de-emphasis circuit of the present invention. ,
FIG. 15 is a wiring diagram showing an embodiment of another emphasis circuit used together with the emphasis circuit of the present invention. 11... Impedance circuit. 12...Admittance circuit, 10, 46a, 46b-squared sine circuit, 25.44
,48,51.25 D ,44 D ,48 D ,
51 D... Compressor, 23.43, 47, 50, 91
, 92, 91 D, 92D... delay device. zs, ss, 49. sz, zst+, 45D, 49
D, 52D, 96, 96D... Adder, 27.29, 93, 94, 95, 105, 107, 93
D, 94D, 95D...Coefficient unit, 28...Nonlinear circuit. 71.73...A/D converter, 72.74...D/A converter. Shasha Low---------------------al Relationship with Patent Applicant Name < 5101 Hitachi, Ltd. 0b Contents of Amendment (1) The scope of claims in the specification is amended as shown in the attached sheet. (2) Page 19, lines 15 to 20 of the same The second line written in
For the admittance Y in figure (b), the admittance Y in figure 2 (b) is corrected as follows. (3) The statement on page 25, line 12 is corrected. (4) [...(24) stated in page 35, line 16 of the same document]
Correct J as [...(25)J. (5) "...(24a) stated on page 35, line 19 of the same
)" is corrected as "...(25a)J. (6) "...(25)J" written in the second line of page 36 of the same
of. "... (25b) Corrected as J. (7) "Delay line 104" stated on page 36, line 17 of the same.
of. Correct it to "delay line, 104." (8) Said page 38, line 9 [(25) above. (24)" should be corrected to "the above equations (25b) and (25)." (9) As stated in page 54, line 9 to page 55, line 10, ``This emphasis amount...set ttNfg as a method for increasing this emphasis amount.'' The easiest method is to increase the value of K in K, but the method of increasing the value of K in K is the easiest method, but it is possible to The emphasis circuit 190a and the de-emphasis circuit 190b are replaced by the pre-emphasis circuit of the present invention,
It may also be used in conjunction with a de-emphasis circuit.More specifically, in FIG. 15, 191, 192 are capacitors, 193. -194, 195, 196 are resistors, and this Z5N(a) pre-emphasis circuit 19
0a is connected in series with the pre-emphasis circuit of the present invention shown in the embodiment of FIG. 3, FIG. 9, FIG. 12 or FIG. 14(a) to constitute a pre-emphasis system, and The de-emphasis circuit 190b of FIG. 15(b) is connected in series with the de-emphasis circuit of the present invention shown in the embodiment of FIG. 6, FIG. 11, FIG. 13, or FIG. 14(b) to perform de-emphasis. Configure the system. According to the above configuration, the time constants T1 and T of the above equation (2),
(Capacitors 191, 192 and resistor 193 in Fig. 15,
194, 195, and 196) to a relatively large value.'' (10) Between lines 18 and 19 of page 56,
"In the above embodiment, the predetermined squared sine characteristic 1
For example, to obtain ``sin'' (ωT), a squared sine circuit whose amplitude characteristic is the same as the squared sine characteristic described above 10.97
．． 97D is used, but the present invention is not limited to this, and within the practically required frequency band of the input signal,
The present invention can also be applied to a circuit configured to have an amplitude characteristic that approximates the squared sine characteristic described above. In the example of FIG.
Although a case has been shown in which the above-mentioned squared sine characteristic is realized using the transversal filter 97 of taps, the present invention is not limited to this. For example, in the embodiment shown in FIG. It can also be applied when approximating the squared sine characteristic. That is, in general, by using 2n delay devices with a delay time of 2T' in cascade (the case of H=1 is shown in the ninth @ embodiment) and configuring a 2n+1 tap transversal filter, a predetermined frequency can be adjusted. The following approximation can be obtained in the band. sin2(ωT)=Σ at sin2(iωT')
(39) i=1 As a result, in a predetermined frequency band in which this approximation holds true, the required squared sine characteristic, which is the main focus of the present invention, can be approximately realized by the sum of a plurality of appropriate squared sine characteristics. it is obvious. As a result, in the embodiments shown in FIGS. 9 and 12, even when the delay time of the delay devices 91, 92, 9LD, and 92D is limited, by increasing the number of taps, the squared sine characteristic, which is the main focus of the present invention, can be achieved. It can be easily realized and the same effects as above can be obtained, all of which are in line with the gist of the present invention. ” to join. (11) Figure 15 of the drawings will be corrected as shown in the attached sheet. Claim 1 is a signal processing method for converting an input signal into a signal having predetermined frequency characteristics and re-converting it to the original frequency characteristic, wherein ω is the angular frequency of the input signal, S is the complex angular frequency, (S=j
ω), T is a constant with the unit of time, and is 0 or more ■1
Let m be an integer and input signal within a predetermined frequency band as (1+Ksin" (ωT)) ・exp (-2S
The signal is processed using the first transfer function approximated by the function T), and its output is expressed as exp (-mST) / (1+Ksin” ((I
IT) Process the signal sequentially using a second transfer function approximated by a function, and change the value of K in the first and second transfer functions according to the level of the high frequency component of the input signal. A signal processing method characterized by: 2. Expand and approximate the above second transfer function, and obtain m=10 [(1-to 1sin'' ((2ωT))・exp(-
2ST) ]X[(1- to 2sin2(2ωT))・
exp(4ST)]X[(1-K2sin2(2ωT)
2. The signal processing method according to claim 1, wherein the signal is processed using a transfer function approximated by a function: ).exp(4ST)]. 3. In a signal processing system that converts an input signal into a signal with predetermined frequency characteristics and reconverts it back to its original frequency characteristics, ω is the angular frequency of the input signal, S is the complex angular frequency (S= jω
), T is a constant having the unit of time, m is an integer, and is a real number greater than or equal to 0, and within a predetermined frequency band, (1+Ksin2(ωT) )・exp (−2ST)
means (2) for changing the coefficient according to the level of the high frequency component of the input signal;
5); and a first circuitry (33) comprising: exp(-msT) / (1+Ksin2(ωT)
), the second circuit network (63) has a transfer function approximated by a function, and changes the coefficient according to the level of the high frequency component of the input signal, ) is configured to cascadely supply the output from the second circuit network (63) to the second circuit network (63). 4. The second circuit network (63) is. [(1-to 1sin2(ωT))・5xp(-2ST)
]X[(1-, sin2(2(2ωT))・exp(
−4ST)]x [(1−K2sin2(2(+)T)
)・5xp(-4S T)]. means (44) for changing the coefficient to the coefficient according to the level of the high frequency component of the input signal; means (48) for changing the coefficient to 2 according to the level of the high frequency component of the input signal; means (51) for changing the coefficient by 3 according to the level of the high frequency component of the input signal; The signal processing device according to claim 3. 5. The second circuit network (63) has a transfer function approximated by the function (1-Kisin2(ωT)). 3 circuit network (6
o) and. (1-K2sin” (2(1) T))・exp(-
48T ) with a transfer function approximated by the function
with a circuit network (61). (1-Kasun2(2(2ωT))・exp(-4S
5. The signal processing device according to claim 3, further comprising a configuration in which a fifth circuit network (62) having a transfer function approximated by a function T) is cascaded. 6, the first circuit network (33), the third circuit network (6
0), the fourth circuit network (61), the fifth circuit network (61),
62). A squared sine function -sin2(NωT) (N is 1 or more) is composed of a series connection of an impedance circuit Z (11) formed by a ladder network of multiple inductances L and capacitances C and an admittance circuit Y (12). integer)
A squared sine circuit (10, 46a, 46
b) for delaying the input signal by a predetermined time of 2NT;
23゜43.47,50), and the above input signal is connected to the above squared sine circuit (10, 46a, 46
b) means for supplying. Means (25) for nonlinearly compressing the output signal from the squared sine circuit (10, 46a, 46b) according to the amplitude level
, 44, 48, 51) and means (26, 45, 4) for adding the output from the compression means and the output from the delay means.
9,52). The signal processing device according to claim 3, 4 or 5, having a configuration comprising: 7. In a signal processing system that converts an input signal into a signal with predetermined frequency characteristics and reconverts it back to the original frequency characteristic, ω is the angular frequency of the input signal, S is the complex angular frequency (S= jω
), T is a constant having the unit of time, m is an integer, is a positive real number, K1. Then, let K3 be a positive real number less than or equal to 1, and within a predetermined frequency band, [(1+Ksin2(ωT))・
exp(-2S T) ]X[(1-K, sin2(2
(1)T))・exp(-4S T)]X[(1-K2
sin2(2ω T)) exp(-4ST)], and means (25) for changing the coefficient according to the level of the high frequency component of the input signal; means (48) for changing the coefficient by 2 in accordance with the level of the high frequency component of the signal; and means (5) for changing the coefficient by 3 in accordance with the level of the high frequency component of the input signal.
1) and an eighth circuit network (64) including (1-K2sin2(ωT))・exp(-2S T)
means for changing the coefficient of the coefficient according to the level of the high-frequency component of the input signal;
44); and a third circuitry (60) comprising: A signal processing device comprising: The signal processing device is configured to cascadely supply the output from the eighth circuit network (64) to the third circuit network (60). 8. The eighth circuit network (64) is (1+Ksin” ((1)T))・exp (−2
a first circuit network (33) having a transfer function approximated by a function ST); (1- to 2sun” (2(1)T) :1exp (
4ST), and a fourth circuit network (61) having a transfer function approximated by a function: (1-, sun" (2(IIT)) "eXP
(4ST) with a transfer function approximated by the function
The signal processing device according to claim 7, comprising a configuration in which the circuit network and the circuit network are connected in cascade. 9. When T, T, (T) is a constant having the unit of time, the sixth circuit network (1+ST1) / (1+ST2) has a transfer function approximated by the function (1+ST1) / (1+ST2).
190a) has a configuration in which it is connected in cascade to the first circuit network (33) or the eighth circuit network (64), and a transfer function approximated by the function (1+5T2)/(1+ST2). The seventh circuit network (
190b) is cascade-connected to the second circuit network (63) or the third circuit network (6o), and the signal processing device according to claim 3 or 7, comprising: . Brave 5 times

Claims (1)

[Claims] 1. A signal processing method for converting an input signal into a signal having predetermined frequency characteristics and re-converting it to return to the original frequency characteristic, where ω is the angular frequency of the input signal, S is the complex angular frequency, (S=j
ω), T is a constant having the unit of time, K is a variable greater than or equal to 0, m is an integer, and within a predetermined frequency band, the input signal is (1+Ksin^2(ωT))・exp(−2ST) The signal is processed using the first transfer function approximated by the function exp(-mST)/(1+Ksin^2(ωT)) A signal processing method, comprising: changing the value of K in the first and second transfer functions according to the level of a high frequency component of the input signal. 2. Expand and approximate the above second transfer function, and obtain [(1-K_1sin^2(ωT))・exp(-2S
T)]×[(1-K_2sin^2(2ωT))・ex
p(-4ST)]×[(1-K_3sin^2(2ωT
2. The signal processing method according to claim 1, wherein the signal processing is performed using a transfer function approximated by a function: )).exp(-4ST)]. 3. In a signal processing system that converts an input signal into a signal with predetermined frequency characteristics and reconverts it back to its original frequency characteristics, ω is the angular frequency of the input signal, S is the complex angular frequency (S= jω
), T is a constant having the unit of time, m is an integer, and K is a real number greater than or equal to 0, and within a predetermined frequency band, it is approximated by the function (1+Ksin^2(ωT))・exp(−2ST). means (25) for changing the coefficients according to the level of the high frequency component of the input signal;
) and a first circuit network (33) containing exp(-mST)
/(1+Ksin^2(ωT)), and a second circuit network (63) that changes the coefficient K according to the level of the high frequency component of the input signal, A signal processing device characterized in that the output from the first circuit network (33) is supplied in cascade to the second circuit network (63). 4. The second circuit network (63) is [(1-K_1sin^2(ωT))・exp(-2S
T)]×[(1-K_2sin^2(2ωT))・ex
p(-4ST)]×[(1-K_3sin^2(2ωT
)). means (48) for changing the coefficient K_2 according to the level of the component;
), and means (51) for changing the coefficient K_3 according to the level of the high-frequency component of the input signal, the amplitude characteristic of which approximates 1/(1+Ksin^2(ωT)). The signal processing device according to claim 3, which has the following configuration. 5. The second circuit network (63) is (1-K_1sin^2(ωT))・exp(-2ST
), and (1-K_2sin^2(2ωT))・exp(-4S
A fourth circuit network (61) having a transfer function approximated by a function T), (1-K_3sin^2(2ωT))・exp(-4S
5. The signal processing device according to claim 3, further comprising a configuration in which a fifth circuit network (62) having a transfer function approximated by a function T) is cascaded. 6, the first circuit network (33), the third circuit network (6
0), the fourth circuit network (61), the fifth circuit network (61),
At least one of 62) is a squared sine function -sin composed of a series connection of an impedance circuit Z (11) and an admittance circuit Y (12) formed by a ladder network of a plurality of inductances L and capacitances C. A squared sine circuit (10, 46a, 4
means (23, 43, 47, 50) for delaying the input signal by 2NT for a predetermined time;
b), and means (25) for nonlinearly compressing the output signal from the squared sine circuit (10, 46a, 46b) according to the amplitude level.
, 44, 48, 51); and means (26, 45, 49, 52) for adding the output from the compression means and the output from the delay means. The signal processing device described in . 7. In a signal processing system that converts an input signal into a signal with predetermined frequency characteristics and reconverts it back to the original frequency characteristic, ω is the angular frequency of the input signal, S is the complex angular frequency (S= jω
), T is a constant having the unit of time, m is an integer, K is a positive real number, K_1, K_2, K_3 are positive real numbers of 1 or less, and within a predetermined frequency band, [(1+Ksin^2(ωT ))・exp(-2ST)
]×[(1-K_2sin^2(2ωT))・exp(
-4ST)]×[(1-K_3sin^2(2ωT))
exp(-4ST)], and means (25) for changing the coefficient K according to the level of the high-frequency component of the input signal; Means for changing the coefficient K_2 according to the level (
48), and means (51) for changing the coefficient K_3 according to the level of the high-frequency component of the input signal; exp(-2ST
), the third circuit network (60) includes means (44) for changing the coefficient K_1 according to the level of the high-frequency component of the input signal; A signal processing device characterized in that it is configured to supply the output from the eighth circuit network (64) to the third circuit network (60) in cascade. 8. The eighth circuit network (64) is the first circuit network (3
3) and (1-K_2sin^2(2ωT))・exp(-4S
A fourth circuit network (61) having a transfer function approximated by a function T), (1-K_3sin^2(2ωT))・exp(-4S
The signal processing device according to claim 7, further comprising: a fifth circuit network having a transfer function approximated by a function T); and a configuration in which the following are connected in cascade. 9. When T_1 and T_2 (T_1>T_2) are constants having the unit of time, the sixth circuit network (1+ST_1)/(1+ST_2) has a transfer function approximated by the function
90a) is the first circuit network (33) or the eighth circuit network (33).
and a seventh circuit network (64) having a transfer function approximated by the function (1+ST_2)/(1+ST_1).
90b) is connected to the second circuit network (63) or the third circuit network (63).
The signal processing device according to claim 3 or 7, comprising: a configuration connected in cascade to a circuit network (60);