JPH0346161A - Non-linear de-emphasis circuit - Google Patents

Abstract

PURPOSE:To make a response at high speed by inputting input data and the output of a feedback circuit to a table and obtaining a de-emphasis output from the table. CONSTITUTION:The data table is written into a ROM 1 in advance and this table inputs an input digital signal x' to an output dmu of an infinite response digital IIR filter 2 and outputs an emphasis output y'. For an LPF 2, an LPF with the same time constant as the HPF of a conventional non-linear de- emphasis circuit is composed of the IIR filter and a feedback circuit with a delay circuit is constituted. Thus, the de-emphasis output is obtained from the ROM 1 of the table and this feedback circuit defines the low area component of the de-emphasis output as the input to the ROM 1 of the table.

Description

Detailed Description of the Invention [Industrial Application Field 1] The present invention relates to a nonlinear de-emphasis circuit applied to a system in which, for example, a video signal is transmitted through a noisy transmission path with a limited dynamo power range. do.

[Prior Art] Conventionally, a circuit as shown in FIG. 4 has been proposed as this type of nonlinear emphasis circuit. Further, as a nonlinear de-emphasis circuit, a circuit as shown in FIG. 5 has been proposed.

In FIG. 4, an input video signal X is applied to a bypass filter (HPF) 41 to separate its high frequency components. The separated high-frequency components are amplitude-compressed by a nonlinear amplifier (hereinafter referred to as NLA) 42.

The NLA 42 has input/output characteristics as shown in FIG. 6, for example, and has such input/output characteristics that the output amplitude is limited when the input signal amplitude is large.

The output W of the NLA 42 is added to the input video signal X by an adder circuit 43, and outputted as a high-frequency emphasized signal y. In FIG. 4, the HPF 41 is constituted by, for example, a high-pass filter using CR, and the NLA 42 is constituted by, for example, a logarithmic compression circuit using a diode.

The frequency characteristic of the output y is, for example, a so-called nonlinear emphasis characteristic in which the amount of high-frequency enhancement changes depending on the input level, as shown in FIG.

After passing the high-frequency enhanced video signal through a transmission system with a lot of noise and a limited dynamic range, such as a magnetic recording/reproducing system such as a VTR, a de-emphasis circuit having characteristics opposite to the above-mentioned emphasis circuit is applied. By suppressing the high-frequency components that have been enhanced, the noise components added by the transmission system can be suppressed and an image with a high S/N ratio can be obtained. Furthermore, since the amount of emphasis is small for a signal with a large level, the dynamic range does not increase, and distortion due to the dynamic range limit of the transmission path does not occur.

Next, the de-emphasis circuit will be explained.

In FIG. 5, the human power X° is applied to a subtracter 53, and the output of the subtracter 53 becomes a de-emphasis output y'. The output y° is added to the IPF 41 and NLA 42 to obtain an amplitude-compressed high frequency component W, which is fed back to the subtracter 53. If the characteristics of HPF 41 and NLA42 are the same as those of (1PF41%NLA42) in the emphasis circuit in Figure 4, the transfer characteristics in Figures 4 and 5 will be opposite to each other, and the transfer characteristics that pass through both will be perfect. becomes 1.

[Problems to be Solved by the Invention] However, in the emphasis circuit and de-emphasis circuit having the characteristics as described above, it is necessary to use a nonlinear amplitude compressor, and this is realized using, for example, a diode logarithmic compressor. In general, it has been difficult for emphasis circuits having such characteristics to achieve high precision and stability, and to obtain good high frequency characteristics.

Furthermore, since the de-emphasis circuit in particular is a feedback circuit, it is particularly required that the frequency characteristics of the logarithmic compressor be stable over a wide band.

Therefore, it has been difficult to apply such a de-emphasis circuit to devices that require wideband and highly accurate processing, such as VTRs that record wideband signals such as high-definition television signals.

Against this background, it is an object of the present invention to provide a nonlinear de-emphasis circuit that can process broadband signals with high precision.

[Means for solving the problem] For this purpose, the nonlinear de-emphasis circuit of the present invention includes a table in which nonlinear characteristics are written,
The feedback circuit includes a delay means, and the table is configured to input human data and the output of the feedback unit to obtain a de-emphasis output from the table, and the feedback circuit is configured to input low frequency output of the de-emphasis output. The composition is such that the ingredients are prepared manually at the table.

[Function] By configuring as described above, since a table is used for the nonlinear characteristics themselves, processing is fast and highly accurate characteristics can be obtained, and since the feedback circuit can be configured easily, the processing time can be shortened. Overall faster response,
That is, it is possible to realize a wide band of signals to be processed.

[Example] Examples of the present invention will be described below.

FIG. 1 is a diagram showing the configuration of a de-emphasis circuit as an embodiment of the present invention. In the figure, reference numeral 1 indicates a human-powered digital signal
nite Impulse Re5ponce data table is written in advance (ROM (Road 0n
ly Memory), 2 is an LPF with the same time constant as the HPF41 shown in FIG. 5 of the conventional example described above.
This is an IIR-LPF composed of filters.

FIG. 2 shows the de-emphasis circuit shown in FIG.
It shows the configuration of the R-LPF2 part in detail,
Blocks that are the same as in FIG. 1 are numbered the same.

In FIG. 2, 24 is a subtracter that takes the difference between the de-emphasis output y in FIG. The coefficient multiplier 22 is a D-type flip-flop (DFF) that delays the output of the coefficient multiplier 23 and the output dn of the IIR-LPF 2 by a sampling period.

Before explaining the de-emphasis circuit of this embodiment shown in FIGS. 1 and 2, we will explain the process of configuring HPF41, NL, and A42 in the de-emphasis circuit of FIG. 5 with digital circuits. do. In Fig. 5, the transfer function from the de-emphasis output y to the output V of the HPF 41 is expressed as follows: T is the sampling period of the human data, CR is the HPF
If 2 is a coefficient determined by CR for the time constant, k, of 41, then by selecting 1, a 11'R filter with characteristics almost identical to PF41 can be constructed by CR.Furthermore, the characteristics of NLA42 are RO where logarithmically compressed data table is written
M, and its properties can be expressed as W − et [V] −
...(2). However, kn is a function having nonlinear characteristics.

When finally configuring the de-emphasis circuit, y'=x'
-W.

Next, consider how to construct equation (3) using an actual digital circuit. Since the feedback loop must necessarily be separated by a D-type flip-flop, the following equation is modified.

Then, we get 2 (y'-du)...(4) for -. du has one data delay for y. Substituting this equation (4) into equation (3), we get y'-x'
-kn[k2(y'-du)] ・”(5
). Since equation (5) is an equation for calculating yo using Xo and du, we can convert it into a function F of Xo and du.
Expressed as n[], y'=Fn[x', dul=・
(6).

FIG. 1 shows this in block diagram form.

The de-emphasis output y' is obtained by calculating du with the IIR-LPF 2 and inputting Xo and du into the ROM 1 in which formula (6) is written in a tabular form.

That is, the configuration of the IIR-LPF 2 shown in FIG. 2 shows a specific configuration for determining du from the de-emphasis output y°.

Therefore, the data μ before the delay can be expressed as . Therefore, the configuration of the IIR filter shown in FIG. 2 is obtained.

As is clear from FIG. 2, since du is latched by the DFF 21, a feedback loop as shown in FIG. 1 can be constructed.

Furthermore, by substituting equation (6) into equation (7), U in equation (7) becomes (Fn[x, dul −
du)-Gn[x, dul
...It can be expressed as a function of x' and du as shown in (8). Therefore, μ can also be made into a table by inputting x and du.

Figure 3 shows a circuit that implements this, where 3 is a ROM, 2
1 is DFF. Input X° and output du of DFF21
is input to ROM3.

The functions of equations (6) and (8) are written in the form of a table in the ROM 3, and the output y' and U to be input to the DFF 21 are output.

By using the above configuration, an emphasis circuit having characteristics similar to the nonlinear emphasis characteristics using an ideal analog circuit can be obtained. Moreover, since the above configuration achieves nonlinear amplitude compression using a table, highly accurate nonlinear processing is possible, and wideband signals can be processed as long as the calculation speed of the calculation circuit in the feedback circuit allows. can be processed. Therefore,
Compared to the circuit of the embodiment shown in FIG. 1, the circuit of the embodiment shown in FIG. 3 enables faster processing. However, the circuit of the embodiment shown in FIG. 3 requires a table with a larger memory capacity than the circuit of the embodiment shown in FIG.

In the above embodiment, both input and output were explained as digital video signals, but when applied to an analog signal processing system used in an analog VTR etc., the circuits shown in FIGS. 1 and 3 may be used. An A/D converter and a D/D converter are installed in the front and rear stages respectively.
It is sufficient to provide each A converter.

Further, in the above embodiment, a logarithmic compression characteristic was assumed as an example of a nonlinear characteristic, but by changing the table, this characteristic can be changed to an arbitrary characteristic, for example, a broken line compression characteristic.
Compression characteristics that cannot be achieved with analog circuits can be obtained. Thereby, for example, de-emphasis characteristics corresponding to a large amount of emphasis, which are difficult to employ from the viewpoint of stability, can be stably obtained.

[Effects of the Invention] As explained above, according to the present invention, a nonlinear de-emphasis circuit capable of stable and highly accurate processing even for wideband signals can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a de-emphasis circuit as an embodiment of the present invention, FIG. 2 is a diagram showing a specific configuration example of the IIR filter in FIG. 1, and FIG. 3 is a diagram showing a specific configuration example of the IIR filter in FIG. FIG. 4 is a diagram showing an example of the configuration of a conventional nonlinear de-emphasis circuit; FIG. 5 is a diagram showing an example of the configuration of a conventional non-linear de-emphasis circuit; The figure shows the frequency characteristics of the emphasis circuit in Figure 4, '! FIG. J7 is a diagram showing the input/output characteristics of the nonlinear amplifier in FIG. 4. In the figure, X° is the input digital video signal, yo is the output digital video signal%, 1 is the ROM table corresponding to the function Fn, 2 is the infinite response digital low-pass filter, 3 is the ROM table corresponding to the function Mn, and 21 is the D-type flip-flop. 22 is an adder, 23 is a coefficient unit, and 24 is a subtracter. →liT liquid school

Claims (4)

[Claims] (1) Consisting of a table in which nonlinear characteristics are written and a feedback circuit including a delay means, input data and the output of the feedback circuit are input to the table,
A nonlinear de-emphasis circuit configured to obtain a de-emphasis output from the table, and wherein the feedback circuit inputs a low frequency component of the de-emphasis output to the table. (2) The feedback circuit comprises an infinite response digital low-pass filter to which the de-emphasis output is input, and the output of the filter is supplied to the table together with the input data. Nonlinear de-emphasis circuit described in ). (3) The low-pass filter includes a subtracter whose one input is the de-emphasis output, a coefficient unit to which the output of the subtracter is supplied, and an accumulator to which the output of the coefficient unit is supplied. 2. The nonlinear de-emphasis circuit according to claim 2, wherein the output of the accumulator is used as a filtering output and is also used as the other input of the subtracter. (4) The table outputs data related to the low frequency component of the de-emphasis output in parallel with the de-emphasis output, and the feedback circuit delays the data related to the low frequency component and inputs the delayed data to the table. A nonlinear de-emphasis circuit according to claim 1, characterized in that the nonlinear de-emphasis circuit comprises a circuit.