JPS62278838A - Clock signal regeneration circuit - Google Patents

Abstract

PURPOSE:To prevent a regeneration clock from being influenced by noise even under the drastic fading environment by providing a signal strength detecting part and a free run circuit to free-run a clock signal at a clock reproducing part based upon the detecting signal. CONSTITUTION:To a signal strength detecting device 4 connected to an IF amplifier 3, a deciding comparator 7 to form a free run circuit is connected together with a free run gate 12 of a PLL circuit 19. The IF amplifier 3 supplies the signal strength information of the receiving signal to the signal strength detecting device 4, the detecting device 4, thus, obtains a direct current signal in proportion to a logarithm and the signal is sent to the deciding comparator circuit 7. Thus, the presence and absence of fading are decided. When the fading occurs, the signal of a logic '0' is outputted from the circuit 7 as a free run request signal, the gate 12 is opened and a correcting request signal is not outputted to a variable phase frequency dividing circuit 10. When the fading is not executed, the signal of a logic 1 is outputted as a free run request signal, the gate 12 is opened, the correcting request signal is outputted to the frequency dividing circuit 10, and the PLL circuit 19 executes the PLL action. When the fading occurs, the regeneration clock signal of the accuracy of a referance clock is outputted while the frequency dividing circuit 10 keeps the phase of the clock of a receiving signal.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a clock signal regeneration circuit that regenerates a clock signal for reproducing digital data signals in mobile communications such as car telephones. It is.

[Prior art]

2. Description of the Related Art Conventionally, in general, in mobile communications such as car telephones, digital data signals have been encoded in a predetermined manner, such as Manchester code, and then transmitted wirelessly.

When receiving the transmitted signal and extracting the clock signal, a phase-locked loop circuit (hereinafter referred to as a PLL circuit) or the like is used to reproduce the clock signal. As shown in FIG. 3, the conventional device for receiving and reproducing the transmitted digital data signal includes an antenna 1, a front end 2, and an intermediate frequency amplifier (hereinafter referred to as I).
(referred to as F amplifier) 3, a wave detector 5, a clock information extraction circuit 6, and a digital PLL circuit 25 are connected in this order. The received radio waves input from the antenna 1 are amplified and frequency converted by the front end 2, further amplified by the IF amplifier 3, and detected by the detector 5.

However, with the above-mentioned conventional receiver, when the receiver is in an environment where severe fading occurs due to the movement of a mobile object, such as a car phone, the reproduced clock signal may be disturbed by the increase in noise caused by the fading. be. In this case, simply changing the characteristics of the PLL circuit 25 will
This has the disadvantage that the clock signal cannot be avoided from being disturbed by this noise.

[Purpose of the invention]

The present invention has been made in consideration of the above-mentioned conventional problems, and it is possible to reliably reproduce the recovered clock without being affected by noise even under the severe fading environment peculiar to mobile communications such as car telephones. It is an object of the present invention to provide a clock signal regeneration circuit that can maintain and perform stable clock regeneration.

[Structure of the invention]

In order to achieve the above object, a clock signal regeneration circuit according to the present invention receives a digital signal that has been encoded in a predetermined manner and transmitted through a communication channel of wireless communication, and generates a clock signal for clock regeneration. A clock signal regeneration circuit having a regeneration section is provided with a signal strength detection section and a free run circuit that causes the clock signal to free run in the clock regeneration section based on the detection signal of the signal strength detection section, and is used in a severe fading environment. This feature is characterized in that the reproduction black mark 7 is reliably held without being affected by noise even if it is located at the bottom.

〔Example〕

An embodiment of the present invention will be described below based on FIGS. 1 and 2.

As shown in FIG. 1, the clock signal regeneration circuit includes an antenna 1, a front end 2, an IF amplifier 3, a detector 5, a clock information extraction circuit 6, and a digital PLL circuit 19 connected in this order. A signal strength detector 4 is connected to the IF amplifier 3 .

The signal strength detector 4 includes a free run gate 12, which will be described later.
A determination comparator 7 forming a free run circuit is also connected thereto. The output signal line 13 of the judgment comparator 7 is
It is connected to the free run gate 12 of the digital PLL circuit 19. The digital PLL circuit 19 includes a phase comparator 8 to which the output signal of the clock information extraction circuit 6 is input.
, a loop filter 9, a free run gate 12, and a variable phase frequency divider 10 are connected in this order. and,
A reference clock signal obtained from a reference clock generator 11 is manually input to the phase comparator 8, loop filter 9, and variable phase frequency divider 10. Further, a lead/lag signal line 20, which is one of the output signal lines of the loop filter 9, is connected to a variable phase frequency divider 10. A feedback signal 23 from the variable phase frequency divider 10 is connected to the loop filter 9. The recovered clock signal, which is the output of the variable phase frequency divider 10, is input to the phase comparator 8.

In the above configuration, the received signal inputted to the antenna 1 is amplified and frequency converted by the front end 2,
It is input to the IF amplifier 3. The IF amplifier 3 amplifies this signal and at the same time provides signal strength information of this signal to the signal strength detector 4.

The signal strength detector 4 obtains a logarithmically proportional DC signal using the signal strength information based on the received electric field. This DC signal is sent to the determination comparator 7. This determination comparator 7 determines the presence or absence of fading based on the magnitude of the DC signal depending on the strength of the received electric field. On the other hand, the output signal of the IF amplifier 3 is detected by a detector 5, and a clock information extraction circuit 6 extracts a lock component necessary for clock recovery from the encoded signal. This extracted clock information signal is sent to the digital PLL circuit 19. Based on this clock information signal, the digital PLL circuit 19 performs clock recovery. A phase comparator 8 compares the phase of the clock information signal with the reproduced clock signal. As a result, a phase error signal is sent from the phase comparator 8 to the loop filter 9.

The loop filter 9 outputs a lead/lag signal and a correction request signal based on the phase error signal. Here, when fading occurs, a signal of low level, that is, logic O, is output from the determination comparator 7 as a free run request signal, and is input to the free run gate 12.

As a result, the free run gate 12 is opened, so that the correction request signal is not output to the variable phase frequency divider 10.

When there is no fading and the received electric field is high, the determination comparator 7 outputs a high level, that is, a logic 1 signal as a free run request signal, and inputs it to the free run gate 12. As a result, the free run gate 12 closes, and the correction request signal is output to the variable phase frequency divider 10. Therefore, when the received electric field is high because no fading has occurred, the digital PLL circuit 19:
Performs PLL operation. When fading occurs and the received electric field is low, the variable phase frequency divider 10 maintains the clock phase of the received signal and outputs a recovered clock signal with the accuracy of the reference clock.

This will be explained in more detail based on FIG. Figure 2 shows the judgment comparator 7 and free run gate 1 shown in Figure 1.
2 shows the variable phase frequency divider 10 and the like in detail.

The circuit of the judgment comparator 7 includes a comparator 7as, a comparison level adjuster 7b, and a pull-up resistor 7C. A free run request signal line 13, which is an output signal of the comparator 7a, is connected to an input terminal of a free run gate 12 consisting of an AND circuit. The output signal line of the free run gate 12 is connected to the input terminal A of the counter 10a and the Nandt gate 10d. Nantes Gate 1
0a also uses the lead/lag signal as an input signal, and the inverter 10
c and the input terminal of the counter 10a. The inverter 10c is connected to the B terminal and C terminal of the counter 10a. The RCo terminal of the counter 10a has
The CK terminal of the N frequency divider 10b and the input terminal of the inverter 10e are connected. The output terminal of the inverter 10e is connected to the Load terminal of the counter 10a, and is output as a phase correction amount pulse. A recovered clock signal is output from the output terminal of the N frequency divider 10b.

In the above configuration, the counter 10a can be preset, and a 74LS163 logic integrated circuit is used. The preset value is Free Run Gate 12.
is determined by the Nant gate 10d and the inverter 10c. If you do not need phase correction of the clock signal,
The counter 10a is preset to "8" and divides the input reference clock signal by eight. The reference clock signal is frequency-divided by BXN by this output and the N frequency divider 10b, and becomes a reproduced clock signal. Therefore, if the transmission speed is B [bits/second] and the frequency of the reference clock is 8XNXB (Hz), then the digital PLL
The frequency of the reproduced clock signal that free-runs the circuit 19 can be made to match the transmission speed. When the received electric field is low due to fading, the free run request signal from the determination comparator 7 outputs a logic O, and the output from the free run gate 12 also becomes a logic O, so that the correction request signal is not input to the counter 10a. As a result, the preset value of the counter 10a becomes "8", and the reproduced clock signal free runs in the digital PLL circuit 19. When there is no fading and the received electric field is high, the free run request signal outputs logic 1, and free run gate 1 is output.
2 also outputs a logic 1 because a logic 1 correction request signal is input. Therefore, in the counter 10a,
The preset value is changed from "8" to "7" or "9" by the lead/lag signal input to the Nantes gate 10d. As a result, the phase of the reference clock signal is corrected for each period, and the phase synchronization operation is performed for the entire reproduced clock signal.

〔Effect of the invention〕

As described above, the clock signal regeneration circuit of the present invention has a clock regeneration unit that receives a predetermined encoded digital signal transmitted through a wireless communication channel and performs clock regeneration. The signal reproducing circuit is provided with a signal strength detecting section and a free run circuit that causes the clock signal to free run in the clock reproducing section based on the detection signal of the signal strength detecting section.

As a result, when the received electric field decreases due to fading, etc., even if noise is added to the phase comparator in the clock recovery section, the recovered clock signal is free-run in the clock recovery section, and the synchronization of the recovered clock signal is disrupted. This reduces the possibility that the clock will be regenerated, and has the effect that stable clock reproduction can be performed.

[Brief explanation of the drawing]

1 and 2 show an embodiment of the present invention, in which FIG. 1 is a block diagram showing a clock signal regeneration circuit;
FIG. 2 is a block diagram showing details of part of the decision comparator and digital PLL circuit, and FIG. 3 is a block diagram showing a conventional clock signal regeneration circuit. 4 is a signal strength detector, 7 is a judgment comparator (free run circuit), 8 is a phase comparator, 9 is a loop filter, 10
1 is a variable phase frequency divider, 11 is a reference clock signal regeneration circuit generator, 12 is a free run gate (free run circuit), 1
9 is a digital PLL circuit (clock regeneration section).

Claims (1)

[Claims] 1. In a clock signal regeneration circuit having a clock regeneration unit that receives a digital signal that has been encoded in a predetermined manner and transmitted through a communication channel of wireless communication, and performs clock regeneration, the signal strength detection unit and the signal A clock signal reproducing circuit comprising: a free-run circuit that causes the clock signal to free-run in the clock reproducing section based on a detection signal of the intensity detecting section.