JPH01164151A - Code deciding reference voltage generation system - Google Patents

Abstract

PURPOSE:To always obtain the correct decided result of the code of a demodulated output by using a reference voltage following the central value of an eye pattern. CONSTITUTION:The voltage of a demodulated signal is stored and held in a capacitor 25 at specified timing prior to code deciding timing. Next, the code of the demodulated signal is decided at the code deciding timing, and the voltage level of the demodulated signal at the specified timing is estimated, and a switch 27 corresponding to said voltage level is operated, and the voltage of the difference between the voltage of the demodulated signal stored and held in the capacitor 25 at the specified timing and the reference voltage held in the capacitor 31 is held in the capacitor 28. The capacitors 28 are provided correspondingly to the kinds portion of the voltage levels in number, and the voltages they held are summed, and is made to pass through a low pass filter and makes the reference voltage. Thus, the voltage following the central value of the demodulated signal is obtained, and the decision which is never influenced by the central value variation due to DC cutoff and has few error can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for generating a reference voltage of a judgment voltage used for code judgment necessary for demodulating a signal modulated by a digital signal.

(Prior Art) In recent years, there has been a demand for wireless transmission of digital signals. Single Channel Per carrier, especially for mobile radio
In the Carrier) method, the binary digital signal is directly FM modulated, or the binary digital signal is passed through a low frequency filter (hereinafter referred to as LPF) and then FM modulated to narrow the transmission bandwidth. methods etc. have been adopted.

The method using a Gaussian filter as the LPF is CMS.
K (Gausgian Filter Manipu
-Lated Minimum 5hift Key
It is a modulation method with an extremely narrow band. There is also a method in which a binary digital signal is converted into a multi-value signal, for example, a digital signal, and then subjected to F'M modulation through an LPF.

Any of the above modulation methods can be considered as a binary or multi-value frequency modulated wave. Since these frequency modulated waves contain a DC component as is clear from their generation process, the DC component must be taken into account throughout the modulation process, transmission process, and demodulation process. However, transmission of this DC component is extremely difficult for the following two reasons.

That is, (a) The transmitting frequency and the receiving frequency each fluctuate due to changes in environmental conditions such as temperature, and their relative deviation appears as a deviation in DC potential upon demodulation.

In order to prevent this deviation in DC potential, a DC cutoff circuit is often installed on the output side of the frequency discriminator of the receiver.

In recent years, frequency synthesizers have been used to generate carrier waves due to the need to switch the transmission frequency, but when performing FM modulation on this, the circuit becomes extremely complex when even the DC component is taken into consideration. .

For the above reasons, a method that does not transmit the DC component is desired, but another problem occurs when the DC component is not transmitted.

This problem will be explained below using the case of binary frequency modulation as an example.

FIG. 2 is a block diagram of the transmitter, in which 1 is an input terminal, 2 is a modulator, 3 is an amplifier, and 4 is a transmitting antenna. FIG. 3 is a block diagram of a conventional receiver, in which 5 is a receiving antenna;
6 is a high frequency amplifier, 2 is a mixer for frequency conversion, 8 is a local oscillator, 9 is an intermediate frequency amplifier including a band F wave generator, 10 is a frequency discriminator, 11 is a DC cutoff circuit, 12 is an analog comparator, 13 is The output terminal 14 is an input terminal into which a sign determination reference voltage is input.

First, connect the input terminal l of the transmitter shown in FIG.
When input data shown in is added, the modulator 2 performs frequency modulation based on this input data, and the frequency modulated signal is amplified by the amplifier 3 and transmitted from the transmission antenna 4. The transmitted radio waves are captured by the receiving antenna 5 of the receiver shown in FIG. 3, amplified by the high frequency amplifier 6, frequency converted by the local oscillation output from the local oscillator 8 in the frequency conversion mixer 2, and converted into an intermediate frequency. Become. This intermediate frequency is amplified by an intermediate frequency amplifier 9 including a band F wave filter, and frequency detected by a frequency discriminator 10.

This detected output has its DC component cut off by a DC cutoff circuit 11, and becomes a demodulated output with a waveform as shown in FIG. 4(b). The analog comparator 12 compares the demodulated output with the sign determination reference voltage input from the input terminal 14, and if the V-pel of the demodulated output is higher, it outputs "1" to the output terminal 13.
Conversely, if it is low, "0" is output.

As shown in FIG. 4(b), the waveform of the demodulated output is (,
) is different from the input data waveform shown in (). That is, the waveform of the demodulated output is subjected to waveform distortion due to the effects of the modulator 2 of the transmitter shown in FIG. 2 and the DC cutoff circuit 11 of the receiver shown in FIG. 3, and its center value is as shown in FIG. 4(b). It fluctuates as shown by the dotted line. However, since the sign determination reference voltage from the input terminal 14 is a fixed voltage as shown by A in FIG. In some cases, the transmission error rate worsened due to incorrect determination.

This is especially true when multileveling is used to narrow the transmission band, and when G
This effect is large when there are multiple values in several songs, such as MSK.

Figure 5 is an example of a delayed phase detection circuit that demodulates a digital phase modulated signal such as GMSK (for example,
8-112805 "Delayed phase detection circuit").

The operation of the circuit shown in FIG. 5 will be briefly described below.

In FIG. 5, a digital phase modulated signal such as GMSK is received by a receiving antenna 5, amplified by a high frequency amplifier 6, and mixed with a local oscillation output from a local oscillator 8 in a frequency conversion mixer 7 to generate an intermediate frequency signal. Convert to band F
The signal is amplified by an intermediate frequency amplifier 9 including a frequency converter, passed through a limiter 15, and divided by a 1/n frequency divider 16. The frequency and phase modulation degree are set to 1/n by the 1/n frequency divider 16 (n is 2
or larger integer). The output of the 1/n frequency divider 16 is applied to one terminal of an exclusive OR circuit 17,
To the other terminal, a delay circuit 18 applies a signal delayed by a certain amount of time, for example, a time corresponding to 2 bits of digital modulation of the input signal. The output of the exclusive OR circuit 17 is a low-frequency F wave generator 19, a DC cutoff circuit 20, and an operational amplifier 2.
is applied to output terminal 22 through . The output of the output terminal 22 is added to a con leak (not shown) to obtain a demodulated signal of "1" or rOJ. Figure 6 shows the low-frequency F wave device 19.
This is the output of Aibatan. The Ainogutan receives GMSK with Bb-T=0.25, and the delay circuit 1
The case is shown in which the delay time of 8 is selected to correspond to 2 bits of the input digital signal. However, Bb is the bandwidth of the Gaussian filter used during modulation, and T is the reciprocal of the bit rate of the digital signal. The horizontal axis of the eye d' button in FIG. 6 indicates the passage of time, and T indicates the time equivalent to one bit.

The Aino 4-tan is shown in Fig. 7 (
It can be classified into four types as shown in a), (b), (c), and 9 (d). (a) is time 0-T, T~2
When T, the bit (hereinafter referred to as the leading bit) is 1,
If the bit exceeds the level indicated by La at time 3T, it is determined that the bit at times 2T to 3T is 1, and if it does not exceed La, it is determined to be 0.

Similarly, (b) shows the case where the leading bit is 0.1, and the judgment level is I4. It is. (,?) has the leading bits 1, 0 and the determination level is Lc, and (d) has the leading bits 0, 0 and the determination level is Ld. If the determination level is determined in accordance with the preceding bit in this way, extremely efficient detection can be performed.

However, as in the case of binary frequency modulation, if the DC component is lost during the modulation process, transmission process, and demodulation process, the center value C of the eye gap shown in Figure 6 will fluctuate, and the value shown in Figure 7 will change. Since the indicated determination levels La, Lb, Lc, and Ld are fixed voltages, the determination margin becomes small and errors in determination are likely to occur.

(Problems to be Solved by the Invention) As explained above, in conventional receivers, the center voltage of the demodulated signal fluctuates due to the interruption of the DC component.
Since the determination voltage that is the reference for code determination is fixed, the determination margin fluctuates and sometimes becomes smaller, resulting in errors in determination. To solve this problem, a reference voltage is required to generate a determination voltage that follows fluctuations in the center voltage of the demodulated signal.

An object of the present invention is to provide a sign determination reference voltage generation method that generates a reference voltage that follows fluctuations in the center voltage of a demodulated signal.

(Means for Solving the Problems) The present invention provides a code judgment reference voltage generation method for generating a reference voltage for a judgment voltage used in code judgment of a demodulated signal obtained by demodulating a signal modulated by a digital signal. determines the sign of the demodulated signal and selects the corresponding voltage holding means, and at a specific timing prior to the sign determination timing, the voltage of the difference between the pre-stored demodulated signal voltage and the reference voltage is determined by the selected voltage holding means. and adding the voltages held by the selected voltage holding means and each of the remaining voltage holding means and passing it through a low-frequency P-wave device, and setting the output voltage of the low-pass F-wave device as a reference voltage. This is a characteristic code determination reference voltage generation method.

(Operation) The voltage of the demodulated signal is stored and held at a specific timing prior to the sign determination timing. Next, the code of the demodulated signal is determined at the code determination timing, and based on the result, the voltage level of the demodulated signal at the specific timing is assumed,
A voltage holding means corresponding to the voltage level is operated to hold the voltage difference between the voltage of the demodulated signal stored and held at the specific timing and the reference voltage. Voltage holding means are provided for each type of voltage level, and for each sign determination, the voltage of the demodulated signal at a specific timing is held in the voltage holding means corresponding to the voltage level.

The voltages held by each of the voltage holding means are added and passed through a low-frequency F wave generator to become a reference voltage. Since the reference voltage is the center value of the voltages held in each of the voltage holding means, it becomes a voltage that follows the center value of the demodulated signal. Therefore,
If the sign of the demodulated signal is judged using the judgment voltage for sign judgment based on the reference voltage, it is possible to realize judgment with fewer errors without being affected by center value fluctuations due to DC cutoff.

(Embodiment) FIG. 1 is a block diagram of an embodiment of the present invention, in which 23 is an input terminal into which a demodulated signal is input, and 24 has one end connected to the input terminal 23.
25 is a capacitor whose one end is grounded and the other end is connected to the other end of the CMOS switch 24; 26 is a capacitor whose input terminal is connected to the CMOS switch 24;
The operational amplifier 27 connected to the other end and the capacitor 25 is composed of five CMOS switches 27-1 to 27-5, and one end of each of the CMOS switches 27-1 to 27-5 is the output of the operational amplifier 26. CMOS switch group 28 commonly connected to the end is five capacitors 28
-1 to 28-5, each capacitor 28-1
The CMOS switch 27 to which one end of ~28-5 corresponds
A group of capacitors connected to the other end of -1 to 27-5,
29 is composed of five operational amplifiers 29-1 to 29-5, and the input terminal of each operational amplifier 29-1 to 29-5 is connected to each C
A group of operational amplifiers each connected to the other end of the MOS switches 27-1 to 27-5 and the one end of each capacitor 28-1 to 28-5, 30 is each operational amplifier 29-1 to 29-2.
Each operational amplifier 29-1 to 9-5 is connected to the output terminal of 9-5.
A capacitor 31 has one end grounded and the other end connected to the output end of the adder circuit 30 and the other end of each of the capacitors 28-1 to 28-5, 32 The input terminals are operational amplifiers 29-1 and 29-2.
．． 29-4, 25-5 and a judgment voltage generation circuit that is connected to the output end of the adder circuit 30 and generates judgment levels L'a + "b +Lc, Ld; 33 is a judgment voltage generation circuit 32;
The determination level La is connected to the determination level La.

A changeover switch that switches and outputs "b,"e+"d, 3
4 is an analog comparator whose input terminal is connected to the input terminal 23 and the output terminal of the changeover switch 33, and 35 is an analog comparator whose input terminal is connected to the output terminal of the analog comparator 34 and whose output terminal is connected to the output terminal 36. 37 is a timing circuit that outputs a timing signal to the CMOS switch 24 and the code string discrimination circuit 35.

The operation of the circuit shown in FIG. 1 will be described below, taking as an example a case where a demodulated signal having an eye/'P tan shown in FIG. 6 is applied to the input terminal 23.

In this embodiment, the eye pattern shown in FIG. 6 is created by combining the preceding bits as shown in FIG. 7(a).

Classified into four categories: (b), (e), and (d), and 3
The sign determination is performed at T, but by focusing on the fact that the I-GUTAN shown in Figure 6 is concentrated in five parts between times 2T and 3T, the sign determination is performed using these parts. It generates a reference voltage.

First, from the timing circuit 37 shown in FIG.
), as shown in (f), a short Noculus is output at time 2.5T, and the CMOS switch 24 is closed. As a result, the demodulated signal at time 2.5T is stored and held in the capacitor 25. Then, from the timing circuit 37, as shown in FIGS. 7(g) and 7(h), the time 3
Short in T? The code string discrimination circuit 35 outputs the signal to the code string discrimination circuit 35. The code string discrimination circuit 35 sends a predetermined control signal to the changeover switch 33 based on the code of the past 2 bits, and also sends a predetermined control signal to the changeover switch 33 based on the code of the signal output from the analog comparator 34. A control signal is output to close the gate. For example, in Figure 7 (
In case a), since the preceding bits are 1, 1 at time 3T, the code string discrimination circuit 35 sends a control signal to the changeover switch 33 to select La as the determination voltage. An analog comparator 34 compares the demodulated signal with the L&.

If the demodulated signal at time 3T is larger than La, that is, if the sign determination is "1", then the voltage stored and held at time 2.5T is (a) in FIG. 7(,). The code string discrimination circuit 35 is a CMOS switch group 2
7, the CMOS switch 27-1 is closed, and the capacitor 28-1 is charged with a voltage equal to the difference between the voltage of the capacitor 25 and the voltage of the capacitor 3I.

Similarly, in FIG. 7(,), if the result of the sign determination at time 3T is "0", the voltage stored and held at time 2.5T is (b). At time 3T, the CMOS switch 27-2 is closed and the capacitor 28-2 is charged with a voltage equal to the difference between the voltage of the capacitor 25 and the voltage of the capacitor 31. Similarly, Figure 7 (with)
(leading pitch) 0.1), the sign determination result is “1”.
”, then ° is (b), so the CMOS switch 27-
2 is closed to charge the capacitor 28-2, and when the result of the sign determination is "0", it is r-3, so the CMOS switch 27-3 is closed and the capacitor 28-3 is charged.

In the case of FIG. 9(C) (preceding pip) 1, 0), when the sign determination result is "1" (c), the CMOS switches 27-3 are closed and the capacitor 28-3 is charged, and the sign is When the result of the determination is "0"), the CMOS switch 27-4 is closed and the capacitor 28-4 is charged. In addition, in the case of FIG. 9(d) (preceding via) 0.0), when the sign determination result is "1"), the CMOS switch 22-4 is closed and the capacitor 28-4 is charged. When the sign determination result is "0" (e), the CMOS switch 27-5 is closed and the capacitor 28-5 is charged.

By the way, the demodulated output voltages (A), (B), (C), NI) at the time 2.5T of Ai-Gutan shown in FIG.
Since (e) moves in parallel with the center voltage C, the voltages that follow this changing center voltage C are the above (a), (b),
(c).

It can be obtained by adding the voltages of ) and (e). That is, the voltages (a) to (e) at time 2.5T held in the capacitors 28-1 to 28-5, respectively, are applied to the adder circuit 30 via operational amplifiers 29-1 to 29-5. Adder circuit 30 and capacitor 31
forms a low frequency door filter, and at the terminal of the capacitor 31 a reference voltage that follows the center voltage C of the eye droplet shown in FIG. 6 is generated.

Here, the adder circuit 30 is composed of five resistors having equal resistance values, and these resistance values are as described in (a), ←)
Weighting may be applied according to voltage values such as . however,
In order to maintain symmetry between the ■ side and the e side, the resistance connected to the voltage (A) and the resistance connected to (E) should be equal in value, and the resistance connected to the voltage (B) should be the same value. The resistances connected to the voltages shall also have the same value.

Further, in order for the voltage at the terminal of the capacitor 31 to closely follow the center voltage C of the eye drop shown in FIG. 6, the following two conditions are necessary.

((a) If the capacitance of capacitors 27-1 to 27-5 is Ca, and the capacitance of capacitor 3I is Cb, then Ca
It is necessary that <<Cb. This is capacitor 27-1~
This is to prevent the voltage of capacitor 31 from changing due to the charging current of capacitors 27-1 to 27-5.
An operational amplifier with a gain of 1 may be inserted between -5 and capacitor 3.

(→ T1 is the time constant determined by the modulator 2 of the transmitter shown in FIG. 2 and the DC cutoff circuit 11 of the receiver shown in FIG. If the time constant of the ν wave device is T2, it is necessary that TI>>T2.

In FIG. 1, operational amplifier 29-1.29-2.29
The output voltage of -4°29-5 and the voltage appearing on the capacitor 3) are input to the judgment voltage generation circuit 32. FIG. 8 shows an example of the determination voltage generation circuit 32, and the terminal 32-1
, ,? The output voltage of the operational amplifier 29-1.29-2.29-4.29-5 is applied to 2-2.32-4 and 32-5, respectively, and the voltage generated at the terminal of the capacitor 31 is applied to the terminal 32-3. A reference voltage is applied. Terminal 32-6~3
Judgment voltages La-Ld shown in FIGS. 7(a)-(d) are outputted to 2-9, respectively.

The resistance value of each resistor in FIG. 8 is the judgment voltage L3~
Ra = R, 1, Rb = Rc to maintain symmetry on the ■ side and e side.

Rabl = Rcdl + Rab2 = Rcd
2 + Rab3 = Rcd3. The judgment voltages L3 to Ld obtained in this way change in parallel with the voltage change of the center value C of I/G shown in FIG. Even if there are fluctuations, the analog comparator 34 can always make a correct sign determination.

(Effects of the Invention) As explained in detail above, according to the present invention, even if the center value of the demodulated output eye-gap changes due to DC cutoff, a reference voltage that follows the center value can be obtained. , a correct sign determination result can always be obtained for the demodulated output, and efficient detection can be performed without using a complicated modulation circuit, DC transmission line, or complicated demodulation circuit.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of a transmitter, Fig. 3 is a block diagram of a conventional receiver, Fig. 4 is a waveform of input data and demodulated output, and Fig. 5 is a block diagram of a conventional receiver. 6 shows a demodulated output A-Z-Tan, FIG. 7 shows an A-Z-Tan which is a four-classification of FIG. 6, and FIG. 8 shows a judgment voltage generation circuit. 23...Input terminal, 24...CMOS switch, 2
5.31... Capacitor, 26... Operational amplifier, 2
7... CMOS switch group, 28... Capacitor group, 29... Operational amplifier group, 30... Adder circuit, 32
... Judgment voltage generation circuit, 33 ... Changeover switch, 3
4... Analog comparator, 35... Code string discrimination circuit,
36... Output terminal, 37... Timing circuit. Patent Applicant Oki Electric Industry Co., Ltd. Transmitter configuration diagram Conventional receiver configuration ° Figure 3 λn type output wave juice 5 Figure 4 skin do]

Claims (1)

[Claims] In a code determination reference voltage generation method that generates a reference voltage for a determination voltage used for determining the sign of a demodulated signal obtained by demodulating a signal modulated by a digital signal, the sign of the demodulated signal is determined at the sign determination timing. selects a corresponding voltage holding means, and holds, by the selected voltage holding means, a voltage that is the difference between the demodulated signal voltage stored in advance and a reference voltage at a specific timing prior to the sign determination timing, and the selected voltage A sign determination reference voltage characterized in that the voltages held by the holding means and the remaining voltage holding means are added together and passed through a low-pass filter, and the output voltage of the low-pass filter is used as the reference voltage. Generation method.