JPH06244772A - Method and device for clock synchronization - Google Patents

Abstract

PURPOSE:To prevent the deviation of transmission/reception timings generated when a reception electric field level declines by comparing a detected electric field level with a threshold value and outputting a compared result as the changeover signals of clock signals. CONSTITUTION:A reception part 1 smooths an intermediate frequency IF to be defined as the level information of a reception electric field and outputs it to a level comparator circuit 3. The circuit 3 compares the electric field level information outputted from the reception part 1 with the preset threshold value and sends clock changeover signals to a clock synchronization circuit 2 so as to respectively output synchronous clock signals when an electric field level value is higher and free-running clock signals when the threshold value 15 higher. A timing control circuit 5 inputs the clock signals outputted from the circuit 2 and outputs the transmission/reception timing control signals of data to the reception part 1 and a multiplexing/demultiplexing circuit 4. By this constitution, even when the electric field level of reception radio waves declines and the phase of the clock signals is disturbed, the deviation of the timings of the operation of the circuit 4 can be surely prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronizer, and more particularly to a clock synchronizer used in a digital car telephone system.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional clock synchronizer for a digital car telephone system includes a receiving section 1, a clock synchronizing circuit 2, a time division multiple access (TDMA) demultiplexing circuit 4, and timing control. And a circuit 5.

The receiving section 1 receives a radio wave as shown in FIG. 3A, reproduces time-division multiplexed data, and synchronously extracts a clock signal B. The clock synchronization circuit 2 uses the clock signal B extracted by the receiving unit 1 as a synchronization clock signal.
It outputs either the regenerated synchronous clock signal C whose phase is synchronized with the clock signal or the free-running clock signal generated by synchronizing the phase with the clock signal output from the receiver 1. The timing control circuit 5 counts the number of synchronous clock signals and outputs a timing control signal according to the counted number to control transmission / reception timing. Demultiplexing circuit 4
Outputs demultiplexed time-division-multiplexed data in the received radio wave using a synchronous clock signal and a timing signal.

That is, the analog received radio wave signal converted to the intermediate frequency 1F is received by the receiving unit 1 as shown in FIG.
The signal is delayed and detected by the differential detection demodulator 11 and reproduced and output as the received data of the digital signal, and the phase data is sent to the clock extraction circuit 12 of the receiver 1. In the clock extraction circuit 12, the symbol synchronization clock (for example, 21 kbit / s) that is synchronized with the reception clock signal according to the sent phase data is used as the reception synchronization clock signal, and the output signal of the oscillation frequency dividing circuit 13 outputs the symbol synchronization clock. A bit synchronous clock (42 kbit / s) with a doubled frequency is generated as a free-running synchronous clock signal. (Note that the bit synchronization clock can be generated at a frequency extremely close to twice the clock frequency of the symbol synchronization clock by the free-running clock without depending on the phase data of the demodulation unit.) These two synchronizations As shown in the upper part of FIG. 5, when the time slots of the transmission / reception period are repeatedly arranged in the order of reception, idle, and transmission as shown in the upper part of FIG.
As shown in the lower part of the figure, the synchronization clock signal extracted from the received radio wave is output even during the period when the reception level is equal to or lower than the threshold value during the reception period, and the oscillation frequency divider circuit 13 outputs during the idle and transmission periods. A free-running clock signal that is generated and kept in synchronization with the phase of the reception clock during the reception period is output.

The demultiplexing circuit 4 controls the data transmission / reception timing by the synchronous clock signal output from the clock synchronization circuit 2 and the timing signal output from the timing control circuit 5, and is reproduced by the receiving section 1. Data in either the reception section or the transmission section is separated from the data signal and output.

As shown in FIG. 6, this operation is carried out at a data transmission rate of 42 kbit / s, 840 bits, and 280 bits of received data and transmission data in one frame of 20 ms.
An example will be described in which the idle sections are arranged every 6.6 ms. FIG. 7 shows an example of a circuit for generating a window for separating the transmission and reception sections. The counter 51, the decoder 52 and the two AND circuits 53, 54 are shown in FIG.
Consists of. The counter 51 inputs a continuous clock synchronized with the rising edge of the transmission data, and uses the boundary between the reception section and the idle section of the data string as the reference point 0 for counting, and counts the clock number up to 839 bit by bit while the decoder 52 decodes the value. Output to. The decoder 52 receives the count value between 560 and 839 for the reception section,
Further, for the transmission section, during the period from 238 to 518, the logical value 1 for instructing the opening of the gate is continuously output to either of the two AND circuits 53 and 54. Each AND circuit inputs the output of the decoder 52 and the continuous synchronous clock signal and outputs a logical product thereof, thereby outputting a window for only one of the reception section and the transmission section.

[0007]

However, since the conventional clock synchronization device controls the timing of the transmission / reception separation window by counting the number of clocks output from the clock synchronization circuit, as described above. As shown in section aa ′ in FIGS. 3 and 5, when the phase of the reproduced clock signal is disturbed due to a decrease in the electric field level in the reception section, the transmission / reception timing is shifted or the reception data is lost. There was a drawback.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a clock synchronizer capable of preventing a transmission / reception timing shift which occurs when a reception electric field level is lowered.

[0009]

A clock synchronization device of the present invention is a means for demodulating a received radio wave to reproduce a received data signal, a means for extracting a clock signal from a variation of the amplitude of the received radio wave, and a reception of the received radio wave. A receiver having means for detecting the electric field level, means for correcting the phase of the clock signal extracted by the receiver, means for generating a free-running clock signal synchronized with the extracted clock signal, and phase corrected A clock synchronization circuit having means for switching between the received clock signal and the free-running clock signal for output, means for comparing the detected electric field level with a preset threshold value, and output by the comparison result A level comparison circuit having means for instructing the clock synchronization circuit to switch the clock signal to be used, and the synchronization clock output from the clock synchronization circuit. The click signal, T to separate the time-division data from the received data signal reproduced by the receiver
It has a DMA demultiplexing circuit and a timing control circuit that counts the number of clocks output from the clock synchronization circuit and controls transmission / reception timing.

The level comparison circuit outputs a corrected reception reproduction clock synchronization signal when the reception electric field level exceeds a set threshold value, and when the electric field level is below the threshold value, the free-running clock is used. Each is preferably controlled so as to output a signal.

[0011]

When the reception clock electric field level is lower than the predetermined threshold value, the synchronization clock signal for separating the received radio wave data is the same as the synchronization clock signal generated from the free-running clock signal. If the threshold value is exceeded, the synchronous clock signal regenerated from the received radio wave is switched.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In this embodiment, as shown in FIG. 1, in addition to a receiver 1 having the same function as the conventional example, a clock synchronization circuit 2, a timing control circuit 5, and a demultiplexing circuit 4, a receiver 1 is provided. A level comparison circuit 3 for detecting the electric field level of the received radio wave is additionally connected between the clock synchronization circuit 2 and the clock synchronization circuit 2.

The receiving unit 1 extracts the data signal and the clock signal from the signal of the intermediate frequency IF obtained by converting the received radio wave, and smoothes the IF to obtain the level information of the received electric field, which is output to the level comparison circuit 3. To do. Level comparison circuit 3
Compares the electric field level information output from the receiving unit 1 with a preset threshold value, and when the value of the electric field level is higher, the synchronous clock signal is generated. A clock switching signal is sent to the clock synchronization circuit 2 so as to output each clock signal. The timing control circuit 5 inputs the clock signal output from the clock synchronization circuit 2 and outputs a data transmission / reception timing control signal to the receiving unit 1 and the demultiplexing circuit 4.

Therefore, when the received electric field level changes in the receiving section as shown in the middle section of FIG. 5, the clock signal output from the clock synchronization circuit 2 in the receiving section has the electric field level as shown in the lower section of FIG. Is switched to either a synchronous clock signal that is synchronously extracted from the fluctuation of the radio wave or a free-running clock signal that maintains the synchronous state according to the level of
The demultiplexing circuit 4 receives a fixed periodic clock signal and a timing signal irrelevant to the reception electric field level, and separates the transmission section and the reception section from the data signal converted from the reception radio wave without error.

[0015]

As described above, according to the present invention, the synchronizing clock signal supplied from the clock synchronizing circuit to the demultiplexing circuit is reproduced by the level comparing circuit from the free-running clock and the received radio wave according to the received electric field level. Since the clock can be switched to any of the clocks, even if the electric field level of the received radio wave of the digital car telephone device is lowered and the phase of the clock signal is disturbed, it is possible to surely prevent the timing deviation of the operation of the demultiplexing circuit. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional clock synchronizer.

FIG. 3 is a timing diagram showing a relationship between a received electric field and a recovered clock.

FIG. 4 is a block diagram of a clock recovery circuit of the receiver 1.

FIG. 5 is an example of a time slot.

FIG. 6 is a timing diagram of a transmission / reception gate.

FIG. 7 is a circuit diagram of an example of a timing control circuit 5.

[Explanation of symbols]

 1 receiver 2 clock synchronization circuit 3 level comparison circuit 4 demultiplexing circuit 5 timing control circuit 11 delay detection demodulation unit 12 clock extraction circuit 13 oscillation frequency divider circuit 51 counter 52 decoder 53, 54 AND circuit

Claims (3)

[Claims] 1. A radio wave of a time division multiple access system is received, a clock signal is synchronously extracted from a variation of the amplitude of the radio wave, an electric field level of the radio wave is detected, and the value is compared with a predetermined threshold value. When the detected value of the electric field level exceeds the threshold value, the synchronously extracted clock signal is output as a first synchronous clock signal and a free-running clock synchronized with the synchronously extracted clock signal is output. If a signal is generated and the detected value of the electric field level is less than or equal to the threshold value,
The self-running clock signal is held in a synchronized state and output as a second synchronized clock signal, and the clock of the outputted synchronized clock signal of either the first or the second is counted to generate a timing control signal. And a clock synchronization method for separating transmission / reception data of a time division multiplex connection method by the timing control signal. 2. A means for receiving a radio wave of a time division multiple access system, a means for detecting an electric field level of the radio wave, a means for demodulating the radio wave to reproduce a received data signal, and a clock based on a variation of the amplitude of the radio wave. Level comparison having a receiving unit having a signal extracting unit, a unit for comparing the detected electric field level with a preset threshold value, and a unit for outputting a clock signal switching instruction signal according to the comparison result. A circuit, means for correcting the phase of the clock signal extracted by the receiving unit, means for generating a free-running clock signal synchronized with the extracted clock signal, and the switching instruction signal for correcting the phase A clock synchronization circuit having means for outputting either a reception clock signal or a free-running clock signal as a synchronization clock signal; A timing control circuit that counts the number of synchronous clock signals output from the clock synchronization circuit and outputs a transmission / reception timing control signal, and the synchronous clock signal and the timing control signal,
And a demultiplexing circuit of a time division multiplex connection system for separating time division data from a received data signal reproduced by the receiving unit. 3. The level comparing circuit, when the detected electric field level exceeds a set threshold value, outputs the synchronous clock signal output from the clock synchronous circuit to the synchronously corrected reception clock signal side and the electric field level. 3. The clock synchronizer according to claim 2, wherein when the value is less than a threshold value, an instruction signal for switching to the free-running clock signal side is output.