JP3239997B2 - Automatic frequency control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic frequency control circuit which is applied to, for example, an oscillation circuit for generating a reference signal for transmission and reception in a wireless communication system and keeps the output frequency of the oscillation circuit constant.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing an example of a digital radio communication system using an automatic frequency control circuit. The system illustrated in FIG. 6 is a VSAT system, in which a master station 1 as a hub station transmits a time division multiplexed signal to each slave station (micro satellite communication earth station) via a radio line 20. However, FIG. 6 shows only one slave station 2.

The slave station 2 reproduces the clock frequency of the digital signal from the carrier signal from the master station 1, for example, and generates a highly stable frequency signal based on the reproduced clock signal. The generated frequency signal is used for carrier generation for transmission.

In the receiver 3 of the slave station 2 shown in FIG. 6, a mixer 32 multiplies a received signal by a local oscillation frequency signal from a local oscillator 31 and outputs a baseband signal. The baseband signal is input to a demodulation circuit 33 and a clock recovery circuit 34. The clock recovery circuit 34
A timing signal component is extracted from the baseband signal, and a clock signal is reproduced by a circuit for reproducing the reference clock signal of the master station 1. The reproduced clock signal is supplied to the demodulation circuit 3
3. Input to the frame conversion circuit 35 and the transmitter 4.

[0005] The demodulation circuit 33 samples the baseband signal with the reproduced clock signal to obtain a demodulated signal, and outputs the demodulated signal to the frame conversion circuit 35. The frame conversion circuit 35 separates the received data for the slave station 2 using the reproduced clock signal. The received data is output via the control circuit 5.

[0006] In the transmitter 4 of the slave station 2, the transmission data input through the control circuit 5 is transmitted to the frame modulation circuit 43.
Is converted into a frame format for wireless communication. The signal converted into the frame format is supplied to the modulation circuit 44. The modulation circuit 44 modulates a carrier reference signal input as a carrier from the voltage controlled oscillator 42 with a signal from the frame modulation circuit 43 to generate a modulated wave in a transmission frequency band. Then, the output modulated wave from the modulation circuit 44 is transmitted to the radio line 20 as a burst signal of the time division multiple access communication.

The frequency of the carrier reference signal from the voltage controlled oscillator 42 is controlled by an automatic frequency control circuit 41. That is, the automatic frequency control circuit 41 inputs the reproduced clock signal from the receiver 3 and
Input a clock synchronization signal. The automatic frequency control circuit 41 knows the synchronization of the reproduced clock by the clock synchronization signal and starts the frequency control. Then, when the frequency error between the frequency of the carrier reference signal output from the voltage controlled oscillator 42 and the reproduced clock signal becomes equal to or less than a certain value, the frequency synchronization signal is output to the control circuit 5. When the frequency synchronizing signal is input, the control circuit 5 determines that transmission is permitted, passes the input transmission data, and supplies it to the frame conversion circuit 43.

Next, a configuration example and operation of the conventional automatic frequency control circuit 41 will be described with reference to the block diagram of FIG. In the automatic frequency control circuit 41 shown in FIG. 7, the reference time generation circuit 11 divides the frequency of the reproduced clock signal to generate a reference time signal indicating a reference time of several seconds. The reference time signal is input to the frequency error detection circuit 100.

The frequency error detection circuit 100 measures the error of the oscillation frequency of the voltage controlled oscillator 42 with respect to the frequency of a carrier reference signal (hereinafter referred to as a reference signal). And
The frequency error signal is output to the gain adjustment circuit 12. After the frequency error signal is gain-adjusted by the gain adjustment circuit 12, the frequency error signal is input to an integration circuit 13 serving as a filter. In this example, the integration circuit 13 includes a delay circuit 16, an adder 15 that adds the input signal and the delay signal and inputs the result to the delay circuit 16.
It is composed of The output of the integrating circuit 13 is converted to an analog signal by the DA converter 14 and
Are supplied as control signals.

Here, the frequency error detection circuit 100 counts the period of the oscillation signal of the voltage controlled oscillator 42 during the reference time. Then, a difference from the number of periods of the reference signal at the reference time is output as a frequency error.

For example, assume that the reference signal is 10 MHz and the reference time is 1 second. Then, the frequency error detection circuit 100
Can measure the oscillation frequency of the voltage controlled oscillator 42 with an accuracy of 1 Hz. Therefore, the oscillation frequency of the voltage controlled oscillator 42 is synchronized with the reproduced clock signal with an error of approximately 1 Hz.

However, in order to count a 10 MHz signal with an accuracy of 1 Hz, a large counter capable of counting up to 10 * 7 is required. In this specification, “*” is used as an index. When a binary counter is used, a counter having a width of 24 bits (2 * 24 ≧ 10 * 7) is required. Further, since 10 * 7 is not a power of 2, the counter output is set to "00" when the frequency error is 0 Hz.
To make the counter output “000001h” when the frequency error is 0000h ”and the frequency error is 1 Hz, the counter initial value must be corrected or the counter output must be corrected, where h is a hexadecimal number. Is shown.

For example, if 3 stages of 8-bit count are connected, 2 * 24 can be counted, but the counter output after 10 * 7 count does not become "000000h". When the frequency error is 0 Hz, the counter output is set to "000000".
h ”, when the frequency error is 1 Hz, the counter output is“
If the frequency error is 0 Hz, the input value of the integrating circuit 13 is “000000h”, and the input value of the integrating circuit 13 is 1 when the frequency error is 1 Hz.
00001h ", which is convenient.

[0014]

As described above, when the automatic frequency control circuit is configured to detect a frequency error using a counter, the number of stages of the counter increases, and as a result, the device size increases. There is a problem that the device cost increases. In the example above,
To increase the frequency accuracy to 0.5 Hz, 0, 25 Hz,..., The reference times need to be extended to 2 seconds, 4 seconds,. Along with that, the number of stages of the counter,
25 bits, 26 bits,... That is, the number of stages of the counter is further increased.

An object of the present invention is to provide an automatic frequency control circuit capable of solving the above-mentioned problems and realizing a counter for detecting a frequency error with a small number of stages.

[0016]

An automatic frequency control circuit according to the present invention comprises a frequency error detecting means for counting the period of an oscillation signal of an oscillator within a predetermined period and detecting an error between the frequency of the oscillation signal and a reference frequency. Control signal generation means for generating a control signal for bringing the oscillation frequency of the oscillator closer to the reference frequency based on the frequency error signal output from the frequency error detection means and providing the control signal to the oscillator, wherein the frequency error detection means There is room for the number of digits that can measure the number of periods according to the predetermined frequency width that the oscillation frequency can take
It is configured to include a binary counter having a number of digits .

[0017] Since the counter is Ru binary counter der,
For example, if the predetermined period is 1 second, the center frequency of the oscillator is 10 MHz, and the accuracy is ± 50 Hz, the minimum number of digits is 7 digits (7 bits) capable of counting the number of periods according to the range of −64 Hz to +63 Hz. ).

The automatic frequency control circuit, since it contains a counter initial value circuit count value gives an initial value of the counter to be zero when there is no frequency error, configuration for generating the control signal of the control signal generating means Is simplified.

The binary counter has a sufficient number of digits that can measure the number of periods according to a predetermined frequency width that the oscillation frequency of the oscillator can take. For example, if the predetermined period is 1 second, the center frequency of the oscillator is 10 MHz, and the accuracy is ± 50 Hz, -128 Hz to +127 Hz
A 9-digit (9-bit) counter capable of counting the number of periods in accordance with the range is used. If a margin is provided for the number of digits (bit width), it is possible to avoid a situation in which the counter control frequency is shifted and the error control direction proceeds in the opposite direction.

The automatic frequency control circuit, the output bit width of the binary counter, since it contains the overflow processing circuit for compressing the range not exceeding the bit width that can measure the number of cycles corresponding to a predetermined frequency width, a subsequent stage of the control signal The bit width of the data input to the generator is not increased, and the configuration of the control signal generator is prevented from becoming complicated.

The overflow processing circuit outputs the output value of the counter as it is, for example, if the output value of the counter is a value within a range that can be represented by a bit width capable of measuring the number of cycles corresponding to a predetermined frequency width, If the output value of the counter exceeds the range that can be represented by a bit width capable of measuring the number of cycles corresponding to the predetermined frequency width, the output value of the counter is set to a bit width capable of measuring the number of cycles corresponding to the predetermined frequency width Is converted to the maximum value and output.

When the output value of the counter is converted into a maximum value based on a bit width capable of measuring the number of cycles corresponding to a predetermined frequency width, the overflow processing circuit outputs information indicating that fact. Is also good. In such a configuration, the information can be used to adjust the gain so that the control signal generating means can follow up quickly, or to detect abnormal oscillation of the oscillator.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of an automatic frequency control circuit according to the present invention. In the automatic frequency control circuit 40 shown in FIG. 1, the reference time generation circuit 11 divides the reproduction clock signal a to generate a reference time signal b indicating a reference time of several seconds. The reference time signal b is input to the frequency error detection circuit 10. The frequency error detection circuit 10 receives the oscillation signal c of the voltage controlled oscillator 42 and measures an error of the oscillation frequency with respect to the reference signal frequency. Then, the frequency error signal d is output to the gain adjustment circuit 12.

After the frequency error signal d is gain-adjusted by the gain adjustment circuit 12, the signal is input to an integration circuit 13 serving as a filter. Note that, in this example, the integrating circuit 13 includes the delay circuit 1
6 and an adder 15 that adds the input signal and the delay signal and inputs the result to the delay circuit 16. Integrating circuit 1
The output of No. 3 is converted into an analog signal by the DA converter 14 and supplied to the voltage controlled oscillator 42 as a control signal.

Each block other than the frequency error detection circuit 10 shown in FIG. 1 is the same as each block shown in FIG. However, the configuration of the frequency error detection circuit 10 is as follows.
This is different from the configuration of the conventional frequency error detection circuit 100. Note that the automatic frequency control circuit 40 is applicable to, for example, the digital wireless communication system shown in FIG.

FIG. 2 is a block diagram showing an example of the configuration of the frequency error detection circuit 10. In the configuration shown in FIG. 2, the frequency error counter 101 inputs the reference time signal b to the load terminal, and inputs the oscillation signal c of the voltage controlled oscillator 42 to the clock terminal. When the reference time signal b is input to the load terminal, the frequency error counter 101 is loaded with the initial value set in the counter initial value circuit 103.
Then, the oscillation signal c input to the clock terminal is counted up.

In the example shown in FIG. 2, the frequency error counter 101 has an m-bit configuration and outputs an m-bit count value to the overflow processing circuit 102. The overflow processing circuit 102 compresses the m-bit count value into n bits (m> n) and outputs the compressed value to the error latch circuit 104. The error latch circuit 104 is implemented by an n-bit flip-flop or a latch circuit, latches the output of the error latch circuit 104 with the reference time signal b, and outputs it as a frequency error signal d.

Next, the operation will be described. First, a configuration method of the frequency error counter 101 will be described. Here, a case where the reference frequency is 10 MHz, the reference time is 1 second, and the frequency error is measured with an accuracy of 1 Hz is taken as an example. Further, it is assumed that the voltage-controlled oscillator 42 has an oscillation range deviation of ± 50 Hz when oscillating at 10 MHz.

Then, when the cycle of the oscillation signal of the voltage controlled oscillator 42 is counted for one second, the count value is 9, 9
99,950 bits to 10,000,050 bits (9,999,950 Hz to 10,000,050 Hz
). 100 between minimum and maximum
The frequency error counter 101 has 10 bits.
If it can count up to 0 bits, the frequency error can be measured.

For example, if the count value is 0, there is no frequency error; if it is 50 or less, the oscillation frequency of the voltage controlled oscillator 42 is higher than 10 MHz; if it is 51 or more, the oscillation frequency of the voltage controlled oscillator 42 is less than 10 MHz. It can be determined that it is low. Then, the count value of the frequency error counter 101 is input to the integration circuit 13 as a frequency error signal d,
If the output of the integrating circuit 134 is given as a control voltage to the voltage controlled oscillator 42, the frequency error can be eliminated.

A binary counter capable of counting 100 bits can be realized by a 7-bit counter. 2 * 7 =
This is because 128> 100. If two's complement is used in the numerical expression, for example, “00000000b” is 0 Hz, “00
“00001b” is +1 Hz, and “0111111b” is +
63 Hz, "1111111b" is -1 Hz, "100
0000b "represents -64 Hz, and -64H
The range from z to +63 Hz can be expressed in 1 Hz steps. Note that b indicates a binary number.

From the above, when a voltage controlled oscillator 42 having a deviation of ± 50 Hz is used,
The frequency error counter 101 can be realized by a 7-bit binary counter. If the oscillation frequency of the voltage controlled oscillator 42 is 10 MHz ± 50 Hz, 10 * 7 =
Since it is 2 * 7 * 5 * 7, a frequency error appears in the counter output after the 5 * 7 round counter has turned.

However, the oscillation frequency error of the voltage controlled oscillator 42 may exceed ± 50 Hz due to circuit adjustment and oscillator accuracy. A particular problem arises when the oscillation frequency error exceeds the range of -64 Hz to +63 Hz. In this case, when “00000000b” corresponds to 0 Hz, the number of times of counter rotation is shifted, for example, +
The shift of 65 Hz is determined to be -63 Hz.

Therefore, in the present embodiment, with a margin, a range four times as large as -64 Hz to +63 Hz, that is, a range from -256 Hz to +255 Hz can be counted.
The frequency error counter 101 is configured by a bit counter.

Since 10 MHz (corresponding to 10 * 7 count) is not divisible by 2 * 9, the count value is "000000".
In order to make 000b "correspond to 0 Hz, it is necessary to give an offset to the initial value of the counter. 10 * 7 = 2 * 7 * 5 * 7 = 2 * 9 * 5 * 7/2 * 2 =
2 * 9 * (19532-3 / 4) = 2 * 9 * 19532.
From -2 * 7 * 3, if an initial value of 2 * 7 * 3 is given to the counter, a frequency error appears in the count value after the count reaches 19532 rounds.

Therefore, in this embodiment, 2 * 7 × 3
Is given to the frequency error counter 101 as an initial value. That is, the counter initial value circuit 103 stores “1100000”
00 ”is set.

When the reference time signal b is input to the frequency error counter 101 as a load signal in the above-described configuration, the frequency error counter 101 sets the initial value set in the counter initial value circuit 103 as " 110,000
000 "is loaded, and the counting of the oscillation signal c of the voltage controlled oscillator 42 is started. Note that the initial value" 110000 "
The count value immediately before 000 ″ is loaded, that is, the frequency error during the previous measurement is latched by the error latch circuit 104 and output to the gain adjustment circuit 12 as a frequency error signal d.

The gain adjustment circuit 12 adjusts the gain so as to give a large gain at the initial stage of the frequency control and to give a small gain after the frequency error becomes small. The frequency error signal d whose gain has been adjusted by the gain adjustment circuit 12 is
After being integrated by an integration circuit 13 as a filter and D / A converted by a D / A converter 14, the voltage is supplied to a voltage controlled oscillator 42 as a control voltage. The voltage controlled oscillator 42 controls the output frequency so that the frequency error becomes zero. Therefore, the oscillation frequency of the voltage controlled oscillator 42 approaches the reference frequency.

As described above, in this embodiment, the frequency error counter 101 is constituted by the binary counter having the minimum bit width sufficient to count the deviation of the voltage controlled oscillator 42. The counter 101 is smaller than the conventional counter. Also,
Since the initial value set in the counter initial value circuit 103 is loaded into the frequency error counter 101 so that the error 0 Hz corresponds to the count value 0, the configuration of the circuit at the subsequent stage, in particular, the integration circuit 13 does not have to be complicated. .

Further, since the bit width of the frequency error counter 101 has a margin with respect to a minimum bit width sufficient to count the deviation of the voltage controlled oscillator 42, the number of times of the counter rotation is shifted. Thus, a situation in which the error control direction proceeds in the reverse direction is avoided.

In the above example, the frequency error counter 10
Although the bit width of 1 is expanded from 7 bits to 9 bits, the expansion undesirably increases the circuit scale of the gain adjustment circuit 12 and the integration circuit 13. Therefore, in this embodiment, as shown in FIG. 2, an overflow processing circuit 102 is provided between the frequency error counter 101 and the error latch circuit 104.

The overflow processing circuit 102 counts the m-bit count value output from the frequency error counter 101 by n
Compress to bits. That is, when the frequency error represented by m bits exceeds the range that can be represented by n bits, the frequency error represented by m bits is converted into the maximum value (in absolute value) that can be represented by n bits. Convert to In the above example, m = 9 and n = 7.

Whether or not the frequency error represented by m bits exceeds the range that can be represented by n bits can be determined by the upper bits of m bits. For example, as can be seen from the explanatory diagram of FIG. 3, when m = 9 and n = 7, the frequency error is −64.
When the frequency exceeds Hz to +63 Hz, the upper 3 bits of the 9 bits are not "000" or "111".
When the frequency exceeds +63 Hz, the most significant bit is 0, and when the frequency is less than -64 Hz, the most significant bit is 1.

Therefore, the overflow processing circuit 102
The upper (m−n + 1) bits of the m bits output from the frequency error counter 101 are monitored, and if the frequency error represented by m bits exceeds the range that can be represented by n bits, The expressed frequency error is converted into a maximum value (in absolute value) that can be expressed by n bits.

FIG. 4 is a circuit diagram showing an example of the configuration of the overflow processing circuit 102. In FIG. 4, an AND circuit 201 has a higher (m−n) of m bits.
+1) Monitor that the bit is "111". The OR circuit (NOR circuit) 202 monitors that the upper (mn + 1) bits of the m bits are “000”. The upper (mn + 1) bits are “111”
Or, if it is “000”, the output of the NOR circuit 203 goes low and the logic circuit 204 and the AND circuit 2
Since the output of step 05 becomes low level, the input first to n-th bits are output from the overflow processing circuit 102 as they are. Note that the logic circuit 204 outputs a high level when the upper input is 0 (low level) and the lower input is high.

The upper (mn) bits are "111".
Otherwise, the output of the NOR circuit 203 goes high. That is, when the frequency error represented by m bits exceeds the range that can be represented by n bits (for example, when the frequency error exceeds −64 Hz to +63 Hz),
The output of the NOR circuit 203 goes high. Therefore,
The gate by the logic circuit 204 and the gate by the AND circuit 205 are opened. However, the logic circuit 204 inverts and passes the value of the m-th bit.

Therefore, if the m-th bit, which is the most significant bit, is 1, the output of the AND circuit 205 goes high, and the gates of the NOR circuits 303, 501 to 503 are closed. That is, the NOR circuits 303, 501 to 503
All outputs go low. Since an inverting circuit (NOT circuit) 304 is provided on the line corresponding to the n-th bit, data in which only the n-th bit becomes 1 (for example, “100000 corresponding to −64 Hz”)
b ″) is output from the overflow processing circuit 102.

The upper (mn + 1) bits are "111"
If the m-th bit, which is the most significant bit, is not 0 and is not “000”, the output of the logic circuit 204 goes high and the gates of the NOR circuits 301, 401 to 403 are closed. That is, the NOR circuits 301, 401 to 40
3 are all low level (for example, “00000000”).
b "). At this time, the NOR circuits 303 and 5
Since the gates 01 to 503 are open, the outputs of the NOR circuits 301 and 401 to 403 all go high. A NOT circuit 304 is provided on the line corresponding to the n-th bit.
Is provided, the data in which only the n-th bit becomes 0 (for example, “0111 corresponding to +63 Hz”)
111b ″) is output from the overflow processing circuit 102.

Note that the NOT circuit 302 operates so as not to invert the logic of the n-th bit when the input n-bit is output from the overflow processing circuit 102 as it is.
It is provided corresponding to the T circuit 304.

After all, the overflow processing circuit 102
Bit (Expression range is -2 * (m-1) Hz to + (2 *
The (m-1) -1) Hz) frequency error is represented by n bits (representation range is -2 * (n-1) Hz to + (2 * (n-1)-
1) To hold down to Hz, -2 * (m-1) Hz ~
− (2 * (n−1) +1) Hz is − (2 * (n−1))
Hz, and + 2 * (n-1) Hz to + (2 * (m
-1) -1) Hz is replaced with + (2 * (n-1) +1) Hz.

As described above, in this embodiment, when the frequency error represented by m bits exceeds the range that can be represented by n bits, the overflow processing circuit 102
The frequency error represented by m bits is converted into a maximum value (in absolute value) that can be represented by n bits. Therefore, the circuit scale of the gain adjustment circuit 12 and the integration circuit 13 at the subsequent stage does not increase.

As an example, 10.000100 MHz ±
Assume that the voltage controlled oscillator 42 has an oscillation characteristic of 128 Hz. That is, the center frequency is shifted by 100 Hz, ± 1
10MHz ± 50Hz with 28Hz deviation
Is deviated from The automatic frequency control circuit 40
Is activated, the integration circuit 13 is cleared to zero.

When m = 9 and n = 7, the frequency error counter 101 starts counting from the initial value "110000000b", and when the frequency error is 0, 19532
The lap count turns and the count value becomes “000000000”
b ", but in this example, the frequency error is 100
Hz, it becomes “001100100b”. This value is limited to 7 bits by the overflow processing circuit 102 and becomes "0111111b" (+63 Hz).

The frequency error signal d of 7 bits becomes a control voltage for the voltage controlled oscillator 42 through the gain adjusting circuit 12, the integrating circuit 13 and the DA converter 14. It acts to reduce the oscillation frequency of the control oscillator 42 by 63 Hz. In addition, since the control direction works so as to reduce the frequency error, there is a logic inversion in the middle.

Accordingly, the voltage-controlled oscillator 42 has a value of 10,0
Oscillates at 00,037 Hz. When the next reference time arrives, the frequency error is determined to be +37 Hz (when the gain is 1). The integration circuit 13 calculates the current +3
The control is performed so that the oscillation frequency of the voltage controlled oscillator 42 is reduced by 100 Hz from the center frequency by adding 7 Hz. As described above, the oscillation frequency of the voltage controlled oscillator 42 approaches the true 10 MHz.

FIG. 5 is a block diagram showing another embodiment of the frequency error detection circuit 10 in the automatic frequency control circuit. In this case, the overflow processing circuit 102A
Compresses m-bit data into n-bit data,
Outputs a 1-bit overflow signal. Therefore, the error latch circuit 104A latches and outputs the (n + 1) -bit data.

As for the overflow signal, the output value of the frequency error counter 101 is -2 * (n-1) Hz to + (2 * (n
-1) -1) A signal indicating that the frequency range has been exceeded. This signal is output to the outside of the frequency error detection circuit 10. The overflow signal is used, for example, for the gain adjustment of the gain adjustment circuit 12, and when the overflow signal is output, the gain can be adjusted so as to speed up the pull-in. Further, when an overflow signal is output, it can be used for processing such as determining that abnormal oscillation has occurred in the voltage controlled oscillator 42 and initializing the automatic frequency control circuit 40.

In the above embodiment, the accuracy of the frequency error detection has been described as 1 Hz, but 1 / k [Hz]
To detect an error of (k: natural number), the reference time needs to be set to k seconds. In that case, the frequency error counter 1
Although it is necessary to increase the number of bits of 01 by k bits, the frequency error counter 101 may be constituted by a binary counter having a minimum bit width sufficient to count the deviation of the voltage controlled oscillator 42. This is the same as the embodiment. In this case, it is preferable to provide a margin in the bit width in consideration of an error according to the characteristics of the voltage controlled oscillator 42, as in the case of the above-described embodiment.

In the above-described embodiment, 10 MHz is exemplified as the reference frequency. However, the above-described embodiment can be applied to other frequencies if the counter initial value is changed accordingly. it can.

[0060]

As described above, according to the present invention, the automatic frequency control circuit is provided with a number of digits by which the frequency error detecting means can measure the number of periods corresponding to a predetermined frequency width that the oscillation frequency of the oscillator can take. However, since the counter is configured to include the counter having the minimum number of digits, the automatic frequency control circuit has an effect that the counter for detecting the frequency error can be realized with a small number of stages.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of an automatic frequency control circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a frequency error detection circuit.

FIG. 3 is an explanatory diagram showing a relationship between a 9-bit expression value and a 7-bit expression value by a 9-bit binary counter.

FIG. 4 is a circuit diagram illustrating a configuration example of an overflow processing circuit.

FIG. 5 is a circuit diagram showing another configuration example of the overflow processing circuit.

FIG. 6 is a block diagram illustrating an example of a digital wireless communication system using an automatic frequency control circuit.

FIG. 7 is a block diagram illustrating a configuration of a conventional automatic frequency control circuit.

[Explanation of symbols]

 Reference Signs List 10 frequency error detection circuit 11 reference time generation circuit 12 gain adjustment circuit 13 integrator circuit 14 DA converter 40 automatic frequency control circuit 42 voltage controlled oscillator 101 frequency error counter 102 overflow processing circuit 103 counter initial value circuit 104 error latch circuit

Claims (3)

(57) [Claims] An automatic frequency control circuit for adjusting an oscillation frequency of an oscillator having an accuracy within a predetermined frequency range with respect to a center frequency to a reference frequency, wherein the automatic frequency control circuit counts a period of the oscillation signal of the oscillator within a predetermined period. Frequency error detection means for detecting an error between the frequency of the oscillation signal and the reference frequency, and a control signal for causing the oscillation frequency of the oscillator to approach the reference frequency based on the frequency error signal output by the frequency error detection means. Control signal generating means for giving the signal to the oscillator, wherein the frequency error detecting means has a margin with respect to the number of digits capable of measuring the number of periods according to a predetermined frequency width that the oscillation frequency of the oscillator can take. Binary counter with number
And the count value becomes 0 when there is no frequency error.
Counter initial value for giving an initial value to the binary counter
Value circuit and the output bit width of the binary counter
Exceeds the bit width that can measure the number of periods according to the fixed frequency width
An overflow processing circuit for compressing the data into an impossible range . 2. An overflow processing circuit comprising :
A bit whose force value can measure the number of periods according to a predetermined frequency width.
Output value of the counter if the value is within the range that can be expressed by
Is output as it is, and the output value of the counter
Range that can be represented by a bit width that can measure the number of periods according to
If the frequency exceeds the threshold, the output value of the counter is
Converted to the maximum value of the measurable bit width
2. The automatic frequency control circuit according to claim 1 , wherein the automatic frequency control circuit outputs the data. 3. An overflow processing circuit according to claim 1 , wherein said overflow processing circuit outputs a counter.
A bit that can measure the number of periods according to a predetermined frequency width
When converted to the maximum value according to the
3. The automatic frequency control circuit according to claim 2 , wherein said automatic frequency control circuit also outputs a report .