JP2803721B2 - Bit rate free optical receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical receiver used for optical communication.

[0002]

2. Description of the Related Art FIG. 4 shows the configuration of a conventional optical receiver. In the optical receiver shown in FIG. 4, an incoming optical signal is converted into an electric signal by using a photodetector 51. A clock component is extracted from the electric signal using a timing extraction circuit 52 including a phase locked loop circuit, a tank circuit, and the like. A next-stage discrimination / reproduction circuit (not shown) compares the electric signal with an appropriate threshold value at the time of rising (or falling) of the clock component, and outputs a signal of a level corresponding to the result. Identification playback is in progress. If the optical signal input to the optical receiver is a time-division multiplexed signal, the output of the identification and reproduction circuit is further input to the time-division demultiplexing circuit and restored to a plurality of transmitted digital signals.

[0003]

SUMMARY OF THE INVENTION In a conventional optical receiver,
Since the timing extraction circuit is tuned to only a single frequency, a receivable signal is limited in a transmission system in which signals of a plurality of transmission rates are mixed.

Also, in the conventional optical receiver, since the multiplicity of the time division multiplexer used is fixed, only signals having one type of time division multiplicity can be received, and the transmission speed standards are different. In a time division multiplex transmission system in which a plurality of digital signals are accommodated in one transmission system, it is impossible to cope with a case where different time division multiplex degrees are set for each transmission speed.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a time-division multiplexing transmission system in which a plurality of digital signals having different transmission speed standards are accommodated in one transmission system, each having a different time-division multiplexing ratio for each transmission speed. It is an object of the present invention to provide an optical receiver that can cope with the case where “1” is set.

[0006]

According to the present invention, a photodetector for converting an input optical signal modulated by a digital signal into an electric signal, and synchronizing with the digital signal from an output electric signal of the photodetector. A clock extraction circuit for extracting the extracted clock component, and comparing the output electric signal of the photodetector with a predetermined threshold value at a timing synchronized with the output clock of the clock extraction circuit, and different values depending on the magnitude. In the optical receiver comprising an identification reproduction circuit for outputting a signal, the timing extraction circuit is a phase locked loop circuit having a large capture range, and the output signal of the identification reproduction circuit is input and output as a plurality of time division separation signals. Adding a separation circuit, and controlling the degree of separation of the time-division separation circuit by an input signal to a voltage-controlled oscillator constituting the phase-locked loop circuit. Bitrate-free optical receiver, wherein is obtained.

Further, according to the present invention, the phase locked loop circuit includes a voltage controlled oscillator, a phase comparator, and a low-pass filter, and includes an input side of the phase comparator and the low-pass filter. Is connected to a level discriminating circuit having first and second comparators and an AND gate. The level discriminating circuit changes the level of the driving voltage applied to the voltage-controlled oscillator to the first and second levels. A bit rate-free optical receiver is obtained, characterized in that the transmission rate of the input optical signal is identified by detection by the second comparator.

Further, according to the present invention, the voltage-controlled oscillator sets the frequency variable range wide enough to cover all bit rates of a digital signal that may be input. A rate-free optical receiver is obtained.

Further, according to the present invention, the time division demultiplexing circuit has a shift register type configuration, and separates an output signal of the identification reproduction circuit into a multiplex number equal to a frequency division ratio of a variable frequency divider. A bit rate-free optical receiver is provided, wherein a frequency division ratio is controlled by the level identification circuit, and the multiplicity of the time division demultiplexing circuit can be automatically set according to the transmission rate / multiplex degree of the input optical signal. .

[0010]

According to the present invention, since a phase locked loop circuit having a large capture range is used as a timing extracting circuit, it is possible to cope with various transmission speeds. In addition, in order to control the degree of separation of the time division demultiplexing circuit by an input control signal to the voltage controlled oscillator constituting the phase locked loop circuit, in a transmission system in which the time division multiplexing is set to a different value for each transmission speed. The optimum degree of separation is automatically set according to the received signal.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram illustrating a configuration of an optical receiver according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating a frequency pull-in characteristic of the timing extraction circuit in FIG.

The optical signal arriving at the optical receiver is a signal obtained by intensity-modulating laser light with any of the following three types of binary digital signals A, B and C. The binary digital signal A (hereinafter, referred to as A signal) is a 2.29 Gb / s signal obtained by time-division multiplexing of 16 143 Mb / s signals, and the binary digital signal B (hereinafter, referred to as B signal) is 1. Time-division multiplexing of eight 270 Mb / s signals A 16-Gb / s signal, and a binary digital signal C (hereinafter, referred to as a C signal) is:
This is a 485 Gb / s signal.

The optical signal input from the outside to the optical receiver via the optical fiber is a PIN photo. The light is converted into an electric signal by a photodetector 1 composed of a diode. This electric signal is subjected to current / voltage conversion in the front end 2. The output of the front end 2 is amplified to a constant level by an automatic gain control function (AGC) amplifier 3. The output of the amplifier 3 is bifurcated into a first output and a second output, and the first output is input to a phase locked loop circuit (hereinafter, referred to as a PLL circuit) 4.
The PLL circuit 4 is a voltage controlled oscillator (hereinafter, referred to as VCO)
5, a phase comparator 6, and a low-pass filter (hereinafter referred to as LPF) 7. The frequency variable range of the VCO 5 is from 1.4 GHz to 2.4 GHz.

Regardless of whether the optical signal input to the optical receiver is any of the A signal, the B signal, and the C signal, the PLL
The timing can be extracted by the circuit 4. The output of the LPF 7 is input to the level identification circuit 8. Since the output level of the LPF 7 corresponds to the transmission speed of the input optical signal to the optical receiver, the transmission speed can be known by monitoring the level.

The level discriminating circuit 8 can be realized by a configuration as shown in FIG. In this circuit, the first and second comparators 4
In steps 1 and 42, it is checked whether the level of the input signal corresponds to the A signal, the B signal, or the C signal. In the first comparator 41, if it corresponds to the C signal, its output is at a low level (L), otherwise the output is at a high level (H).
On the other hand, the second comparator 42 outputs a high level (H) if the signal is an A signal, and outputs a low level (L) otherwise. In summary, the operation of the level identification circuit 8 is as shown in Table 1 below.

[0016]

[Table 1] The second output of the amplifier 3 is input to a data input terminal of an identification reproducing circuit 9 composed of a D flip-flop. A clock signal, which is the output of the PLL circuit 4, is input to the discriminating / reproducing circuit 9, and at the timing of this clock, it is discriminated whether the level of the second output of the amplifier 3 is high or low. The output of the identification and reproduction circuit 9 is input to the time division separation circuit 10. The time division separation circuit 10 has a shift register type configuration as shown in FIG. The degree of separation of the time division separation circuit 10 is controlled by the output of the level identification circuit 8 which is separately input. In order to control the degree of separation of the time division separation circuit 10, the count value of the ring counter is controlled by a decoder. The decoder operates based on the truth table shown in Table 2 below, based on the output of the level identification circuit 8 that is input.

[0017]

[Table 2] By applying the output shown in Table 2 to the ring counter, the count value of the ring counter becomes 1,
It changes to 8,16.

[0018]

According to the present invention, since a phase locked loop circuit having a large capture range is used as a timing extraction circuit, various transmission speeds can be handled.

Further, according to the present invention, since the degree of separation of the time division demultiplexing circuit is controlled by the input control signal to the voltage controlled oscillator constituting the phase locked loop circuit, the time division multiplicity differs for each transmission speed. In the transmission system set to the value, the optimum degree of separation is automatically set according to the received signal.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a bit rate free optical receiver according to the present invention.

FIG. 2 is a diagram illustrating a frequency pull-in characteristic of a timing extraction circuit.

FIG. 3 is a diagram showing a configuration of a level identification circuit.

FIG. 4 is a diagram showing a conventional optical receiver.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Photodetector 2 Front end 3 Amplifier 4 PLL circuit 5 VCO 6 Phase comparator 7 LPF 8 Level discrimination circuit 9 Discrimination reproduction circuit 10 Time division separation circuit 41, 42 Comparator

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04B 10/28 H04J 3/00 3/06 H04L 7/033

Claims (4)

(57) [Claims] 1. A photodetector for converting an input optical signal modulated by a digital signal into an electric signal, and clock extraction for extracting a clock component synchronized with the digital signal from an electric signal output from the photodetector. And a discrimination / regeneration circuit that compares an output electric signal of the photodetector with a predetermined threshold value at a timing synchronized with an output clock of the clock extraction circuit, and outputs a different value according to the magnitude of the threshold value. In the receiver, the timing extraction circuit is a phase-locked loop circuit having a large capture range, and a time-division separation circuit that receives an output signal of the identification and reproduction circuit as an input and outputs a plurality of time-division separation signals is added. Bit rate-free light, wherein the degree of separation of the time-division separation circuit is controlled by an input signal to a voltage-controlled oscillator constituting a circuit. Receiver. 2. The phase locked loop circuit includes a voltage controlled oscillator, a phase comparator, and a low-pass filter, and a second input terminal of the phase comparator and an output terminal of the low-pass filter. A first and second comparator and a level identification circuit having an AND gate are connected, and the level identification circuit includes:
2. The bit according to claim 1, wherein the transmission speed of the input optical signal is identified by detecting a level of a driving voltage applied to the voltage controlled oscillator by the first and second comparators. Rate-free optical receiver. 3. The bit rate according to claim 2, wherein the voltage-controlled oscillator sets a frequency variable range wide enough to cover all bit rates of a digital signal that may be input. Free light receiver. 4. The time-division demultiplexing circuit is of a shift register type, and separates an output signal of the discrimination / reproduction circuit into a multiplex number equal to a frequency-division ratio of a variable frequency divider. 4. The bit rate-free optical receiver according to claim 2, wherein a multiplicity of the time division demultiplexing circuit can be automatically set according to a transmission rate / multiplex degree of the input optical signal under the control of an identification circuit.