JPH09181687A - Burst digital optical receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To identify an optical signal without deterioration in a minimum input level by selecting an identification level for a received burst optical signal to have a logic '0' with a sufficient offset in the case of non-signal and selecting the 0 level in the middle of the signal level at the reception of the signal. SOLUTION: A received signal light is converted into a differential output signal by a photoelectric conversion element 1 and a preamplifier 2 and given to an automatic threshold control circuit 3. A peak hold signal 113 of a noninverting input signal 103 and that of an inverting input signal 103 are averaged binary in an average circuit 34 to be a noninverting identification signal 111, and the inverting input signal 103 and an output signal 109 of a selection circuit 39 are binary averaged in an average circuit 35, from which an inverting identification signal 110 is obtained. The signal 109 is an offset voltage of a reference voltage source 40 when no signal is received and a voltage selected from an output signal of the peak hold circuit 104 when the signal is received. The identification signals 110, 112 are given to an identification device 4, in which logical level I/O is identified and an output signal 112 is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital optical receiver, and more particularly to a PON (Passive Optical).
l Network) The present invention relates to an optical receiver for receiving burst data in an optical transmission system, an optical Ethernet communication system, or the like.

[0002]

2. Description of the Related Art As means for economically realizing an optical subscriber transmission system, a service to a plurality of subscribers has been devised by branching a transmission line extended from one station halfway. In a PON system, a signal from a subscriber to a station is transmitted by time division multiple access (TDMA: Time Division M).
Since it is multiplexed by multiple access, the subscriber signal received by the station is a burst signal in which the signal strength changes suddenly for each subscriber.

When digital binary modulation is used as the transmission code, the output signal of the receiver at the station is "1" corresponding to the mark portion, "0" corresponding to the space portion, and the non-signal portion between bursts. And "undefined". However, when there is no signal, it is desired to keep outputting a certain logic level "0" or "1" in order to simplify a synchronization circuit and a TDMA access control circuit connected to the subsequent stage of the receiver.

FIG. 4 and FIG. 5 show a conventional burst digital optical receiver described in Japanese Patent Application Laid-Open No. Hei 2-266630.

In FIG. 4, a received burst digital optical signal 501 is converted into an electric signal by a photoelectric conversion element 10 using a pin photodiode, and
The signal is amplified to a predetermined level by a differential output signal and enters a unipolar code / bipolar code conversion circuit 30, where it is converted into a bipolar signal. Are added by the adder 40, and then input to the discriminator 5 as a differential signal 503. The discriminator 50 outputs a data output signal 504 of logic 1 or 0 using the offset voltage as the discrimination level. The operation of the unipolar code / bipolar code conversion circuit 30 is reset for each received signal by the reset signal 502.

FIG. 4 shows a signal waveform in each part, and shows a state of the data input signal 501 when the pulse amplitude is a normal pulse amplitude and when the pulse amplitude is low. The reset signal 502 is input for each received signal. Unipolar code /
The output signal 503 of the bipolar code conversion circuit 30 is identified as a logical value 1 or ₀ at an identification level D0. The data output signal 504 output from the discriminator 50 has a slightly narrower pulse width due to the shift of the discrimination level D ₀ even when the data input signal has a normal amplitude, and further becomes narrower when the amplitude is low.

In order to keep outputting the logic level "0" without being affected by noise or the like when there is no signal, a certain offset is given at the input of the discriminator 50 and the offset is provided from the center of the input pulse amplitude. The position shifted by a certain value (FIG. 5)
Is performed determination of the logic level "1", "0" at the discrimination level D ₀₎ in the.

[0008]

When discriminating between logic "1" and logic "0" for an input signal pulse which has been digitally modulated, a receiving circuit such as an optical receiver using a pin photodiode is used. In a system in which the S / N (signal power to noise power ratio) is determined only by noise, the S / N ratio is maximized, and the pulse width of the discriminator output is set to a value equal to the clock cycle T ₀ to maximize the discrimination phase margin. Therefore, it is desirable to perform the identification at the center of the pulse amplitude.

However, in the conventional burst digital optical receiver, since the identification value is given a constant offset as described above, the identification is performed at a position higher than the center of the pulse amplitude. When the size is small, the influence of the offset becomes significant. That is,
As shown in FIG. 5, there are the following problems when the pulse amplitude of the input signal is small. (1) Identification is performed at a position shifted from the S / N maximum. (2) The output pulse width becomes narrower, and the discrimination phase margin sufficient to operate the bit synchronization circuit connected to the subsequent stage of the receiver cannot be obtained. The problem (2) can be reduced by setting the receiving system to a wide band. For example, in a continuous signal receiver having a clock frequency fc, the reception band is usually set to about 0.7 fc, but in a conventional burst mode optical receiver, the reception band is set to 1.0 fc to 1.5 f.
It is set to about c. However, the noise band of the receiving circuit is also increased by widening the band, so that the S / N ratio is deteriorated.

As described above, in the conventional burst digital optical receiver, due to the S / N deterioration and the reduction of the discrimination phase margin,
As compared with a continuous signal receiver whose discrimination level is always set at the center of the signal amplitude, the minimum light receiving level is 3 dB to 5 d
There is a problem of deterioration by about B.

[0011]

SUMMARY OF THE INVENTION A burst digital optical receiver according to the present invention comprises a photoelectric conversion element for converting a received burst digital optical signal into an electric signal, amplifying the electric signal to a predetermined level, and outputting a differential signal. And a preamplifier that outputs a first positive-phase signal and a first negative-phase signal, and a binary average value of a value of the first positive-phase signal and a value obtained by peak-holding the first negative-phase signal. The second positive-phase signal and the first
The average of the value of the negative-phase signal and the value of the peak voltage of the first positive-phase signal at the time of the signal and the value of the offset voltage set to a value higher than this value at the time of no signal were taken. An automatic threshold control circuit for outputting a second negative-phase signal having a negative-phase relationship with a second positive-phase signal; and a burst digital optical signal based on the second positive-phase signal and the second negative-phase signal. When there is no signal, the logical value 0 is determined. When the signal is a signal, the logical value is determined by the intermediate value of the amplitude value of the burst digital optical signal, and the logical value
And a discriminator that outputs 0.

Further, the automatic threshold value control circuit includes
A first peak hold circuit for holding the maximum value of the positive phase signal, a second peak hold circuit for holding the maximum value of the first negative phase signal, and a minimum value of the first positive phase signal. A bottom hold circuit, first and second reference voltage sources, and an output signal of the first peak hold circuit and an output signal of the first reference voltage source. A comparator that outputs a logical value H when the output signal voltage is higher than the output signal voltage of the first reference voltage source, and outputs a logical value H when the output signal voltage is lower than the output signal voltage, an output signal of the bottom hold circuit, and the second reference voltage source And an output signal of the first peak hold circuit and an output signal of the adder. When the comparator has the logical value H, the output of the first peak hold circuit is output. Addition when signal is L And an output signal of the first positive-phase signal and the output signal of the second peak hold circuit, and an average value of these signals is used as a second positive-phase signal for logic determination. Output signal first
And a second average value circuit which takes in the first negative phase signal and the output signal of the selection circuit and outputs an average value of these signals as a second negative phase signal for logic judgment. May be provided.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings.

First, in order to explain the principle of operation of the present invention, FIG. 3 shows the relationship between a data input signal and an identification value for identifying its logic in comparison with the conventional case.

Generally, in a burst digital optical receiver, since the signal level differs for each burst, a peak value of a signal to be received is held using a peak hold circuit, and an intermediate value thereof is used as an identification value of the received signal to define a logical value. Judgment is being performed. In this case, when there is no signal, the peak value of the received signal is the same as the “0” level of the received signal, so that the identification value of the received signal is equal to the logical “0” level. As a result, the identification becomes indefinite and “1” and “0” are output indefinitely.

Therefore, in the case of a conventional burst digital optical receiver, an offset is given to the identification value in advance as shown in FIG. 3B in order to output a logical "0" when there is no signal. However, at the time of signal input, the value obtained by adding the intermediate value of the signal amplitude to this offset becomes the identification value,
When the signal amplitude in the vicinity of the minimum light receiving level is small, as shown in the figure, the signal amplitude is higher (first half burst signal) or exceeds the signal amplitude (second half burst signal), resulting in deterioration of reception characteristics or reception. The result is not possible.

According to the present invention, as shown in FIG. 3 (a), when there is no signal, a conventional and sufficient offset is given by providing a sufficient offset, and when a signal is input, the signal is always output at the center of the signal amplitude. Is to be identified.

FIG. 1 is a block diagram showing the configuration of a burst digital optical receiver according to this embodiment. The data input signal 101 enters the photoelectric conversion element 10 and is converted into a current signal. The electric signal is amplified and converted into a differential output signal 103 by the preamplifier 2. The output of the preamplifier 2 is ATC (Automatic Threshold).
(Control automatic threshold control) circuit 3 and is converted into identification signals 110 and 111. This identification signal 1
10 and 111 are input to the discriminator 4 and output a logically discriminated data output signal 112.

The ATC circuit 3 which characterizes the present invention will be described below.
Will be described in detail. Output signal 10 of preamplifier 2
The positive-phase output of the differential signal No. 3 is input to an average value circuit 34, a peak hold circuit 31 and a bottom hold circuit 33 which hold the peak value and the bottom value of the signal, respectively. Further, the negative-phase output of the differential signal of the output signal 103 of the preamplifier 2 is input to an average value circuit 35 and a peak hold circuit 32 which holds the peak value of the signal.

The output signal 104 of the peak hold circuit 31
Is input to the comparator 36 and the selection circuit 39, respectively.
In the comparator 36, the signal is compared with the reference voltage 107 of the reference voltage source 38 for recognizing the reception of the signal, and this reference voltage 107
If it is smaller, it outputs logic "L", and if it is larger, it outputs logic "H". The output signal 105 of the bottom hold circuit 33 is input to the adder 37, and the reference voltage 106 of the reference voltage source 40 is added. As for the reference voltage 106, the data output signal 112 outputs "0" when there is no signal,
This is the offset given to the identification value. This adder 3
The seven outputs are input to the selection circuit 39.

The selection circuit 39 selects one of the two levels of the output signal 104 of the peak hold circuit 31 and the output signal of the adder 37, based on the output signal 108 of the comparator 36. Output signal 108 of comparator 36
Is "L", the output signal 1 of the selection circuit 39
The output signal of the adder 37 is selected as 09. on the other hand,
When the logic of the output signal 104 of the comparator 36 is “H”, the output signal 104 of the peak hold circuit 31 is selected.

The average value circuit 34 receives the output signal 113 of the peak hold circuit 32 and the in-phase output of the preamplifier 2 output signal 103, and averages the two values to obtain the ATC circuit 3
Is output as the positive-phase signal 111 of. The average value circuit 35 receives the output of the output signal 109 of the selection circuit 39 and the output of the negative phase of the preamplifier 2 output signal 103, and outputs the average value of the two values as the negative phase signal 110 of the ATC circuit 3.

The peak hold circuits 31, 32 and the bottom hold circuit 33 have their hold values reset by a reset signal between burst signals, and hold the maximum value or the minimum value of the next incoming burst signal. It goes into a standby state.

Next, the operation of the burst digital optical receiver shown in FIG. 1 will be described with reference to FIG. FIG. 2 shows FIG.
3 is a time chart showing the operation of each part signal in FIG.

As shown in this figure, the reference voltage 107 of the reference voltage source 38 is set to a value smaller than the signal amplitude at the minimum light receiving level. The reference voltage 106 of the reference voltage source 40 is set to a voltage sufficient to output “0” when there is no signal.

First, the operation when there is no signal will be described. In this case, the output signal 108 of the comparator 36 outputs a logic “L”, whereby the selection circuit 39 selects the voltage of the adder 37 as an output. The output of the adder 37 is obtained by adding the reference voltage 106 of the reference voltage source 40 to the output signal 105 of the bottom hold circuit 33. The average value of the output signal 109 of the selection circuit 39 and the negative phase output of the preamplifier 2 is obtained by the average value circuit 35 as a negative phase signal 110.

On the other hand, the normal phase signal 111 of the average value circuit 34
Is the positive phase output of the preamplifier 2 and the peak hold circuit 32.
From the output signal 113. When the signals 110 and 111 of the average value circuit outputs 34 and 35 are input to the discriminator 4, when there is no signal, the signal 111 which is the positive-phase output of the ATC circuit 3 is always the reverse-phase output of the ATC circuit 3. It is smaller than a certain signal 110. As a result, when there is no signal, the output data signal 112 of the discriminator 4 outputs logic "0".

Next, the operation at the time of signal input will be described. In this case, the output signal 108 of the comparator 36 outputs a logic “H”, so that the selection circuit 39 selects the voltage of the peak hold circuit 31 as the output signal 109. The average value of the output signal 109 of the selection circuit 39 and the negative phase output of the preamplifier 2 is obtained by the average value circuit 35.

On the other hand, the output signal 111 of the average value circuit 34
Is the positive phase output of the preamplifier 2 and the peak hold circuit 32.
Is obtained from the average of the output signals 113 of The output signals 111 and 110 of the obtained average value circuits 34 and 35 have the same amplitude, and have a differential waveform in which one peak value is equal to the other bottom value, and one bottom value is equal to the other peak value. When this differential waveform is input to the discriminator 4, as shown in the figure, the data output signal 11 without duty deterioration and S / N deterioration does not occur.
Get 2.

[0030]

As described above, the burst digital optical receiver according to the present invention has the following effects.

The output signal of the receiver outputs a stable logic "0" by giving an offset to the logic decision identification value when there is no signal, and always outputs the logic decision identification value at the center of the signal amplitude when a signal is input. Since the setting is made, the discrimination is performed under the conditions of the maximum S / N and the maximum discrimination phase margin, and as a result, the minimum input level does not deteriorate. That is, there is an effect that a stable "0" signal can be obtained when there is no signal without deterioration of the minimum input level.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an exemplary embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of FIG.

FIG. 3 is a characteristic diagram illustrating the operation principle of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional optical receiver.

FIG. 5 is a flowchart illustrating the operation of FIG. 1;

[Explanation of reference numerals] 1 photoelectric conversion element 2 purine amplifier 3 ATC circuit 4 discriminator 31, 32 peak hold circuit 33 bottom hold circuit 34, 35 average value circuit 36 comparator 37 adder 38, 40 reference voltage source 39 selection circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04L 25/03

Claims (2)

[Claims] An optical-electrical conversion element for converting a received burst digital optical signal into an electric signal, a first positive-phase signal having a differential output and an amplifying the electric signal to a predetermined level.
A pre-amplifier that outputs a negative-phase signal of a first positive-phase signal, a second positive-phase signal that is a binary average value of a value of the first positive-phase signal and a value obtained by peak-holding the first negative-phase signal, In the case of a signal, the value of the first negative-phase signal and the value obtained by peak-holding the first positive-phase signal are used, and in the case of no signal, the average value of the offset voltage set to a value higher than this value is used. Said the second
An automatic threshold value control circuit for outputting a second negative-phase signal having a negative-phase relationship with the positive-phase signal of the second phase signal;
A discriminator for determining a logical value of 0 when the burst digital optical signal is not signaled from the opposite phase signal, and for logically judging an intermediate value of the amplitude value of the burst digital optical signal and outputting logical values 1 and 0 for the signal. And a burst digital optical receiver. 2. An automatic threshold control circuit comprising: a first peak hold circuit for holding a maximum value of the first positive-phase signal; and a second peak hold circuit for holding a maximum value of the first negative-phase signal. A hold circuit, a bottom hold circuit that holds a minimum value of the first positive-phase signal, first and second reference voltage sources, an output signal of the first peak hold circuit, and the first reference voltage A comparator which compares the output signal voltage of the first peak hold circuit with the output signal voltage of the first reference voltage source and outputs a logical value H if the output signal voltage is lower than the output signal voltage of the first reference voltage source; An adder for adding the output signal of the bottom hold circuit and the output signal of the second reference voltage source; and an output signal of the first peak hold circuit and an output signal of the adder, the comparator taking in the output signal. Logical value H
In the case of, the output signal of the first peak hold circuit or L
In this case, the selection circuit for selecting the output signal of the adder, the first normal phase signal and the output signal of the second peak hold circuit are fetched, and the average value of these signals is converted to a logical judgment value. A first average value circuit that outputs an output signal as a second positive-phase signal, a first negative-phase signal, and an output signal of the selection circuit. 2. The burst digital optical receiver according to claim 1, further comprising a second average value circuit that outputs an output signal.