JPS6227569B2 - - Google Patents
Info
- Publication number
- JPS6227569B2 JPS6227569B2 JP1863679A JP1863679A JPS6227569B2 JP S6227569 B2 JPS6227569 B2 JP S6227569B2 JP 1863679 A JP1863679 A JP 1863679A JP 1863679 A JP1863679 A JP 1863679A JP S6227569 B2 JPS6227569 B2 JP S6227569B2
- Authority
- JP
- Japan
- Prior art keywords
- flip
- terminal
- flop
- output
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/007—Fail-safe circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1863679A JPS55110430A (en) | 1979-02-19 | 1979-02-19 | Fail safe type and circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1863679A JPS55110430A (en) | 1979-02-19 | 1979-02-19 | Fail safe type and circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55110430A JPS55110430A (en) | 1980-08-25 |
| JPS6227569B2 true JPS6227569B2 (enrdf_load_html_response) | 1987-06-16 |
Family
ID=11977088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1863679A Granted JPS55110430A (en) | 1979-02-19 | 1979-02-19 | Fail safe type and circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55110430A (enrdf_load_html_response) |
-
1979
- 1979-02-19 JP JP1863679A patent/JPS55110430A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55110430A (en) | 1980-08-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR910006735A (ko) | 디지탈 집적회로에 있어서의 테스트 용이화 회로 | |
| CA1266517C (en) | ROCKING CIRCUIT | |
| Pedersen et al. | The operator equation 𝑇𝐻𝑇= 𝐾 | |
| JPS6227569B2 (enrdf_load_html_response) | ||
| JPH0221814Y2 (enrdf_load_html_response) | ||
| Meyer | Five-coloring planar maps | |
| SU999165A1 (ru) | Резервированный релейный логический модуль | |
| WO1999017122A3 (en) | Current comparator | |
| JPS609221A (ja) | テスト機能付分周回路 | |
| JPH0654860B2 (ja) | フリップフロップ回路 | |
| KR950001439Y1 (ko) | R-s 플립플롭 | |
| JPS6127024A (ja) | 選択回路 | |
| Nashier et al. | Determination of a unique solution of the quadratic partition for primes p≡ 1 (mod 7) | |
| US4038569A (en) | Bistable circuit | |
| JPS6020076Y2 (ja) | クロツク表示装置 | |
| JPH0355200Y2 (enrdf_load_html_response) | ||
| SU754553A1 (ru) | Устройство для дистанционной защиты линий электропередачи от повреждения 1 | |
| JPH0537306A (ja) | フリツプフロツプ回路 | |
| SU811489A1 (ru) | Смеситель | |
| JPH03216897A (ja) | シフトレジスタ | |
| JPH02308616A (ja) | エッジ検出回路 | |
| JPS63257139A (ja) | チヤタリング防止回路 | |
| JPH0522121A (ja) | 分周器 | |
| JPH05218852A (ja) | 多数決回路 | |
| JPS59229923A (ja) | 集積回路用論理回路 |