JPS62274684A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62274684A JPS62274684A JP11952086A JP11952086A JPS62274684A JP S62274684 A JPS62274684 A JP S62274684A JP 11952086 A JP11952086 A JP 11952086A JP 11952086 A JP11952086 A JP 11952086A JP S62274684 A JPS62274684 A JP S62274684A
- Authority
- JP
- Japan
- Prior art keywords
- mount
- parallel
- semiconductor laser
- end surface
- laser chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 229910000679 solder Inorganic materials 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims description 9
- 238000007747 plating Methods 0.000 claims description 9
- 238000002844 melting Methods 0.000 abstract description 2
- 230000008018 melting Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 2
- 230000010355 oscillation Effects 0.000 description 11
- 230000000694 effects Effects 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
3、発明の詳細な説明
〔産業上の利用分野〕
この発明は、半導体チップが半田材によってマウントに
接着されて構成される半導体装置に関するものである。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device in which a semiconductor chip is bonded to a mount using a solder material.
以下、接合を下にして接着されるジャンクションダウン
型の半導体装置を例にとって説明する。Hereinafter, a description will be given by taking as an example a junction-down type semiconductor device that is bonded with the bonding side facing down.
第4図は従来のジャンクションダウン型の半導体チップ
、例久ば半導体レーザチップの構造を示す斜視図である
。この図において、半導体レーザチップ1は、半導体基
板11.下クラッド層12゜活性層13.上クラッド層
14.コンタクト層15から構成されており、半導体基
板11側には裏面Ti極21が、コンタクト層15側に
は表面電極22がそれぞれ被着されている。接きは、活
性層13の位ffiに形成されている。ジャンクション
ダウン型の半導体レーザチップ1は、接合を下にして組
み立てろ際の半田材によるショー)・を防ぐために、表
面電極22の上にさらにメ・フキ電極23が形成されて
、電極の高さをかせいでいろ。FIG. 4 is a perspective view showing the structure of a conventional junction-down type semiconductor chip, for example a semiconductor laser chip. In this figure, a semiconductor laser chip 1 includes a semiconductor substrate 11. Lower cladding layer 12° active layer 13. Upper cladding layer 14. It is composed of a contact layer 15, and a back Ti electrode 21 is attached to the semiconductor substrate 11 side, and a front electrode 22 is attached to the contact layer 15 side. A contact is formed at the active layer 13 ffi. In the junction-down type semiconductor laser chip 1, in order to prevent soldering caused by the solder material when assembled with the junction facing down, a metal foil electrode 23 is further formed on the surface electrode 22 to reduce the height of the electrode. Let's make it happen.
第5図は上記従来のジャンクンヨノダウン型の半導体レ
ーザチップ1を、マウンl−3に装着した状態を示す斜
視図である。半導体レーザチップ1は半田材2を介して
接合を下にして、すなわち、メッキ電極23を下にして
マウント3に接着される。接着の際、半導体レーザチッ
プ1の発振端面1Aは、マウント3の端面(発振端面1
Aと合わせるべき面)3Aと同一平面となるように位置
することが望ましい。もし、半導体レーザチップ1の発
振端面1Aがマウント3の端面3Aよりも後退して接着
されろと、特にジャンクションダウンに組み立てられて
いる場合、レーザ光がマウント3によりけられるという
問題点がある。また逆に、半導体レーザチップ1の発振
端面1Aがマウント3の端面3Aより突出して接着され
ると、熱放出効果が悪くなるという問題点がある。FIG. 5 is a perspective view showing a state in which the conventional jump-down type semiconductor laser chip 1 is mounted on a mount l-3. The semiconductor laser chip 1 is bonded to the mount 3 via the solder material 2 with the bonding side facing down, that is, the plating electrode 23 facing down. When bonding, the oscillation end face 1A of the semiconductor laser chip 1 is attached to the end face of the mount 3 (oscillation end face 1A).
Surface to be aligned with A) It is desirable to position it so that it is on the same plane as 3A. If the oscillation end face 1A of the semiconductor laser chip 1 is bonded so as to be set back from the end face 3A of the mount 3, especially when assembled in a junction-down manner, there is a problem that the laser beam will be eclipsed by the mount 3. Conversely, if the oscillation end face 1A of the semiconductor laser chip 1 is bonded so as to protrude from the end face 3A of the mount 3, there is a problem that the heat dissipation effect becomes worse.
ところで、従来の半導体装置では、半導体レーザチップ
1の発振端面1Aとマウント3の端面3Aとの位置合わ
せは目視のみで行っていたので、両端面IA、3Aが同
一平面に位置するよ弓に合わせることが非常に難しく、
例えば第6図に示すように、半導体レーザチップ1がマ
ウント3に平行に接着されなかったり、第7図に示すよ
うに、半導体レーザチップ1がマウント3より後退した
り、逆に第8図に示すように、半導体レーザチップ1が
マウント3より突出して接着される等組み立て時の信頼
性および作業性に多くの問題点があった。By the way, in conventional semiconductor devices, the alignment between the oscillation end face 1A of the semiconductor laser chip 1 and the end face 3A of the mount 3 was performed only by visual inspection, so both end faces IA and 3A were aligned in the bow so that they were located on the same plane. It is very difficult to
For example, as shown in FIG. 6, the semiconductor laser chip 1 may not be bonded parallel to the mount 3, or as shown in FIG. As shown, there were many problems in reliability and workability during assembly, such as the semiconductor laser chip 1 protruding from the mount 3 and being adhered.
この発明は、上記のような問題点を解消するためになさ
れたもので、半導体チップの端面がマウントの端面に対
して平行で、かつ後退しないように、同一平面となるよ
うに容易に位置合わせすることができる半導体装置を得
ることを目的とする。This invention was made to solve the above-mentioned problems, and it is possible to easily align the end face of the semiconductor chip so that it is parallel to the end face of the mount and on the same plane so that it does not retreat. The object of the present invention is to obtain a semiconductor device that can perform the following steps.
この発明に係る半導体装置は、マウントを接着するため
のメッキ電極に半導体チップの端面と同一平面となる端
面を有し、かつこの端面と平行な面を有する突起部を設
けたものである。In the semiconductor device according to the present invention, a plating electrode for adhering a mount is provided with a protrusion having an end surface flush with the end surface of the semiconductor chip and a surface parallel to the end surface.
この発明においては、半導体チップをマウントに接着す
る際に、メッキ電極の突起部の端面に平行な面と、マウ
ントの端面とを密着させることにより、半導体チップの
端面がマウントの端面に対して平行で、かつ後退しない
ように位置合わせされる。In this invention, when bonding the semiconductor chip to the mount, the end surface of the semiconductor chip is parallel to the end surface of the mount by bringing the surface parallel to the end surface of the protrusion of the plated electrode into close contact with the end surface of the mount. , and is positioned so that it does not move backward.
以下、この発明の実施例を図面について説明する。なお
、この実施例の説明においては、従来の説明と重複する
部分については、適宜その説明を省略する。Embodiments of the present invention will be described below with reference to the drawings. In addition, in the description of this embodiment, the description of parts that overlap with the conventional description will be omitted as appropriate.
第1図はこの発明の一実施例である半導体装置を構成す
る半導体チップ、例えば半導体レーザチップを示す斜視
図である。この図において、24は前記半導体レーザチ
ップ1の発振端面1Aと同一平面となる端面24Aと、
この端面?lAと平行な面2dBを有する突起部である
。FIG. 1 is a perspective view showing a semiconductor chip, such as a semiconductor laser chip, constituting a semiconductor device according to an embodiment of the present invention. In this figure, reference numeral 24 denotes an end face 24A that is flush with the oscillation end face 1A of the semiconductor laser chip 1;
This edge? This is a protrusion having a surface of 2 dB parallel to lA.
第2図はこの発明の一実施例である半導体装置の斜視図
で、第1図に示した半導体レーザチップ1を用いて構成
されたものである。すなわち、第1図に示す半導体レー
ザチップ1を半田材2を介してマウント3上に載せ、半
田材2の融点まで加熱すると、半田材2は溶融する。こ
の時、メッキ電極23の突起部24の端面24Aに平行
な面24Bをマウント3の端面3Aと密着させることに
より、半導体レーザチップ1の発振端面1Aはマウント
3の端面3Aに対して平行で、かつ後退しないように位
置合わせすることができる。FIG. 2 is a perspective view of a semiconductor device according to an embodiment of the present invention, which is constructed using the semiconductor laser chip 1 shown in FIG. That is, when the semiconductor laser chip 1 shown in FIG. 1 is placed on the mount 3 via the solder material 2 and heated to the melting point of the solder material 2, the solder material 2 is melted. At this time, by bringing the surface 24B parallel to the end surface 24A of the protrusion 24 of the plated electrode 23 into close contact with the end surface 3A of the mount 3, the oscillation end surface 1A of the semiconductor laser chip 1 is parallel to the end surface 3A of the mount 3. In addition, the position can be adjusted so as not to move backward.
また第2図に示した実施例では、半導体レーザチップ1
の発振端面1Aは、マウント3の端面3Aよりメッキ電
極23の突起部24の厚み分だけ前面に突出しているが
、この実施例の場合、突起部24はマウント3と半田材
2とによって完全に接着されているので、半導体レーザ
駆動時の熱放出の効果が何ら減少することがない。Further, in the embodiment shown in FIG. 2, the semiconductor laser chip 1
The oscillation end surface 1A of the mount 3 protrudes forward from the end surface 3A of the mount 3 by the thickness of the protrusion 24 of the plated electrode 23, but in the case of this embodiment, the protrusion 24 is completely covered by the mount 3 and the solder material 2. Since they are bonded, the effect of heat release during driving of the semiconductor laser is not reduced in any way.
第3図はこの発明の他の実施例を示す半導体装置の斜視
図で、第1図に示した半導体レーザチップ1を用いて構
成されたものである。第3図に示した実施例では、半導
体レーザチップ1の発振端面1Aと合わせるべき面であ
るマウント3の端面3Aを変形したものである。すなわ
ち、マウント3の端面3Aと直角な一面3Cとが交差す
る部分にマウント3の端面3Aと平行な面3Bを持つ直
方体の凹部3Dを設けている。半導体レーザチップ1を
マウント3に接着するに際しては、メッキ電極23の突
起部24の端面24Aに平行な面2dBを、マウンl−
3の凹部3Dのマウント3の端面3Aと平行な面3Bに
密着させることにより、半導体レーザチップ1の発振端
面1Aをマウント3の端面3Aと平行にすることができ
る。FIG. 3 is a perspective view of a semiconductor device showing another embodiment of the invention, which is constructed using the semiconductor laser chip 1 shown in FIG. 1. In the embodiment shown in FIG. 3, the end surface 3A of the mount 3, which is the surface to be aligned with the oscillation end surface 1A of the semiconductor laser chip 1, is modified. That is, a rectangular parallelepiped recess 3D having a surface 3B parallel to the end surface 3A of the mount 3 is provided at the intersection of the end surface 3A of the mount 3 and a perpendicular surface 3C. When bonding the semiconductor laser chip 1 to the mount 3, a surface 2 dB parallel to the end surface 24A of the protrusion 24 of the plating electrode 23 is attached to the mount l-
By bringing the concave portion 3D of No. 3 into close contact with the surface 3B parallel to the end surface 3A of the mount 3, the oscillation end surface 1A of the semiconductor laser chip 1 can be made parallel to the end surface 3A of the mount 3.
また第3図に示す実施例では、マウント3の凹部3Dの
寸法をメッキ電極23の突起部24の厚みの寸法と合わ
せろことにより、半導体レーザチップ1とマウント3と
の前後左右の位Fa 合わせを極めて精度よく行うこと
ができる。In addition, in the embodiment shown in FIG. 3, by matching the dimensions of the recess 3D of the mount 3 with the thickness of the protrusion 24 of the plating electrode 23, the alignment of the semiconductor laser chip 1 and the mount 3 in the front, back, left, and right directions can be achieved. This can be done with extreme precision.
なお、上記実施例では、半導体レーザチップ1の接合を
下にして接着する場合について示したが、接合を上にし
て接着する場合でも、裏面電極21の上にメッキ電極2
3と突起部24を設けることにより、同様の半導体装置
を形成できろことはいうまでもない。In the above embodiment, the case where the semiconductor laser chip 1 is bonded with the bond side down is shown, but even if the semiconductor laser chip 1 is bonded with the bond side up, the plating electrode 2 is placed on the back electrode 21.
It goes without saying that a similar semiconductor device can be formed by providing the protrusion 3 and the protrusion 24.
この発明は以上説明したとおり、半導体チップの表面電
極上または裏面電極上に形成されるメッキ電極に、半導
体チップの端面と同一平面となる端面を有し、かつこの
端面と平行な面を有する突起部を設けたので、この突起
部の端面と平行な面とをマウントの端面と密着させるこ
とにより、半導体チップとマウントとの位置合わせを精
度よく行うことがき、したがって、半導体装置の組み立
ての信頼性および作業性2強いては歩留りを著しく向上
させる乙とができる利点が得られる。As explained above, the present invention provides a protrusion on a plating electrode formed on a front surface electrode or a back surface electrode of a semiconductor chip, which has an end surface that is flush with the end surface of the semiconductor chip and has a surface that is parallel to this end surface. Since the projection is provided with a parallel surface, the end surface of the protrusion and the surface parallel to the end surface of the mount can be brought into close contact with the end surface of the mount, thereby making it possible to accurately align the semiconductor chip and the mount, thereby improving the reliability of the assembly of semiconductor devices. and workability 2. In particular, there are advantages in that the yield can be significantly improved.
第1図はこの発明の一実施例である半導体装置を構成す
る半導体レーザチップを示す斜視図、第2図はこの発明
の一実施例を示す半導体装置の斜視図、第3図はこの発
明の他の実施例を示す半導体装置の斜視図、第4図は従
来のジャンクションダウン型の半導体レーザチップの構
造を示す斜視図、第5図は従来のジャンクシコンダウン
型の半導体レーザチップをマウントに装着した状態を示
す斜視図、第6図は半導体レーザチップがマウントに平
行に接着されていない状態を示す斜視図、第7図は半導
体レーザチップがマウントより後退して接着された状態
を示す斜視図、第8図は半導体レーザチップがマウント
より突出して接着された状態を示す斜視図である。
図において、1は半導体レーザチップ、1Aは発振端面
、2は半田材、3はマウン15.3Aはマウントの端面
、3Bはマウントの端面と平行な面、21は裏面電極、
22は表i電極、23はメッキ電極、24は突起部、2
dAは端面、24Bは平行な面である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 (外2名)第1図
24B、平庁η面
第2図
第3図
3B・マクントの溝面と1呵〒σ面
第4図
第5図
第6図
第7図
第8図
手続補正書([4つL
61 12 ど2
昭和 年 月 日
持許庁長宮殿
3、補正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目2番3号名
称 (601)三菱電機株式会社代表者 志 岐
守 哉
4、代理人
住 所 東京都千代田区丸の内二丁目2番3号三
菱電機株式会社内
氏名 (7375)弁理士大岩増雄。
(連絡先03(213>3421特許部)5、m正の対
象
明細書の発明の詳細な説明の欄および図面6、補正の内
容
(1)明細書第5頁2行の「おいては、」を。
「おいて、」と補正する。
(2)同じく第8頁4行のr強いてはjを、「ひいては
」と補正する。
(3)第3図、第5図を別紙のように補正する。
以 上FIG. 1 is a perspective view showing a semiconductor laser chip constituting a semiconductor device which is an embodiment of the present invention, FIG. 2 is a perspective view of a semiconductor device which is an embodiment of the invention, and FIG. A perspective view of a semiconductor device showing another embodiment, FIG. 4 is a perspective view showing the structure of a conventional junction down type semiconductor laser chip, and FIG. 5 shows a conventional junction down type semiconductor laser chip mounted on a mount. 6 is a perspective view showing a state in which the semiconductor laser chip is not bonded parallel to the mount, and FIG. 7 is a perspective view showing a state in which the semiconductor laser chip is retreated from the mount and bonded. , FIG. 8 is a perspective view showing a state in which the semiconductor laser chip protrudes from the mount and is bonded. In the figure, 1 is a semiconductor laser chip, 1A is an oscillation end surface, 2 is a solder material, 3 is a mount 15. 3A is an end surface of a mount, 3B is a surface parallel to the end surface of the mount, 21 is a back electrode,
22 is a front i-electrode, 23 is a plating electrode, 24 is a protrusion, 2
dA is an end surface, and 24B is a parallel surface. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others) Figure 1 24B, Heicho η plane Figure 2 Figure 3 Figure 3B, Makunto groove surface and 12〒σ plane Figure 4 Figure 6 Figure 7 Figure 8 Procedural amendment document ([4 L 61 12 d 2 Showa year/month/day/month/year/month/year/month/year/month/year/month/year/year/month/day/year/month/year/year/month/year/year/year/month/day.relationshipwiththecaseofthepersonwhomakesthe amendment Patent applicant address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo) Name (601) Mitsubishi Electric Corporation Representative Shiki
Moriya 4, Agent address: Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (7375) Masuo Oiwa, patent attorney. (Contact information 03 (213>3421 Patent Department) 5, column for detailed description of the invention in the subject specification and drawing 6, contents of amendment (1) "In the second line of page 5 of the specification," ”. Correct it as “by extension.” (2) Similarly, in page 8, line 4, r should be corrected to “by extension.” Correct. That's all.
Claims (1)
たメッキ電極を半田材を介してマウントに接着した半導
体装置において、前記メッキ電極に前記半導体チップの
端面と同一平面となる端面を有し、かっこの端面と平行
な面を有する突起部を設け、この突起部の前記端面と平
行な面を前記マウントの端面に密着せしめて接着したこ
とを特徴とする半導体装置。In a semiconductor device in which a plating electrode formed on a front surface electrode or a back surface electrode of a semiconductor chip is bonded to a mount via a solder material, the plating electrode has an end surface that is flush with the end surface of the semiconductor chip; 1. A semiconductor device comprising: a protrusion having a surface parallel to the end surface of the mount; and a surface of the protrusion parallel to the end surface of the mount is closely bonded to the end surface of the mount.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11952086A JPS62274684A (en) | 1986-05-22 | 1986-05-22 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11952086A JPS62274684A (en) | 1986-05-22 | 1986-05-22 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62274684A true JPS62274684A (en) | 1987-11-28 |
Family
ID=14763307
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11952086A Pending JPS62274684A (en) | 1986-05-22 | 1986-05-22 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62274684A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20000040031A (en) * | 1998-12-17 | 2000-07-05 | 구자홍 | Solder evaporation method for a laser diode assembling |
JP2006303299A (en) * | 2005-04-22 | 2006-11-02 | Sharp Corp | Semiconductor laser |
-
1986
- 1986-05-22 JP JP11952086A patent/JPS62274684A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20000040031A (en) * | 1998-12-17 | 2000-07-05 | 구자홍 | Solder evaporation method for a laser diode assembling |
JP2006303299A (en) * | 2005-04-22 | 2006-11-02 | Sharp Corp | Semiconductor laser |
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