JPH04299541A - Structure and method for performing die bonding - Google Patents
Structure and method for performing die bondingInfo
- Publication number
- JPH04299541A JPH04299541A JP3087656A JP8765691A JPH04299541A JP H04299541 A JPH04299541 A JP H04299541A JP 3087656 A JP3087656 A JP 3087656A JP 8765691 A JP8765691 A JP 8765691A JP H04299541 A JPH04299541 A JP H04299541A
- Authority
- JP
- Japan
- Prior art keywords
- die
- bonding
- base material
- oxide
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 25
- 239000000463 material Substances 0.000 claims description 63
- 239000004020 conductor Substances 0.000 claims description 30
- 239000011521 glass Substances 0.000 abstract description 37
- 239000000758 substrate Substances 0.000 abstract description 23
- 229910052710 silicon Inorganic materials 0.000 abstract description 15
- 239000010703 silicon Substances 0.000 abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 239000005355 lead glass Substances 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 3
- 239000002585 base Substances 0.000 description 55
- 239000002184 metal Substances 0.000 description 23
- 229910052751 metal Inorganic materials 0.000 description 23
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 230000008646 thermal stress Effects 0.000 description 6
- 239000012530 fluid Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- 239000003513 alkali Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、ＩＣチップやＬＳＩチ
ップ等のダイをガラス基板やパッケージ等の基材に固定
するためのボンディング構造およびボンディング方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bonding structure and bonding method for fixing a die such as an IC chip or an LSI chip to a base material such as a glass substrate or a package.
【０００２】0002
【従来の技術】ＩＣチップを基板に固定するには、従来
、ダイと基材との間に銀ペーストや接着剤、あるいはＳ
ｉ−Ａｕの共晶接合を介在させて行っていた。[Prior Art] Conventionally, in order to fix an IC chip to a substrate, silver paste, adhesive, or S
This was done by interposing i-Au eutectic bonding.
【０００３】0003
【発明が解決しようとする課題】液晶パネル等において
ＩＣチップ実装のために占有される面積を小さくするた
めには、画素ピッチＰｐとボンディングピッチＰｂを等
しくして、ＩＣチップの長辺に沿って出力端子を設ける
とよい。図４（ａ）（ｃ）に示すように、ＰｐがＰｂよ
り大であっても小であっても、ＰｐとＰｂの差を解消す
るためには配線を引き回す必要があり、この配線引き回
し部２０のためにかなりの面積が占有される。これに対
して図４（ｂ）に示すように、Ｐｐ＝Ｐｂにすると配線
の引き回しが不要となり、実装のために占有される面積
が小となる。[Problems to be Solved by the Invention] In order to reduce the area occupied by IC chip mounting in a liquid crystal panel, etc., it is necessary to make the pixel pitch Pp and the bonding pitch Pb equal, and to It is recommended to provide an output terminal. As shown in FIGS. 4(a) and 4(c), whether Pp is larger or smaller than Pb, it is necessary to route the wiring in order to eliminate the difference between Pp and Pb. 20 occupies a considerable area. On the other hand, as shown in FIG. 4(b), when Pp=Pb, there is no need to route the wiring, and the area occupied for mounting becomes small.
【０００４】ところで、画素ピッチＰｐが数１０から１
００μｍと高密度化が進んだ液晶パネルやプリンターヘ
ッドにＩＣチップを実装する際には、前記のようにＰｐ
＝Ｐｂとすると、ＩＣチップと基材の位置を正確に合わ
せて固定する必要が生じる。By the way, the pixel pitch Pp is from several tens to 1
When mounting IC chips on liquid crystal panels and printer heads, which have a high density of 00 μm, as mentioned above, Pp
=Pb, it becomes necessary to accurately align and fix the IC chip and the base material.
【０００５】ところが、前述のように接着剤等を用いて
ＩＣチップと基材とを固定すると、接着時には接着界面
部分が一時流動状態を経るため、接着界面が固化するま
での間に、図５に示すようにＩＣチップ１が位置ずれし
易く、位置合わせ精度を高く維持することが難しい。However, when the IC chip and the base material are fixed using an adhesive or the like as described above, the adhesive interface part temporarily goes through a fluid state during adhesion, so that the adhesive interface part is temporarily in a fluid state until the adhesive interface solidifies. As shown in FIG. 2, the IC chip 1 is easily misaligned, and it is difficult to maintain high alignment accuracy.
【０００６】なお図５中符号２は基材、符号３は基材側
電極、符号４はチップ側電極、符号５はバンプである。
そして図５（ａ）はワイヤー６によってＩＣチップ１の
電極４と基材２の電極３とを電気的に接続するタイプ、
図５（ｂ）はフェイスダウンによってＩＣチップ１のバ
ンプ５を基材２の電極３に接続するタイプを示している
。In FIG. 5, reference numeral 2 represents a base material, reference numeral 3 represents an electrode on the base material side, reference numeral 4 represents an electrode on the chip side, and reference numeral 5 represents a bump. FIG. 5(a) shows a type in which the electrode 4 of the IC chip 1 and the electrode 3 of the base material 2 are electrically connected by the wire 6.
FIG. 5(b) shows a type in which the bumps 5 of the IC chip 1 are connected to the electrodes 3 of the base material 2 by face-down.
【０００７】本発明は前記事情に鑑みてなされたもので
、高い精度でダイを固定できるダイボンディング構造及
び方法を提供することを目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a die bonding structure and method that can secure a die with high precision.
【０００８】[0008]
【課題を解決するための手段】本発明のダイボンディン
グ構造は、ダイを基材に固定するダイボンディング構造
において、ダイまたは基材の一方の少なくとも表面が酸
化物を形成し得る導体であり、他方の少なくとも表面が
酸化物であり、これらの表面が陽極接合されてダイと基
材を固定する接合部を形成していることを特徴とする。Means for Solving the Problems The die bonding structure of the present invention is a die bonding structure for fixing a die to a base material, in which at least the surface of either the die or the base material is a conductor capable of forming an oxide, and the other surface is a conductor capable of forming an oxide. At least the surface of the die is an oxide, and these surfaces are anodically bonded to form a joint that fixes the die and the base material.
【０００９】この酸化物としては、鉛ガラスや、硼ケイ
酸ガラス、パイレックスガラス等各種のガラスおよびＬ
ｉＮｂＯ３、水晶等の単結晶を利用できるが、導体との
接合処理を低温で行える点で鉛ガラス、硼ケイ酸ガラス
等の低温で変形し易い低融点ガラスを利用することが望
ましい。[0009] Examples of this oxide include lead glass, borosilicate glass, Pyrex glass, etc., and various types of glass.
Although single crystals such as iNbO3 and quartz can be used, it is preferable to use low-melting point glasses that are easily deformed at low temperatures, such as lead glass and borosilicate glass, since the bonding process with the conductor can be performed at low temperatures.
【００１０】酸化物を成膜した基材を用いる場合、酸化
物の膜厚は、通常５０００オンク゛ストローム以上で有
れば良いが、接合処理作業での歩留まりが高いという点
で４μｍ程度に設定されることが望ましい。[0010] When using a base material on which an oxide film is formed, the thickness of the oxide film should normally be 5000 angstroms or more, but it is set to about 4 μm from the viewpoint of high yield in bonding processing work. This is desirable.
【００１１】導体としては、シリコン（Ｓｉ）やガリウ
ムひ素（ＧａＡｓ）、アルミニウム（Ａｌ）、インジウ
ム錫酸化物（ＩＴＯ）など各種の導体を利用できるが、
接合し易さの点で、Ａｌ，Ｓｉが適している。Various conductors such as silicon (Si), gallium arsenide (GaAs), aluminum (Al), and indium tin oxide (ITO) can be used as the conductor.
Al and Si are suitable from the viewpoint of ease of joining.
【００１２】前記接合部は、ダイの長さ方向の中央部の
みに設けられることが望ましい。また接合部の大きさは
、熱応力を小さく抑えるために強度上の問題がない限り
、できるだけ小さい方が良い。[0012] It is preferable that the joint portion is provided only at a central portion in the length direction of the die. Furthermore, the size of the joint is preferably as small as possible in order to keep thermal stress to a minimum unless there is a problem with strength.
【００１３】このようなダイボンディングを行う方法と
しては、ダイまたは基材の一方を酸化可能な導体からな
る基材又は酸化可能な導体を成膜した基材とし、他方を
酸化物からなる基材又は酸化物を成膜した基材とし、こ
れらを重ね合わせて酸化物側がマイナス、導体側がプラ
スとなるように両者間に電圧を印加して陽極接合する。
酸化物を成膜する方法としては、スパッタ法、蒸着
法、ガスデポジション、印刷ー焼成法など各種の方法を
採用できる。[0013] As a method for performing such die bonding, one of the die and the base material is a base material made of an oxidizable conductor or a base material on which a film of an oxidizable conductor is formed, and the other is a base material made of an oxide. Alternatively, a base material on which an oxide film is formed is used, and these are stacked and anodic bonded by applying a voltage between them so that the oxide side becomes negative and the conductor side becomes positive. Various methods can be used to form the oxide film, such as sputtering, vapor deposition, gas deposition, and printing-baking.
【００１４】[0014]
【作用】本発明のダイボンディング構造では、接着剤等
を介さず酸化物を形成し得る導体と酸化物とを直接陽極
接合でき、導体と酸化物の酸素との間で強固に化学結合
するため、信頼性の高いダイボンディンク゛が可能にな
る。この陽極接合は接合界面が固相状態のままで行われ
るため、位置合わせ精度を高く保ことができる。[Operation] In the die bonding structure of the present invention, a conductor capable of forming an oxide and an oxide can be directly anodically bonded without using an adhesive or the like, and a strong chemical bond is formed between the conductor and the oxygen in the oxide. This enables highly reliable die bonding. Since this anodic bonding is performed while the bonding interface remains in a solid state, high alignment accuracy can be maintained.
【００１５】前記接合部をダイの長さ方向の中央部のみ
に設けると、接合後温度変化があった場合にダイと基材
の熱膨張の差によって接合部分に生じる熱応力を小さく
抑えることができる。しかも接合部を中央部に設けると
、固定されている接合部からダイの端部までの距離が短
くなるので、ダイと基材との熱膨張の差によって、ダイ
端部に顕著にあらわれる基板側電極とダイ側電極との位
置ずれも小さくでき、信頼性が向上する。[0015] When the joint portion is provided only at the center portion of the die in the length direction, it is possible to suppress thermal stress generated in the joint portion due to the difference in thermal expansion between the die and the base material to a small level when there is a temperature change after joining. can. Moreover, if the joint is located in the center, the distance from the fixed joint to the edge of the die becomes shorter, so the difference in thermal expansion between the die and the base material causes the substrate side to appear more prominently at the die end. Misalignment between the electrode and the die-side electrode can also be reduced, improving reliability.
【００１６】また本発明のダイボンディング方法では、
酸化物側がマイナス、導体側がプラスとなるように両者
間に電圧を印加するので、酸化物中のアルカリイオンな
どの可動イオンがマイナス極側に移動し、これに伴い酸
化物と導体との間に大きな静電引力が生じる。また界面
の部分で酸化物中の酸素と導体の化学結合が生じて酸化
物と導体とが強固に接合する。このとき酸化物と接合用
導体との界面が流動状態になることはなく、位置合わせ
精度を高く保つことができる。[0016] Furthermore, in the die bonding method of the present invention,
Since a voltage is applied between the two so that the oxide side is negative and the conductor side is positive, mobile ions such as alkali ions in the oxide move to the negative electrode side, and as a result, a voltage is applied between the oxide and the conductor. A large electrostatic attraction occurs. Further, a chemical bond occurs between oxygen in the oxide and the conductor at the interface, and the oxide and the conductor are firmly bonded. At this time, the interface between the oxide and the bonding conductor does not enter a fluid state, and high alignment accuracy can be maintained.
【００１７】[0017]
【実施例】以下、図面を参照して本発明のダイボンディ
ング構造と方法を詳しく説明する。なお前記従来例と同
一構成部分には、同一符号を付して説明を簡略化する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The die bonding structure and method of the present invention will be explained in detail below with reference to the drawings. Note that the same components as those in the conventional example are given the same reference numerals to simplify the explanation.
【００１８】（実施例１）図１は、本発明のダイボンデ
ィング構造によって接合されたガラス製の基材２とＩＣ
チップ１を示している。ＩＣチップ１は長方形状のシリ
コン基板７の表面側９に回路が形成されたものである。
さらにこのシリコン基板７の表面側には、長手方向に延
びる辺に沿ってバンプ５が設けられている。(Example 1) FIG. 1 shows a glass substrate 2 and an IC bonded by the die bonding structure of the present invention.
Chip 1 is shown. The IC chip 1 has a circuit formed on the front side 9 of a rectangular silicon substrate 7. Furthermore, bumps 5 are provided on the front side of the silicon substrate 7 along the sides extending in the longitudinal direction.
【００１９】このシリコン基板７の表面側９にはさらに
接合用ガラス層８が形成されている。接合用ガラス層８
は、鉛ガラスによって形成されている。この接合用ガラ
ス層８は、直径２ｍｍに形成されており、シリコン基板
７の中央部に配置されている。この接合用ガラス層の直
径は熱応力を小さく抑えるために、強度上の問題がない
限り、できるだけ小さい方が良く、２ｍｍ以下が良い。
この接合用ガラス層８の厚さは、約４μｍである。A bonding glass layer 8 is further formed on the front side 9 of this silicon substrate 7. Bonding glass layer 8
is made of lead glass. This bonding glass layer 8 is formed to have a diameter of 2 mm and is placed at the center of the silicon substrate 7. In order to suppress thermal stress, the diameter of this bonding glass layer is preferably as small as possible, preferably 2 mm or less, unless there is a problem with strength. The thickness of this bonding glass layer 8 is approximately 4 μm.
【００２０】またシリコン基板７の裏面側には、後述す
る陽極接合処理時に電圧を印加するために用いるコンタ
クトパッド１１が、オーミックコンタクト用不純物拡散
層１０を介して設けられている。Further, on the back side of the silicon substrate 7, a contact pad 11 used for applying a voltage during an anodic bonding process, which will be described later, is provided through an impurity diffusion layer 10 for ohmic contact.
【００２１】基材２はガラス製のもので、その表面には
Ａｌ製の接合用金属層１２が設けられている。この接合
用金属層１２は、前記接合用ガラス層８と一致する箇所
に設けられている。またこの接合用金属層１２は、通常
は厚さ１．０μｍ程度に形成されているが、表面粗さが
Ｒｍａｘ≦０．０５μｍであれば、厚さは特に問わない
。。The base material 2 is made of glass, and a bonding metal layer 12 made of Al is provided on its surface. This bonding metal layer 12 is provided at a location that coincides with the bonding glass layer 8. Further, the bonding metal layer 12 is usually formed to have a thickness of about 1.0 μm, but the thickness is not particularly limited as long as the surface roughness is Rmax≦0.05 μm. .
【００２２】この接合用金属層１２には、後述する陽極
接合処理時に利用する配線１３が連接されている。[0022] This bonding metal layer 12 is connected with a wiring 13 to be used during an anodic bonding process, which will be described later.
【００２３】前記ＩＣチップ１に設けられた接合用ガラ
ス層８と基材２に設けられた接合用金属層１２は陽極接
合されて、接合部１４を形成している。この状態でＩＣ
チップ１のバンプ５と基材２の基板側電極３は電気的に
接続されている。そしてＩＣチップ１と基材２との間隙
は封止剤１５によって密封されている。The bonding glass layer 8 provided on the IC chip 1 and the bonding metal layer 12 provided on the base material 2 are anodically bonded to form a bonding portion 14. In this state, the IC
The bumps 5 of the chip 1 and the substrate-side electrodes 3 of the base material 2 are electrically connected. The gap between the IC chip 1 and the base material 2 is sealed with a sealant 15.
【００２４】次に前記のようにＩＣチップ１と基材２を
ダイボンデイングする方法を説明する。この方法では、
まず基材２の表面にＡｌをスパッタして接合用金属層１
２と電極１３を形成した。他方ＩＣチップ１のシリコン
基板７にも、鉛ガラスをスパッタして接合用ガラス層８
を形成した。Next, a method of die bonding the IC chip 1 and the base material 2 as described above will be explained. in this way,
First, Al is sputtered on the surface of the base material 2 to form a bonding metal layer 1.
2 and an electrode 13 were formed. On the other hand, a bonding glass layer 8 is also formed on the silicon substrate 7 of the IC chip 1 by sputtering lead glass.
was formed.
【００２５】ついでＩＣチップ１と基材２を重ねて位置
合わせし、接合用ガラス層８と接合用金属層１２を重ね
合わせ、ＩＣチップ１側のコンタクトパッド１１を電源
２１のマイナス極に接続し、基材２側の配線１３をプラ
ス極に接続して、接合用ガラス層８にマイナス、接合用
金属層１２にプラスの電圧を印加した。この時加えた電
圧は数１０Ｖであった。この様に電圧を印加したところ
、前記接合用ガラス層８と接合用金属層１２は陽極接合
された。この作業は、室温下で行った。Next, the IC chip 1 and the base material 2 are overlapped and aligned, the bonding glass layer 8 and the bonding metal layer 12 are overlapped, and the contact pad 11 on the IC chip 1 side is connected to the negative pole of the power source 21. The wiring 13 on the base material 2 side was connected to the positive electrode, and a negative voltage was applied to the bonding glass layer 8 and a positive voltage was applied to the bonding metal layer 12. The voltage applied at this time was several tens of volts. When voltage was applied in this way, the bonding glass layer 8 and the bonding metal layer 12 were anodic bonded. This work was performed at room temperature.
【００２６】この後、接合されたＩＣチップ１と基材２
との間に封止機能と接着機能を有する樹脂を塗布したあ
と真空容器に入れたことろ、ＩＣチップ１と基材２との
間に樹脂が行き渡り、これらをしっかり封止、接合でき
た。After that, the joined IC chip 1 and base material 2
After applying a resin having a sealing function and an adhesive function between the IC chip 1 and the base material 2, the resin was spread between the IC chip 1 and the base material 2, and the IC chip 1 and the base material 2 were firmly sealed and bonded.
【００２７】この実施例のダイボンディング構造では、
基材２に接合用金属層１２を設け、ＩＣチップ１に接合
用ガラス層８設けたので、これらの接合用層８，１２を
陽極接合することによってＩＣチップ１と基材２を固定
できる。接合用金属層１２と接合用ガラス層８との間は
、金属−酸素間の化学結合によって接合している。この
陽極接合は接合処理時に接合界面が液相になることがな
く固相状態のままで行なわれるので、このダイボンディ
ング構造によれば、ＩＣチップ１と基材２とを位置合わ
せした状態を保ちつつ接合処理できる。ＩＣチップ１と
基材２を位置精度良く固定できる。In the die bonding structure of this example,
Since the bonding metal layer 12 is provided on the base material 2 and the bonding glass layer 8 is provided on the IC chip 1, the IC chip 1 and the base material 2 can be fixed by anodic bonding these bonding layers 8 and 12. The bonding metal layer 12 and the bonding glass layer 8 are bonded by a metal-oxygen chemical bond. This anodic bonding is performed while the bonding interface does not become a liquid phase during the bonding process and remains in a solid phase, so according to this die bonding structure, the IC chip 1 and the base material 2 can be maintained in an aligned state. It can also be bonded. The IC chip 1 and the base material 2 can be fixed with high positional accuracy.
【００２８】またこの実施例のダイボンディング構造で
は、接合用ガラス層８を鉛ガラスで形成したので、接合
用ガラス層８と接合用金属層１２の陽極接合処理を室温
で行うことができる。従ってこの実施例のダイボンディ
ング構造では、接合処理の時と処理後とでのＩＣチップ
１及び基材２の寸法変化を回避でき、接合による残留応
力の発生を防止できる。Furthermore, in the die bonding structure of this embodiment, since the bonding glass layer 8 is formed of lead glass, the anodic bonding process between the bonding glass layer 8 and the bonding metal layer 12 can be performed at room temperature. Therefore, in the die bonding structure of this embodiment, it is possible to avoid dimensional changes in the IC chip 1 and the base material 2 between the time of the bonding process and after the process, and generation of residual stress due to bonding can be prevented.
【００２９】さらにこの実施例のダイボンディング構造
では、接合部１４をＩＣチップ１の長さ方向の中央部の
みに設け、他の部分を封止材１５で接合したので、接合
部１４が狭くＩＣチップ１と基材２との熱膨張の差によ
って接合部１４に生じる熱応力を小さく抑えることがで
きる。他の部分における熱膨張の差は、樹脂製の封止材
１５の変形により吸収できる。加えて接合部１４を中央
部に設けたので、接合部１４からＩＣチップ１の端部ま
での最長距離が短くなり、ＩＣチップ１と基材２との熱
膨張の差によるバンプ５，基板側電極３の位置づれが小
さくなる。従って、この実施例のダイボンディング構造
によれば、ＩＣチップ１と基材２との位置合わせ精度を
高く保ちつつ、熱応力も緩和することができる。そして
ＩＣチップ１を長くしてチップ１の実装数を減らし、作
業性を向上することが可能となる。Furthermore, in the die bonding structure of this embodiment, the bonding portion 14 is provided only at the center portion in the length direction of the IC chip 1, and the other portions are bonded with the sealing material 15. Therefore, the bonding portion 14 is narrow and the IC chip 1 is Thermal stress generated in the joint portion 14 due to the difference in thermal expansion between the chip 1 and the base material 2 can be suppressed to a small level. Differences in thermal expansion in other parts can be absorbed by deformation of the resin sealing material 15. In addition, since the joint part 14 is provided in the center, the longest distance from the joint part 14 to the end of the IC chip 1 is shortened, and the difference in thermal expansion between the IC chip 1 and the base material 2 causes bumps 5 and the substrate side. The positional deviation of the electrode 3 is reduced. Therefore, according to the die bonding structure of this embodiment, thermal stress can be alleviated while maintaining high alignment accuracy between the IC chip 1 and the base material 2. It is also possible to increase the length of the IC chip 1, reduce the number of chips 1 mounted, and improve work efficiency.
【００３０】またこの実施例のダイボンディング方法で
は、接合用ガラス層８がマイナス、接合用金属層１２が
プラスとなるように両者間に電圧を印加したので、ガラ
ス内でのアルカリイオンの移動に伴い、ガラスと金属と
の間に大きな静電気引力が生じる。また界面の部分でガ
ラス中の酸素と金属との化学結合が生じ、接合用ガラス
層８と接合用金属層１２とを強固に接合することができ
た。しかもこの接合処理は接合用ガラス層８と接合用金
属層１２との界面が固相の状態で行われ、接合界面が流
動状態になることはない。従ってこのダイボンディング
方法によれば、ＩＣチップ１と基材２を位置合わせした
時の状態を保ったまま接合することができ、これらを正
確に固定できる。Furthermore, in the die bonding method of this embodiment, since a voltage was applied between the bonding glass layer 8 and the bonding metal layer 12 so that the voltage was negative and the bonding metal layer 12 was positive, the movement of alkali ions within the glass was prevented. Accordingly, a large electrostatic attraction occurs between the glass and the metal. Further, a chemical bond was formed between the oxygen in the glass and the metal at the interface, and the bonding glass layer 8 and the bonding metal layer 12 could be firmly bonded. Moreover, this bonding process is performed while the interface between the bonding glass layer 8 and the bonding metal layer 12 is in a solid state, and the bonding interface is not in a fluid state. Therefore, according to this die bonding method, it is possible to bond the IC chip 1 and the base material 2 while maintaining their alignment, and it is possible to accurately fix them.
【００３１】なお前記実施例では、ＩＣチップ１のシリ
コン基板７に接合用ガラス層８を直接設けたが、シリコ
ン基板７と接合用ガラス層８との間には両者に密着性の
よい金属を介在させてもよい。In the above embodiment, the bonding glass layer 8 was directly provided on the silicon substrate 7 of the IC chip 1, but a metal with good adhesion between the silicon substrate 7 and the bonding glass layer 8 was used. It is also possible to intervene.
【００３２】（実施例２）図２は、本発明のダイボンデ
ィング構造の第２実施例を示すもので、前記実施例と同
一構成部分には、同一符号を付して説明を簡略化する。(Embodiment 2) FIG. 2 shows a second embodiment of the die bonding structure of the present invention, and the same components as in the previous embodiment are given the same reference numerals to simplify the explanation.
【００３３】この例のダイボンディング構造が前記実施
例１と異なる点は、ガラス製の基材２側に接合用ガラス
層８を設け、ＩＣチップ１のシリコン基板７側に接合用
金属層１２を設けた点である。また接合用ガラス層８は
、この接合用ガラス層８に電圧を印加するための電極１
３の上に設けられている。この電極１３は、基材２と接
合用ガラス層８の両方に密着性のよい導電材料で形成さ
れている。The die bonding structure of this example is different from the first embodiment described above in that a bonding glass layer 8 is provided on the glass base material 2 side, and a bonding metal layer 12 is provided on the silicon substrate 7 side of the IC chip 1. This is the point I made. Further, the bonding glass layer 8 has an electrode 1 for applying a voltage to the bonding glass layer 8.
It is placed on top of 3. This electrode 13 is made of a conductive material that has good adhesion to both the base material 2 and the bonding glass layer 8.
【００３４】この実施例のダイボンディングにおいても
前記実施例１と同様の作用効果が得られる。In the die bonding of this embodiment, the same effects as in the first embodiment can be obtained.
【００３５】なおこの実施例ではシリコン基板７に別途
、接合用金属層１２を設けたが、シリコン基板７自体を
接合用金属層１２として用いてもよい。In this embodiment, the bonding metal layer 12 is separately provided on the silicon substrate 7, but the silicon substrate 7 itself may be used as the bonding metal layer 12.
【００３６】（実施例３）この発明のダイボンディング
構造は、図３に示すように、ＩＣチップ１のチップ側電
極４と基材２の基材側電極３とをワイヤー６を用いて接
続するワイヤーボンド技術においても利用できる。(Embodiment 3) As shown in FIG. 3, the die bonding structure of the present invention connects the chip side electrode 4 of the IC chip 1 and the base material side electrode 3 of the base material 2 using a wire 6. It can also be used in wire bond technology.
【００３７】[0037]
【発明の効果】以上説明したように本発明のダイボンデ
ィング構造においては、ダイまたは基材の一方の少なく
とも表面が酸化物を形成し得る導体であり、他方の少な
くとも表面が酸化物であり、これらの表面が陽極接合さ
れてダイと基材を固定する接合部を形成しているので、
導体と酸化物との間は、金属−酸素間の化学結合によっ
て接合している。この陽極接合は接合処理時に接合界面
が液相になることがなく固相状態のままで行なわれるの
で、ダイと基材とを位置合わせした状態を維持して接合
処理できる。よってこのダイボンディング構造によれば
、ダイと基材を位置精度良く固定できる。As explained above, in the die bonding structure of the present invention, at least the surface of one of the die or the base material is a conductor capable of forming an oxide, and at least the surface of the other is a conductor capable of forming an oxide. The surface of the die is anodically bonded to form the joint that fixes the die and the substrate.
The conductor and the oxide are bonded by a metal-oxygen chemical bond. This anodic bonding is performed while the bonding interface does not become a liquid phase during the bonding process and remains in a solid state, so that the bonding process can be performed while maintaining the aligned state of the die and the base material. Therefore, according to this die bonding structure, the die and the base material can be fixed with high positional accuracy.
【００３８】また、接合部がダイの長さ方向の中央部の
みに設けられた請求項２のダイボンディング構造では、
接合部が狭くダイと基材との熱膨張の差による応力の発
生を小さく抑えることができる。加えて接合部を中央部
に設けたので、接合部からダイの端部までの最長距離が
短くなり、ダイと基材との熱膨張の差によるダイ側電極
と基材側電極の位置づれが最小となる。従って、このダ
イボンディング構造によれば、ダイと基材との位置合わ
せ精度を高く保ちつつ、熱応力も緩和できるので、ダイ
を長く形成してチップの実装数を減らし、作業性を向上
することが可能となる。Further, in the die bonding structure according to claim 2, the bonding portion is provided only at the central portion in the length direction of the die,
Since the joint is narrow, the generation of stress due to the difference in thermal expansion between the die and the base material can be suppressed. In addition, since the joint is located in the center, the longest distance from the joint to the edge of the die is shortened, which reduces the positional deviation between the die side electrode and the base material side electrode due to the difference in thermal expansion between the die and the base material. Minimum. Therefore, according to this die bonding structure, thermal stress can be alleviated while maintaining high alignment accuracy between the die and the base material, so it is possible to form a long die, reduce the number of chips mounted, and improve workability. becomes possible.
【００３９】請求項３のダイボンディング方法は、ダイ
または基材の一方を酸化可能な導体からなる基材あるい
は酸化可能な導体を成膜した基材とし、他方を酸化物か
らなる基材あるいは酸化物を成膜した基材とし、これら
を重ね合わせて酸化物側がマイナス、導体側がプラスと
なるように両者間に電圧を印加して陽極接合する方法な
ので、酸化物中のアルカリイオン等の可動イオンの移動
に伴い、酸化物と導体との間に大きな静電引力が生じる
と共に、界面の部分で酸化物中の酸素と導体との化学結
合が生じて酸化物と導体とを強固に接合することができ
る。しかもこの接合処理は酸化物と導体との界面が固相
の状態のままで行われ、接合界面が流動状態になること
はない。従ってこのダイボンディング方法によれば、ダ
イと基材を位置合わせした時の状態を保ったまま接合す
ることができ、これらを正確に固定できる。In the die bonding method of claim 3, one of the die and the base material is a base material made of an oxidizable conductor or a base material on which an oxidizable conductor is formed, and the other is a base material made of an oxide or a base material made of an oxidized conductor. This is a method of anodic bonding by using a base material on which a film has been formed, stacking them and applying a voltage between them so that the oxide side is negative and the conductor side is positive, so mobile ions such as alkali ions in the oxide As the oxide moves, a large electrostatic attraction is generated between the oxide and the conductor, and a chemical bond is generated between the oxygen in the oxide and the conductor at the interface, which firmly bonds the oxide and the conductor. Can be done. Moreover, this bonding process is performed while the interface between the oxide and the conductor remains in a solid state, and the bonding interface does not become fluid. Therefore, according to this die bonding method, it is possible to bond the die and the base material while maintaining their alignment, and it is possible to accurately fix them.
【図１】実施例１のダイボンディング構造を示すもので
、（ａ）は平面図、（ｂ）は（ａ）中Ｉ−Ｉ線に沿う断
面図。FIG. 1 shows a die bonding structure of Example 1, in which (a) is a plan view and (b) is a cross-sectional view taken along line II in (a).
【図２】実施例２のダイボンディング構造を示す断面図
。FIG. 2 is a cross-sectional view showing a die bonding structure of Example 2.
【図３】実施例３のダイボンディング構造を示すもので
、（ａ）は平面図、（ｂ）は断面図。FIG. 3 shows a die bonding structure of Example 3, in which (a) is a plan view and (b) is a cross-sectional view.
【図４】液晶表示パネルの画素ピッチＰｐとボンディン
グピチッチＰｂとの差によって生じる問題を説明するた
めの平面図。FIG. 4 is a plan view for explaining a problem caused by a difference between a pixel pitch Pp and a bonding pitch Pb of a liquid crystal display panel.
【図５】従来のダイボンディング構造で生じる問題を説
明するためのめ平面図。FIG. 5 is a plan view for explaining problems that occur in a conventional die bonding structure.
１ ＩＣチップ
２ 基材
３ 基材側電極
４ チップ側電極
５ バンプ
６ ワイヤー
７ シリコン基板
８ 接合用ガラス層
９ 表面側
１０ オーミックコンタクト用不純物拡散層１１
コンタクトパッド
１２ 接合用金属層
１３ 電極
１４ 接合部
１５ 封止剤1 IC chip 2 Base material 3 Base material side electrode 4 Chip side electrode 5 Bump 6 Wire 7 Silicon substrate 8 Bonding glass layer 9 Surface side 10 Impurity diffusion layer 11 for ohmic contact
Contact pad 12 Bonding metal layer 13 Electrode 14 Bonding portion 15 Sealant
Claims (3)
グ構造において、ダイまたは基材の一方の少なくとも表
面が酸化物を形成し得る導体であり、他方の少なくとも
表面が酸化物であり、これらの表面が陽極接合されてダ
イと基材を固定する接合部を形成していることを特徴と
するダイボンディング構造。Claim 1: In a die bonding structure for fixing a die to a base material, at least one surface of the die or the base material is a conductor capable of forming an oxide, and at least the surface of the other is an oxide, and these surfaces A die bonding structure characterized in that the two are anodically bonded to form a joint that fixes the die and the base material.
のみに設けられたことを特徴とする請求項１のダイボン
ディング構造。2. The die bonding structure according to claim 1, wherein the bonding portion is provided only at a central portion of the die in the length direction.
面が酸化物を形成し得る導体であり、他方の少なくとも
表面が酸化物であり、これらを重ね合わせて、酸化物側
がマイナス、導体側がプラスとなるように両者間に電圧
を印加して陽極接合することを特徴とするダイボンディ
ング方法。3. At least the surface of one of the die or the base material is a conductor capable of forming an oxide, and at least the surface of the other is an oxide, and these are stacked so that the oxide side is negative and the conductor side is positive. A die bonding method characterized by anodic bonding by applying a voltage between the two so as to achieve the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3087656A JP2831484B2 (en) | 1991-03-27 | 1991-03-27 | Die bonding structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3087656A JP2831484B2 (en) | 1991-03-27 | 1991-03-27 | Die bonding structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04299541A true JPH04299541A (en) | 1992-10-22 |
| JP2831484B2 JP2831484B2 (en) | 1998-12-02 |
Family
ID=13921003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3087656A Expired - Fee Related JP2831484B2 (en) | 1991-03-27 | 1991-03-27 | Die bonding structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2831484B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5900671A (en) * | 1994-07-12 | 1999-05-04 | Mitsubishi Denki Kabushiki Kaisha | Electronic component including conductor connected to electrode and anodically bonded to insulating coating |
| DE19525388B4 (en) * | 1994-07-12 | 2005-06-02 | Mitsubishi Denki K.K. | Electronic component with anodically bonded lead frame |
| DE19549750B4 (en) * | 1994-07-12 | 2005-07-14 | Mitsubishi Denki K.K. | Electronic component with anodisch gebontetem lead frame |
-
1991
- 1991-03-27 JP JP3087656A patent/JP2831484B2/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5900671A (en) * | 1994-07-12 | 1999-05-04 | Mitsubishi Denki Kabushiki Kaisha | Electronic component including conductor connected to electrode and anodically bonded to insulating coating |
| US6087201A (en) * | 1994-07-12 | 2000-07-11 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing ball grid array electronic component |
| US6133069A (en) * | 1994-07-12 | 2000-10-17 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing the electronic using the anode junction method |
| US6181009B1 (en) | 1994-07-12 | 2001-01-30 | Mitsubishi Denki Kabushiki Kaisha | Electronic component with a lead frame and insulating coating |
| US6268647B1 (en) | 1994-07-12 | 2001-07-31 | Mitsubishi Denki Kabushiki Kaisha | Electronic component with an insulating coating |
| US6310395B1 (en) | 1994-07-12 | 2001-10-30 | Mitsubishi Denki Kabushiki Kaisha | Electronic component with anodically bonded contact |
| DE19525388B4 (en) * | 1994-07-12 | 2005-06-02 | Mitsubishi Denki K.K. | Electronic component with anodically bonded lead frame |
| DE19549750B4 (en) * | 1994-07-12 | 2005-07-14 | Mitsubishi Denki K.K. | Electronic component with anodisch gebontetem lead frame |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2831484B2 (en) | 1998-12-02 |
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| LAPS | Cancellation because of no payment of annual fees |