JP2977338B2 - Semiconductor module - Google Patents

Abstract

PURPOSE:To provide the semiconductor module which can accurately hold the position relation between a semiconductor chip and other module constituent components and also supports the semiconductor chip mechanically tightly even when made into a thin film. CONSTITUTION:The semiconductor module where the semiconductor chip is mounted is equipped with an adhered substrate formed by connecting the surfaces of two semiconductor wafers 1 and 2 which have specific thickness and smooth surfaces, a recessed part 4 formed by etching part of the adhered substrate to depth reaching the connection part between the wafers 1 and 2, and the semiconductor chip mounted in the recessed part 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor module on which a semiconductor chip such as a laser is mounted, and more particularly to a semiconductor module which simplifies positioning of a semiconductor chip and other module components.

[0002]

2. Description of the Related Art Conventionally, a configuration as shown in FIG. 13 is known as an example of a semiconductor module having a semiconductor chip mounted thereon. In this module, the semiconductor laser chip 1
11 is soldered onto a copper stem 113 via a silicon submount 112, and a cap 114 with a lens is welded to the stem 113. In the cap 114,
An optical fiber 116 is welded through a suitable sleeve 115. Then, these are stored in a package together with necessary electronic components, and a semiconductor laser module is configured.

[0003] The laser chip 111 generates a large amount of heat during operation.
3 is used. However, since the compound semiconductor forming the semiconductor laser and the copper forming the stem have different coefficients of thermal expansion, a silicon submount 112 having an intermediate coefficient of thermal expansion is used to reduce the stress caused by the difference.

Here, in order to efficiently guide the light emitted from the laser chip 111 to the fiber 116, the optical axes of the laser chip 111, the lens, and the fiber 116 must be accurately aligned. That is, the positional relationship between these components must be set with high accuracy. However, usually, in order to reduce the manufacturing cost, the laser chip 111 and the lens are not connected with high accuracy and the optical axis is aligned at the time of connecting the fiber.

[0005] This optical axis alignment requires considerable time and effort even for a heat technician, and this step is the factor that most increases the manufacturing cost. When the laser chip 111 and the fiber 116 are in a one-to-one correspondence, it is relatively possible to cope with it. However, when the laser chip 111 and the fiber 116 are arrayed, it is difficult to cope with such a method.

As described above, a demand for mounting a semiconductor chip at an accurate position in a module is strong not only for an optical component chip such as a laser but also for a general electronic component chip. For example, in the flow of high density component mounting in recent years, surface mounting of components as shown in FIG. 14 is progressing, and a metal bump 123 is formed on a wiring 122 of a printed circuit board 121, and a chip 124 A so-called bump connection method or a flip chip mounting method for directly mounting the electrode 125 is often used. However, in these methods, chip 1
It is necessary to accurately align the positions of the 24 electrodes 125 and the metal bumps 123, and for example, it is necessary to perform the alignment with an accuracy of 10 μm.

On the other hand, in an IC card or the like where thinning is desired, as shown in FIG.
And a method of molding with a resin 133 by fitting into the hole of. However, this method has a problem that the mechanical strength is weak because only the resin 133 supports the chip 131.

[0008]

As described above, it is extremely important to mount a semiconductor chip at an accurate position in a module, and overcoming the difficulty is a major issue. In addition, the method of embedding a chip in a hole of a substrate and performing resin molding in order to reduce the thickness is problematic in that the mechanical strength is weak, and the necessity for increasing the mechanical strength is increasing.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to accurately maintain the positional relationship between a semiconductor chip and other module components and to reduce the film thickness. An object of the present invention is to provide a semiconductor module capable of mechanically and firmly supporting a semiconductor chip.

[0010]

The gist of the present invention is to use a submount (chip mounting component) provided with a concave portion and mount a chip in the concave portion, and in particular, to bond a plurality of wafers as a submount. The use of a substrate.

That is, according to the present invention, in a semiconductor module on which a semiconductor chip is mounted, an adhesive substrate formed by joining surfaces of a plurality of semiconductor wafers each having a predetermined thickness and a smooth surface, and a part of the adhesive substrate are provided. The semiconductor device is characterized by comprising a concave portion formed by etching to a depth reaching the bonding portion of the wafer, and a semiconductor chip mounted in the concave portion.

Here, it is preferable that the concave portion is formed so that the cross-sectional diameter of the middle portion is smaller than the cross-sectional diameter of the bottom portion. The cross section of the middle portion refers to the bottom or the surface in the concave portion parallel to the wafer surface, and refers to the average value of the diameter, the length of the diagonal line, and the like. In short, it is preferable that the position of the concave portion that is positioned in contact with the semiconductor chip is located near the middle part or near the entrance.

[0013]

When a concave portion is provided in a semiconductor wafer, the position in the horizontal direction can be accurately defined by using a normal mask alignment process. However, in the depth direction, it is difficult to accurately etch the depth and flatten the bottom surface in a normal etching process.

On the other hand, in the present invention, since the two wafers are joined via an oxide film or the like, the etching of the recess is automatically stopped at the oxide film. Therefore, if the thickness of the wafer by polishing is precisely controlled, it becomes easy to accurately etch the depth of the concave portion and flatten the bottom surface at an arbitrary position in the wafer surface. The use of the recess makes it possible to mount the semiconductor chip at an accurate position in both the horizontal and vertical directions.

Further, in the present invention, since the semiconductor chip is supported by at least one semiconductor wafer, it has high mechanical strength. Further, since it is easy to cut the wafer at a predetermined position as needed, by holding the wafer at a predetermined position in the module, the positional relationship with other module components can be accurately set.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments. FIG. 1 is a perspective view showing a main configuration of a semiconductor module according to a first embodiment of the present invention.

First, the two silicon wafers 1 and 2 are each polished to a predetermined thickness, for example, the wafer 1 is smoothed to 200 μm and the wafer 2 is smoothed to 250 μm, and the surface is directly oxidized through an oxide film 3 formed by thermal oxidation. Join. A method of directly bonding this silicon wafer via an oxide film is described in, for example, Japanese Patent Application Laid-Open Nos. 61-5544 and 61-42154.
This is described in detail in Japanese Patent Publication No.

Next, a concave portion 4 serving as a chip mounting portion is provided on the bonding substrate on which the two wafers 1 and 2 are bonded through a normal mask aligning step and an etching step. If the edge of the mask matches the crystal orientation of silicon, there is almost no lateral retreat of the etching. As described above, the etching in the depth direction automatically stops at the oxide film 3. Therefore, the size of the recess 4 is determined by the accuracy of the mask,
The depth is automatically determined by the thickness accuracy of the wafer, and any of them can be controlled with high accuracy.

Next, necessary electrode wirings 5 and the like are formed on one surface of the adhesive substrate, and the substrate is cut out to a predetermined size, so that module components (chip mounting substrate) 6 are cut out.
Is completed.

FIG. 2 shows a method of using this module component 6 as a submount of a semiconductor laser module.
And FIG. Although FIG. 3 is based on the case where four lasers and fibers are arrayed, the same applies to a single laser and an array of other numbers.

First, before cutting out as a part, the oxide film 3 exposed on the bottom surface of the concave portion 4 is removed with hydrofluoric acid or the like.
The bottom surface of the recess 4 is metallized with a solder material (for example, AuSn), and the back surface of the wafer is metallized with, for example, AuCr.

Next, as shown in FIG. 2A, the adhesive substrate is cut into a size of, for example, 3.9 mm × 6.0 mm at a predetermined position. Then, a laser chip 7 polished to a predetermined thickness, for example, 100 μm, is mounted on the bottom surface of the recess 4. Here, if the size of the concave portion 4 is previously adjusted to the size of the laser chip 7 and mounted so that the edge of the concave portion 4 and the edge of the chip 7 are aligned or parallel, the arrangement of the laser chip 7 is also improved. Determined exactly. Thereafter, the laser chip 7 may be fixed by soldering or the like by a process such as heat treatment.

Usually, since the laser chip alone is very small, there are considerable restrictions on handling such as the end face of the active layer cannot be held with tweezers and the degree of freedom of electrode wiring is small. However, if the chip is mounted in a sub-mount chip shape as in this embodiment, the required electrode wiring is completed in addition to the chip alone, and the degree of freedom in handling and mounting wiring is increased. There is also an advantage. The Si wafer is not only a tool for positioning, but also as shown in FIG. 2B, if an IC element 150 or the like is formed in the Si wafer to form a hybrid IC, the size of the entire module can be reduced, and at the same time, the electrodes can be reduced. Wiring can be reduced to a minimum, which is particularly advantageous during high-speed operation.

Next, the coupling from the submount to the optical fiber will be described. In recent years, a ribbon fiber connector called a so-called MT connector is commercially available as a tool for connecting a ribbon fiber in which a plurality of optical fibers are bundled. As shown in FIG. 16, the two connectors 143 are connected via two pins 141, and a ribbon fiber inserted from the rear surface of the connector 143 is inserted between the pin insertion portions on the front surface of the connector 143. 145 is arranged with high accuracy. And
The front faces of the two connectors 143 are abutted against each other and stopped by the clip 144, whereby the two ribbon fibers 1
45 is easily connected. Using this MT connector, the positional relationship between the laser chip mounted on the submount described above and the optical fiber as another module component can be accurately maintained.
This is shown in FIG. (A) is a block diagram, (b) is a sectional view of the assembled state.

First, the sub mount 6 is connected to the MT connector 14
The copper base 8 is cut out in accordance with the interval (for example, 3.9 mm) between the three pins 141 and mounted in parallel with the front edge 8a of the copper base 8 or lowered several tens of μm from the front edge 8a. In this mount, In is vapor-deposited on the metallization on the lower surface of the submount 6 in advance, and 200 mm is applied under an appropriate pressure.
The temperature may be raised to about ° C. Naturally, the laser chip 7 is arranged at the center of the front edge of the submount 6.

The pin 141 of the MT connector 143 is fitted so as to sandwich the submount 6, and the pin 141 is pressed down from above by a suitable lid 9. The cover 9 may be held down, for example, by screwing it to the base 8. Pin 14
The thickness of 1 is generally 700 μm in diameter. If the thickness of the submount 6 is set to 450 μm, the lid 9 does not contact the submount 6 and the pin 141 can be securely pressed down. Further, the thickness of the laser chip 7 is set to 1
If the thickness of the bottom of the submount is set to 00 μm and the thickness of the bottom of the submount is set to 250 μm, the active layer of the laser coincides with the height of the center of the pin 141, that is, the height of the center of the fiber end face 142. Can be opposed.

The clip 144 can be used to press the MT connector 143 against the base 8 in the horizontal direction. That is, if the length of the lid 9 is the same as that of the MT connector 143, it is only necessary to fit the clip 144.
Also, an appropriate step is provided at the rear of the base 8 so that the holder plate 1
By inserting the “0” and holding the holder plate 10 together with the clip 144, the pressing can be performed more reliably.

As shown in FIG. 4, the cover 9a is provided with a width equal to the outer space of the guide pin 141.
With a structure having a groove having a depth equal to the diameter of the guide pin 141, not only the fixing in the vertical direction but also the displacement of the guide pin 141 in the horizontal direction can be prevented and the positioning can be fixed.

Further, as shown in FIG. 5, a lid 9b having a groove having a width equal to the outer space between the guide pins 141 of the connector 143 and a depth equal to the diameter of the guide pins 141.
In this case, if the groove is further provided with a groove having a predetermined width and depth, a predetermined electronic component or the like can be mounted on the surface of the submount 6.

To summarize the above mechanism, the pin 141 is pinched by the submount 6 in the horizontal direction, and the pin 141 is pinched by the lid 9 and the base 8 in the vertical direction.
In the front-rear direction, the clip 144
The T connector 143 is securely held at an accurate position with respect to the submount 6. Further, the laser chip 7 is accurately positioned on the submount 6 as described above. Therefore, the positional relationship between the laser chip 7 and the end face 142 of the fiber is accurately maintained.

After assembling these packages, Y
Welding and fixing of each part using AG laser welding,
It is also possible to apply an application such as performing hermetic sealing by soldering or welding by using a full-surface lid having a glass window between the semiconductor chip and the MT connector.

Although an example in which the laser chip and the fiber are modularized has been described above, not only the laser but also other optical elements such as a photodiode (PD), a lens,
Obviously, an isolator and the like can be modularized by the present invention. Further, not only the optical element but also the electronic element can be firmly arranged at an accurate position in the module. An example is shown in FIG.

FIG. 6 is a cross-sectional view showing a main configuration of a semiconductor module according to the second embodiment. As shown in FIG. 6A, silicon wafers 1 and
The electrode wiring 5 is formed on the adhesive substrate 41 on which
Several recesses 4 are provided. In some cases, the electronic elements 42 such as FETs may be formed on the wafer 1. Then, the electronic element chip 43 is mounted in the concave portion 4 as before. The oxide film 3 exposed at the bottom of the concave portion becomes an electrical insulating film between the wafer 2 and the chip 43 if left as it is, and if this is removed, it can be used as a part of a wiring to a ground or the like.

The electric connection on the upper surface of the chip may be performed by wire bonding or TAB connection. In this embodiment, the TAB connection is more suitable. That is, each electronic element is mounted at an accurate position in the adhesive substrate 41,
This is because batch connection is possible, so that the process can be simplified. In this case, it is better to make the height of the electronic element chip 43 and the depth of the recess 4 uniform, so that the effect of the present invention, in which accurate control of the depth of the recess is easy, can be sufficiently utilized.

When a plurality of elements to be mounted have different heights, a plurality of silicon wafers are bonded together as shown in FIG. 6B to form recesses 4 ₁ , 4 having different depths.
It is also possible to form the _2, 4 _3. FIG.
As shown in (c), the concave portions 4 ₄ ,
4 _5, 4 _6, 4 if ₇ is provided, it is possible to firmly mount by a simple process elements from both sides, has the characteristics of high more effective for high-density mounting of the device.

In the above-described embodiments, the example in which the positioning of the semiconductor chip and the like is performed at the bottom of the concave portion 4 has been described. However, the positioning may be performed at the middle of the concave portion.
The fixing material (solder material, conductive paste, resin) that fixes the positioning target such as a semiconductor chip needs to be adapted to the target in a liquid or semi-fixed state before curing.
At this time, the position of the fixing target may fluctuate due to the surface tension of the fixing material. In the above-described example in which positioning is performed at the bottom of the concave portion 4, the influence of the surface tension of the fixing material tends to appear, and inclination and displacement of the fixing target due to aggregation of the fixing material and the like are often seen. Therefore, in order to more reliably position the semiconductor chip and the like, it is desirable that the bottom portion of the concave portion 4 and the contact portion for positioning have a certain level difference, and the concave portion has a double level difference hereinafter.
An embodiment of a positioning mechanism in which a bottom and a contact portion for positioning have a certain level difference will be described.

FIGS. 7 (a) and 7 (b) are views for explaining a main configuration of a semiconductor module according to the third embodiment. FIG. 7 (a) is a plan view and FIG. 7 (b) is a sectional view taken along the line AA 'of FIG. Is shown. As described above, this is an embodiment in which the positioning recess has a double step, and only the vicinity of the recess in the embodiments up to FIG. 6 is shown.

In this embodiment, the Si substrates 51, 53, 5
6 is directly bonded via the SiO ₂ films 52 and 54, and in particular, the uppermost Si substrate 56 on which the Si ₃ N ₄ film 55 is deposited is used. According to the embodiments shown in FIGS. 6A and 6B, for example, 51 is 250
μm, 53 at 10 μm, 56 at 190 μm, SiO 2
₂ is 1 μm for both 52 and 54, and 0.2 μm for Si ₃ N ₄ 55
m, and these substrates can be formed by combining processes such as thermal oxidation, direct bonding, polishing, and CVD.

Thereafter, as in the embodiment described above by ordinary photolithography, the uppermost Si substrate 5 is formed.
6 is etched. As the crystal orientation of Si,
For example, 51, 53, and 56 are respectively adhered on the {100} surface, and the mask patterns are formed so as to be in <011> and <01-1> directions. The etching may be performed by anisotropic chemical etching using a KOH aqueous solution or the like. As a result, the exposed Si ₃ N ₄ film 55 is removed by ion milling, dry etching or the like, and then the Si ₃ N ₄ film 55 is removed.
The SiO ₂ film 54 sandwiched between the silicon substrate 53 and the Si substrate 53 is subjected to selective side etching of, for example, 10 μm using an aqueous solution of ammonium fluoride or the like.

Thereafter, by performing the anisotropic chemical etching of Si again, a concave portion having a double step as shown in FIG. 7B can be formed, and the semiconductor chip 57 can be effectively positioned. become able to. Further, in this example, since the pattern of the Si substrate 56 and the pattern of the Si substrate 53 can be formed in a self-aligned manner (self-alignment), there is no misalignment between the two, and there is no problem caused by forming a double step. .

The double step shown in FIG. 7 can be formed not only by side etching but also by utilizing the crystal anisotropy of Si as shown in FIG. In FIG. 8,
(A) is a plan view, and (b) is a sectional view taken along the line BB 'of (a). In the fourth embodiment, the Si substrate 61,
The substrates 63 and 65 are directly bonded only via the SiO ₂ films 62 and 64, and at this time, the Si substrate 63 and the Si substrate 65 are directly bonded by changing the crystal plane or the crystal orientation. Specifically, the Si substrate 63 on the Si substrate 61 (arbitrary crystal orientation) is bonded on the {110} surface, and the Si substrate 65 is bonded on the {100} surface. Further, the <001> direction of the Si substrate 63 and S
The <011> direction of the i-substrate 65 is aligned.

<01>
A mask pattern is formed along the <1> and <01-1> directions, and anisotropic chemical etching of Si is performed as in the case of FIG. Next, the exposed portion of the SiO ₂ film 64 is removed by etching, and subsequently, anisotropic chemical etching of Si is performed again. As a result, a geometrical {111} crystal plane corresponding to the shape of the mask appears in each Si crystal. Particularly, the middle part of the Si substrate 63 has a rhombus or parallelogram having an inscribed pattern as a mask, such as 63 '. Etched into shape. This diamond or parallelogram pattern
By setting the thickness of the Si substrate 63 appropriately, it is possible to make most of the side surfaces vertical.

This will be described with reference to FIG. FIG. 9 shows only a square pattern (solid line) and an etching pattern (dashed line) serving as a mask, and the left and lower figures show cross sections on a diagonal line of a rhombus corresponding to the same direction. Reference numeral 71 denotes an opening for positioning, that is, a positioning pattern of a semiconductor chip or the like; 72, a region where the bottom SiO ₂ film 62 is exposed in an etched region (a boundary side surface is a vertical surface) of the Si substrate 63; Is a region where the bottom SiO ₂ film 62 is not exposed.

The region 73 has an oblique surface as shown in the left diagram of FIG. 9, which is the same {111} plane (equivalent to the (111) plane) as the vertical plane of the diamond-shaped boundary. This 73
Is further extended if the Si substrate 63 is sufficiently thick. Here, the amount of extension (depth) is increased by the SiO ₂ film 62.
Is stopped at a position as shown in the figure. When the region 73 is extended to the opening 71, the bottom of the opening 71 is not a flat surface, so that the original purpose cannot be achieved. Therefore, it is necessary to perform these designs in consideration of the relationship between the size of the opening 71, the thickness of the Si substrate 63, and the size of the inclined surface 73.

An example of this design example is shown. For simplicity,
The opening 71 serving as a mask is a square having a side of a, and the diagonal of the diamond in the vertical direction in FIG. 9 is the <001> direction of the Si substrate 63. Further, the thickness of the Si substrate 63 is set to D
And b, c, and d are defined as shown in FIG. in this case,
Other values can be calculated using a and D as parameters. That is, b = a / 2 ^1/2 , C = a / 2 ^3/2 , D = D × 2 ^1/2
Where d is smaller than b (d <b), D <a /
It suffices to satisfy 2.

Therefore, in the case of FIG. 9, there is no problem if the thickness of the Si substrate 63 is set to be equal to or less than 1/2 of the mask width of the substrate 63 in the <001> direction. Also, in general, when the direction of the opening serving as a mask is shifted from the <001> direction of the Si substrate 63 (when the crystal directions in which the Si substrate 63 and the Si substrate 65 are bonded are shifted), FIG.
0, and even in this case, the Si substrate 63
Can be similarly defined. As an example, FIG.
In the cases of (b) and (c) of 0, if the opening of the mask is a square with one side a, there is no problem if the thickness of D is 20% or less of a.

As in the embodiment shown in FIG. 8, an opening having a double step can be formed even on an adhesive substrate using another crystal plane. This is shown in FIG. In FIG. 11,
(A) is a plan view, and (b) is a cross-sectional view taken along the line CC ′ of (a). In the fifth embodiment, as in FIG. 8, the Si substrates 91, 93 and 95 are directly bonded only through the SiO ₂ films 92 and 94.
Both the i-substrate 93 and the Si substrate 95 have {100} faces, and the <011> direction of the Si substrate 93 and the Si substrate 95
Are bonded such that the <011> direction is shifted, for example, 45 °. As in the case of FIG. 8, a mask pattern along the <011> and <01-1> directions is formed on the surface of the Si substrate 95 using this adhesive substrate, and anisotropic chemical etching of Si and the exposed SiO ₂ film are performed. 94 is removed by etching, followed by anisotropic chemical etching of Si.

As a result, the respective Si substrates 93, 95
A geometrical {111} crystal plane conforming to the shape of the mask appears. In particular, the middle part of the Si substrate 93 is etched into a square or rectangle inscribed with the mask pattern like 93 '. This square or rectangular pattern has a {111} side surface, and there is a problem that a corner portion of the square or rectangular mask opening does not become a flat bottom surface. However, even in such a case, the purpose can be achieved by using the deformed mask, and application as a holder for the lens 97 as shown in FIG. 11 is possible.

Further, such a double step can be applied to a surface input / output type semiconductor module as shown in FIG. In the sixth embodiment, Si substrates 93 and 95 are directly bonded via an SiO ₂ film 94,
5 are both {100} faces, and the <0
The bonding is performed so that the <11> direction and the <011> direction of the Si substrate 95 are shifted, for example, 45 °. In addition, Si
On the back surface of the substrate 93, a protection mask such as SiO ₂ is provided. As in the case of FIG. 8, a mask pattern along the <011> and <01-1> directions is formed on the surface of the Si substrate 95 using this adhesive substrate, and anisotropic chemical etching of Si and the exposed SiO ₂ film are performed. 94, followed by Si
Is performed by anisotropic chemical etching.

As a result, the respective Si substrates 93, 95
A geometrical {111} crystal plane conforming to the shape of the mask appears. In particular, a pattern serving as a mask is etched into a square or a rectangle inscribed like 93 ′ at an intermediate portion of the Si substrate 93. Thereafter, the protective mask on the back surface of the Si substrate 93 is removed, and a surface input / output type semiconductor element (semiconductor laser, light emitting diode, photodiode, etc.) 101 and a lens 97 'are mounted and electrically connected.

The present invention is not limited to the above embodiment. For example, the wafers to be bonded are not limited to Si, but Si and Ge, GaAs, In.
Various combinations such as P and InSb are conceivable. Further, the wafer to be bonded is not limited to a semiconductor material, and a dielectric substrate or the like can be used. For example, a ceramic material such as Al ₂ O ₃ , AlN, C-BN, SiC, or a polyimide material may be used. Polymer materials can also be used. Furthermore, when different kinds of wafers are bonded, or even between wafers of the same kind, the etching is automatically determined by the bonding surface without interposing an oxide film by interposing a modified layer by changing the crystal orientation or the like. It is possible. In addition, not only the optical element and the electronic element mounted on the concave portion, but also a fiber, a pin, a screw, or the like can be fitted and aligned. In addition, various modifications can be made without departing from the scope of the present invention.

[0052]

As described above in detail, according to the present invention, a concave portion reaching a wafer bonding portion is provided on an adhesive substrate to which a plurality of wafers are directly bonded, and a semiconductor chip is mounted in the concave portion. The positional relationship between the semiconductor chip and other module components can be accurately maintained, and the semiconductor chip can be mechanically and firmly supported.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a configuration of a main part of a semiconductor module according to a first embodiment of the present invention;

FIG. 2 is a perspective view showing an application example of a laser module to a submount.

FIG. 3 is an exploded perspective view and a sectional view showing an application example to a laser module using an MT connector;

FIG. 4 is an exploded perspective view showing a modification of FIG. 3;

FIG. 5 is an exploded perspective view showing a modification of FIG. 3;

FIG. 6 is a sectional view showing a configuration of a main part of a semiconductor module according to a second embodiment;

FIGS. 7A and 7B are a plan view and a cross-sectional view illustrating a main part configuration of a semiconductor module according to a third embodiment;

FIGS. 8A and 8B are a plan view and a cross-sectional view illustrating a configuration of a main part of a semiconductor module according to a fourth embodiment;

FIG. 9 is a schematic diagram for explaining the operation of the fourth embodiment;

FIG. 10 is a schematic view showing a case where a crystal direction of a wafer to be bonded is shifted;

FIG. 11 is a cross-sectional view illustrating a configuration of a main part of a lens holder according to a fifth embodiment;

FIG. 12 is a sectional view showing a configuration of a main part of a semiconductor module according to a sixth embodiment;

FIG. 13 is an exploded perspective view showing an example of a conventional laser module.

FIG. 14 is a cross-sectional view for explaining a conventional surface mounting method.

FIG. 15 is a cross-sectional view for explaining a method of molding an element in a conventional IC card.

FIG. 16 is a perspective view showing a configuration example of an MT connector.

[Explanation of symbols]

 1, 2, silicon wafer, 3, oxide film, 4, recess, 5 electrode wiring, 6 module component (chip mounting board), 7 laser chip, 8 base, 9 lid, 10 holder plate 41, an adhesive substrate, 42, an electronic element, 43, an electronic element chip, 141, a pin, 142, a fiber end face, 143, a connector, 144, a clip, 145, an optical fiber.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Fumihiko Shimizu 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Komukai Plant of Toshiba Corporation (56) References JP-A-61-5544 (JP, A) JP-A-57-118685 (JP, A) JP-A-61-42154 (JP, A) JP-A-62-162860 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) G02B 6 / 12-6/138 G02B 6/26-6/43 H01L 23/12

Claims (4)

(57) [Claims] An adhesive substrate formed by bonding surfaces of a plurality of semiconductor wafers having a predetermined thickness and a smooth surface, and a part of the adhesive substrate is etched to a depth reaching a bonding portion of the wafer. A semiconductor module comprising: a formed recess; and a semiconductor chip mounted in the recess. 2. An adhesive substrate formed by joining surfaces of a plurality of semiconductor wafers having a predetermined thickness and a smooth surface, and a part of the adhesive substrate is etched to a depth reaching a joint of the wafer. A semiconductor module comprising: a concave portion formed such that a cross-sectional diameter of a top portion or a middle portion is smaller than a cross-sectional diameter of a bottom portion; and a semiconductor chip mounted in the concave portion. 3. An adhesive substrate obtained by laminating at least three semiconductor wafers having a predetermined thickness and a smooth surface by directly bonding the surfaces of the wafers to each other, and joining a part of the adhesive substrate to a bonding portion of the wafer. And a recess formed so that the cross-sectional diameter of the middle part is smaller than the cross-sectional diameter of the bottom part, and the semiconductor chip mounted in this concave part. A semiconductor module comprising: 4. A connector having a predetermined guide pin or capable of being held by the guide pin is cut out in accordance with the guide pin and its interval and positioned by a chip mounting board having a semiconductor chip at a predetermined position. A semiconductor module characterized by being made.