JPH0566330A - Semiconductor module - Google Patents

Abstract

PURPOSE:To provide the semiconductor module which can accurately hold the position relation between a semiconductor chip and other module constituent components and also supports the semiconductor chip mechanically tightly even when made into a thin film. CONSTITUTION:The semiconductor module where the semiconductor chip is mounted is equipped with an adhered substrate formed by connecting the surfaces of two semiconductor wafers 1 and 2 which have specific thickness and smooth surfaces, a recessed part 4 formed by etching part of the adhered substrate to depth reaching the connection part between the wafers 1 and 2, and the semiconductor chip mounted in the recessed part 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor module on which a semiconductor chip such as a laser is mounted, and more particularly to a semiconductor module in which positioning of the semiconductor chip and other module components is simplified.

[0002]

2. Description of the Related Art Conventionally, a configuration shown in FIG. 13 is known as an example of a semiconductor module having a semiconductor chip mounted thereon. In this module, the semiconductor laser chip 1
11 is soldered onto a copper stem 113 via a silicon submount 112, and a lens cap 114 is welded to the stem 113. The cap 114 has
The optical fiber 116 is welded through a suitable sleeve 115. Then, these are packaged together with necessary electronic components in a package to form a semiconductor laser module.

Since the laser chip 111 generates a large amount of heat during operation, the stem 11 made of copper is used to improve heat dissipation.
3 is used. However, since the compound semiconductor forming the semiconductor laser and the copper forming the stem have different coefficients of thermal expansion, the silicon submount 112 having an intermediate coefficient of thermal expansion is used in order to reduce the stress due to the difference.

Here, in order to efficiently guide the light emitted from the laser chip 111 to the fiber 116, the optical axes of the laser chip 111, the lens and the fiber 116 must be aligned accurately. That is, the positional relationship between these parts must be set with high accuracy. However, normally, in order to reduce the manufacturing cost, the laser chip 111 and the lens are not so accurately connected to each other, and the optical axes are aligned at the time of fiber connection.

This optical axis alignment requires a considerable amount of time and labor even for a heat technician, and this process is the factor that raises the manufacturing cost most. When the laser chip 111 and the fiber 116 are in a one-to-one correspondence, it can be dealt with comparatively, but when the laser chip 111 and the fiber 116 are arrayed, it is difficult to deal with such a method.

As described above, the demand for mounting a semiconductor chip at an accurate position in a module is strong not only for optical component chips such as lasers but also for general electronic component chips. For example, in the recent trend of increasing the density of component mounting, the surface mounting of components as shown in FIG. 14 is progressing, and metal bumps 123 are formed on the wirings 122 of the printed board 121, and the chips 124 are formed on the metal bumps 123. A so-called bump connection method or a flip chip mounting method for directly mounting the electrode 125 is often used. However, with these methods, chip 1
It is necessary to accurately align the positions of the electrode 125 of 24 and the metal bump 123, and for example, the alignment of 10 μm accuracy must be performed.

Further, in an IC card or the like which is desired to be made thinner, as shown in FIG.
There is also a method in which the resin 133 is fitted into the hole and is molded with the resin 133. However, this method has a problem that the mechanical strength is weak because only the resin 133 supports the chip 131.

[0008]

As described above, it is extremely important to mount a semiconductor chip at an accurate position in a module, and it is a major problem to overcome the difficulty. Further, in a method of embedding a chip in a hole of a substrate for resin-molding in order to reduce the thickness, there is a problem that mechanical strength is weak, and it is becoming more and more necessary to increase mechanical strength.

The present invention has been made in consideration of the above circumstances, and an object thereof is to accurately maintain the positional relationship between a semiconductor chip and other module components and to reduce the thickness. An object of the present invention is to provide a semiconductor module that can mechanically and firmly support a semiconductor chip.

[0010]

The essence of the present invention resides in that a submount (chip mounting component) having a recess is used and a chip is mounted in the recess. In particular, a plurality of wafers are bonded as a submount. The use of a substrate.

That is, according to the present invention, in a semiconductor module having a semiconductor chip mounted thereon, an adhesive substrate formed by joining the surfaces of a plurality of semiconductor wafers having a predetermined thickness and smooth surfaces to each other, and a part of the adhesive substrate are provided. It is characterized by comprising a recess formed by etching to a depth reaching the bonded portion of the wafer and a semiconductor chip mounted in the recess.

Here, it is preferable that the recess is formed so that the cross-sectional diameter of the middle abdomen is smaller than the cross-sectional diameter of the bottom. The cross section of the middle abdomen means the bottom or the surface in the recess parallel to the wafer surface, and means the average value of the diameter, the length of the diagonal line, and the like. In short, it is preferable that the concave portion is located at a position where the concave portion comes into contact with the semiconductor chip and is positioned near the middle abdomen or the entrance.

[0013]

When a concave portion is provided in a semiconductor wafer, a normal mask alignment process is used to accurately define its horizontal position. However, in the depth direction, it is difficult to etch the depth accurately and to flatten the bottom surface by a normal etching process.

On the other hand, in the present invention, since the two wafers are bonded together via the oxide film or the like, the etching of the recess is automatically stopped by the oxide film. Therefore, if the thickness of the wafer by polishing is precisely controlled, it becomes easy to accurately etch the depth of the recess and flatten the bottom surface at an arbitrary position within the wafer surface. Then, by utilizing this concave portion, it becomes possible to mount the semiconductor chip at an accurate position in both the horizontal and vertical directions.

Further, in the present invention, since the semiconductor chip is supported by at least one semiconductor wafer, the mechanical strength is high. Further, since it is easy to cut the wafer at a predetermined position if necessary, by holding this wafer at a predetermined position in the module, the positional relationship with other module components can be set accurately.

[0016]

The details of the present invention will be described below with reference to the illustrated embodiments. FIG. 1 is a perspective view showing a main configuration of a semiconductor module according to a first embodiment of the present invention.

First, the two silicon wafers 1 and 2 are each smooth-polished to a predetermined thickness, for example, the wafer 1 to 200 μm and the wafer 2 to 250 μm, and the surfaces are directly oxidized through the oxide film 3 formed by thermal oxidation. To join. A method for directly bonding the silicon wafer via an oxide film is described in, for example, Japanese Patent Laid-Open Nos. 61-5544 and 61-42154.
It is described in detail in the official gazette.

Then, a concave portion 4 to be a chip mounting portion is provided on the adhesive substrate to which the above-mentioned two wafers 1 and 2 are adhered, through a normal mask aligning process and etching process. If the edge of the mask is aligned with the crystal orientation of silicon, there is almost no lateral retreat of etching. Further, as described above, the etching in the depth direction automatically stops at the oxide film 3. Therefore, the size of the recess 4 is determined by the accuracy of the mask,
The depth is automatically determined by the thickness accuracy of the wafer, and any of them can be controlled with high accuracy.

Next, necessary electrode wirings 5 and the like are formed on one surface of the adhesive substrate, and the substrate is cut into a predetermined size to form a module component (chip mounting substrate) 6
Is completed.

A method of using this module component 6 as a submount of a semiconductor laser module is shown in FIG.
And shown in FIG. In FIG. 3, an array of four lasers and fibers is kept in mind, but the same applies to one array and other arrays.

First, before cutting out as a component, the oxide film 3 exposed on the bottom surface of the recess 4 is removed with hydrofluoric acid or the like,
The bottom surface of the concave portion 4 is metallized with a solder material (for example, AuSn), and the back surface of the wafer is metalized with, for example, AuCr.

Next, as shown in FIG. 2 (a), the adhesive substrate is cut out at a predetermined position into a size of, for example, 3.9 mm × 6.0 mm. Then, the laser chip 7 polished to a predetermined thickness, for example 100 μm, is mounted on the bottom surface of the recess 4. Here, if the size of the recess 4 is adjusted to the size of the laser chip 7 in advance and the mount of the recess 4 and the edge of the chip 7 are aligned or parallel to each other, the laser chip 7 can be arranged. Accurately determined. After that, soldering of the laser chip 7 or the like may be performed by a process such as heat treatment.

Usually, since the laser chip itself is minute, the end face of the active layer cannot be held with tweezers, the degree of freedom of electrode wiring is small, and the handling is considerably restricted. However, if the chip is mounted in the form of a submount chip as in this embodiment, the electrode wiring required in addition to being larger than the chip alone is also completed, and the degree of freedom in handling and mounting wiring is also increased. There is also an advantage. The Si wafer is not only a tool for alignment, but if the IC element 150 or the like is formed in the Si wafer to form a hybrid IC as shown in FIG. Wiring can also be shortened to a minimum, which is particularly advantageous during high-speed operation.

Next, the coupling from the submount to the optical fiber will be described. In recent years, a ribbon fiber connector called a so-called MT connector is commercially available as a tool for connecting a ribbon fiber formed by bundling a plurality of optical fibers. As shown in FIG. 16, this is to connect two connectors 143 via two pins 141, and between the pin insertion portions on the front surface of the connector 143, a ribbon fiber inserted from the rear surface of the connector 143. The end surface 142 of 145 is accurately arranged. And
By connecting the front faces of the two connectors 143 to each other and fixing them with a clip 144, the two ribbon fibers 1
45 is easily connected. By using this MT connector, it is possible to accurately maintain the positional relationship between the laser chip mounted on the submount described above and the optical fiber that is another module component.
The situation is shown in FIG. (A) is a block diagram and (b) is a sectional view of the assembled state.

First, the submount 6 is attached to the MT connector 14
It is cut out according to the interval (for example, 3.9 mm) between the three pins 141, and is mounted in parallel with the front edge 8a of the copper base 8 or with the front edge 8a lowered by several tens of μm. In this mount, In was vapor-deposited on the metallization of the lower surface of the submount 6 in advance, and the pressure was adjusted to 200 after applying appropriate pressure.
The temperature may be raised to about ° C. Naturally, the laser chip 7 is arranged at the center of the front edge of the submount 6.

The pin 141 of the MT connector 143 is fitted so as to sandwich the submount 6, and the pin 141 is pressed down from above with a suitable lid 9. The lid 9 may be pressed down by screwing it to the base 8, for example. Pin 14
The thickness of 1 is generally 700 μm in diameter, and if the thickness of the submount 6 is 450 μm, the lid 9 does not contact the submount 6 and the pin 141 can be surely pressed down. Further, the thickness of the laser chip 7 is set to 1
If the thickness of the bottom of the submount is set to 00 μm and the thickness of the bottom of the submount is set to 250 μm, the active layer of the laser coincides with the height of the center of the pin 141, that is, the height of the center of the fiber end face 142. Can be made to face each other.

The above-mentioned clip 144 can be used for the force of pushing the MT connector 143 horizontally to the base 8. That is, if the length of the lid 9 is the same as that of the MT connector 143, it is only necessary to fit the clip 144.
In addition, an appropriate step is also provided on the rear part of the base 8 so that the holder plate 1
If 0 is inserted and the holder plate 10 is sandwiched by the clips 144, the holder plate 10 can be more reliably pressed.

Further, as shown in FIG. 4, the lid 9a has a width equal to the outer spacing of the guide pins 141.
With a structure having a groove having a depth equal to the diameter of the guide pin 141, not only the vertical fixing but also the lateral fixing of the guide pin 141 can be prevented and the alignment can be fixed.

Furthermore, as shown in FIG. 5, a lid 9b having a groove having a width equal to the outer spacing of the guide pins 141 of the connector 143 and a depth equal to the diameter of the guide pins 141.
In the above, if the groove is further provided with a groove having a predetermined width and a predetermined depth, a predetermined electronic component or the like can be mounted on the surface of the submount 6.

To summarize the above mechanism, the pin 141 is sandwiched laterally, and the pin 141 is sandwiched vertically by the lid 9 and the base 8.
In addition, by sandwiching the clip 144 in the front-back direction, M
The T connector 143 is securely held in the correct position with respect to the submount 6. Further, the laser chip 7 is accurately positioned on the submount 6 as described above. Therefore, the positional relationship between the laser chip 7 and the end surface 142 of the fiber is maintained accurately.

After assembling these mounting bodies, Y
We weld and fix each part using AG laser welding,
It is also possible to use a full-face lid having a glass window between the semiconductor chip and the MT connector to perform airtight sealing by soldering or welding.

Although an example in which the laser chip and the fiber are modularized is given here, not only the laser but also other optical elements such as a photodiode (PD), a lens,
Obviously, isolators and the like can also be modularized by the present invention. Further, not only the optical element but also the electronic element can be firmly arranged at a correct position in the module. An example thereof is shown in FIG.

FIG. 6 is a sectional view showing the structure of the main part of a semiconductor module according to the second embodiment. As shown in FIG. 6A, the silicon wafer 1,
The electrode wiring 5 is formed on the adhesive substrate 41 in which the two are bonded together,
Several recesses 4 are provided. In some cases, the electronic element 42 such as FET may be formed on the wafer 1 as well. Then, as before, the electronic element chip 43 is mounted in the recess 4. If the oxide film 3 exposed on the bottom surface of the recess is left as it is, it serves as an electrical insulating film between the wafer 2 and the chip 43, and if it is removed, it can be used as a part of wiring to the ground or the like.

Wire bonding, TAB connection or the like may be used for electrical connection on the upper surface of the chip, but TAB connection is more suitable for this embodiment. That is, each electronic element is mounted at an accurate position in the adhesive substrate 41,
This is because the wires can be collectively connected and the process can be simplified easily. In this case, it is better to make the height of the electronic element chip 43 and the depth of the recess 4 uniform, so that the effect of the present invention that the accurate control of the depth of the recess is easy can be fully utilized.

When the heights of the plurality of elements to be mounted are different, a plurality of silicon wafers are attached to each other as shown in FIG. 6B to form recesses 4 ₁ and 4 having different depths.
It is also possible to form ₂ , 4 ₃ . In addition, FIG.
As shown in (c), the recesses 4 ₄ ,
4 _5, 4 _6, 4 if ₇ is provided, it is possible to firmly mount by a simple process elements from both sides, has the characteristics of high more effective for high-density mounting of the device.

In the above-described embodiments, the semiconductor chip or the like is positioned at the bottom of the recess 4 by way of example, but it may be positioned at the middle of the recess.
A fixing material (solder material, conductive paste, resin) for fixing a positioning object such as a semiconductor chip needs to be adapted to the object in a liquid or semi-fixed state before hardening.
At this time, the position of the fixed object may change due to the surface tension of the fixing material. In the example in which the positioning is performed at the bottom of the concave portion 4 as described above, the influence of the surface tension of the fixing material is likely to appear, and tilting or positional deviation of the fixing target due to aggregation of the fixing material is often seen. Therefore, in order to more surely position the semiconductor chip and the like, it is desirable that the bottom of the recess 4 and the contact portion for positioning have a certain level of step.
An embodiment of the positioning mechanism in which the bottom portion and the contact portion for positioning have a certain level difference will be described.

FIGS. 7A and 7B are for explaining the main structure of the semiconductor module according to the third embodiment. FIG. 7A is a plan view and FIG. 7B is a sectional view taken along the line AA 'in FIG. Shows. This is an embodiment in which the positioning recess has a double step as described above, and only the periphery of the recess in the embodiments up to FIG. 6 is shown.

In this embodiment, the Si substrates 51, 53, 5 are
6 is directly bonded via the SiO ₂ films 52 and 54, and in particular, the uppermost Si substrate 56 on which the Si ₃ N ₄ film 55 is deposited is used. As for the respective thicknesses, if the thicknesses of the Si substrate and the embodiment shown in FIG.
μm, 53 to 10 μm, 56 to 190 μm, SiO
₂ is 1 μm for both 52 and 54, 0.2 μ for Si ₃ N ₄ 55
m, and these substrates can be produced by combining processes such as thermal oxidation, direct bonding, polishing, and CVD.

After that, the uppermost Si substrate 5 is formed by ordinary photolithography as in the above-described embodiment.
The etching process of 6 is performed. As the crystal orientation of Si,
For example, 51, 53, and 56 are adhered on the {100} plane, respectively, and the mask patterns are formed in the <011> and <01-1> directions. The etching process may be anisotropic chemical etching using a KOH aqueous solution or the like. As a result, the exposed Si ₃ N ₄ film 55 is removed by ion milling, dry etching or the like, and then the Si ₃ N ₄ film 55 is removed.
The SiO ₂ film 54 sandwiched between the Si substrate 53 and the Si substrate 53 is subjected to selective side etching of, for example, 10 μm with an ammonium fluoride aqueous solution or the like.

After that, by performing anisotropic chemical etching of Si again, a double stepped concave portion as shown in FIG. 7B can be formed, and the semiconductor chip 57 can be effectively positioned. become able to. Further, in this example, since the pattern of the Si substrate 56 and the pattern of the Si substrate 53 can be formed in a self-aligned manner (self-aligned), there is no pattern deviation between the two and no problem caused by forming a double step. ..

The double step difference shown in FIG. 7 can be formed not only by side etching but also by utilizing the crystal anisotropy of Si as shown in FIG. In addition, in FIG.
(A) is a plan view and (b) is a sectional view taken along the line BB ′ of (a). In the fourth embodiment, the Si substrate 61,
63 and 65 are directly bonded only via the SiO ₂ films 62 and 64, and at that time, the Si substrate 63 and the Si substrate 65 are directly bonded by changing their crystal planes or crystal orientations. Specifically, the Si substrate 63 on the Si substrate 61 (arbitrary crystal orientation) is bonded on the {110} plane, and the Si substrate 65 is bonded on the {100} plane. Furthermore, the <001> direction of the Si substrate 63 and the S
The <011> direction of the i substrate 65 is aligned.

On the surface of the Si substrate 65 of this adhesive substrate, <01
A mask pattern is formed along the <1> and <01-1> directions, and anisotropic chemical etching of Si is performed as in the case of FIG. Next, the exposed portion of the SiO ₂ film 64 is removed by etching, and then anisotropic chemical etching of Si is performed again. As a result, each Si crystal has a geometrical {111} crystal plane that matches the shape of the mask, and particularly, the intermediate portion of the Si substrate 63 has a rhombic shape or parallelograms in which the mask pattern is inscribed like 63 '. Etched into shape. This diamond or parallelogram pattern is
By setting the thickness of the Si substrate 63 appropriately, most of the side surfaces can be made vertical.

This will be described with reference to FIG. In FIG. 9, only a rectangular pattern (solid line) and an etching pattern (broken line) that serve as a mask are shown, and the left diagram and the lower diagram show cross-sections on a diagonal line of a rhombus corresponding to the same direction. Reference numeral 71 is an opening for positioning, that is, a positioning pattern of a semiconductor chip or the like, 72 is an area in which the bottom SiO ₂ film 62 is exposed in an etched area of the Si substrate 63 (a boundary side surface is a vertical surface), 73 Is a region where the bottom SiO ₂ film 62 is not exposed.

In the region 73, an oblique surface appears as shown in the left diagram of FIG. 9, which is the same {111} (equivalent to (111) surface) as the vertical surface of the diamond boundary. This 73
If the Si substrate 63 is sufficiently thick, the oblique surface of the is further extended, but here the extension amount (depth) is increased by the SiO ₂ film 62.
Since it is regulated, it has stopped at the position shown in the figure. When the region 73 is extended to the opening 71, the bottom of the opening 71 is not a flat surface, and the original purpose cannot be achieved. Therefore, it is necessary to design these in consideration of the relationship between the size of the opening 71, the thickness of the Si substrate 63, and the size of the oblique surface 73.

An example of this design example will be shown. For simplicity,
The opening 71 serving as a mask is a square having one side of a size, and the diagonal line of the diamond shape in FIG. 9 in the vertical direction is the <001> direction of the Si substrate 63. In addition, the thickness of the Si substrate 63 is set to D
And b, c, and d are defined as shown in FIG. in this case,
Other values can be calculated using a and D as parameters. That is, b = a / 2 ^1/2 , C = a / 2 ^3/2 , D = D × 2 ^1/2
And the condition that d is smaller than b (d <b) is D <a /
It is enough to fill 2.

Therefore, in the case of FIG. 9, there is no problem if the thickness of the Si substrate 63 is set to 1/2 or less of the mask width of the substrate 63 in the <001> direction. Further, in general, when the direction of the opening serving as a mask is deviated from the <001> direction of the Si substrate 63 (when the crystallizing directions of bonding the Si substrate 63 and the Si substrate 65 are deviated),
The shape shown in FIG.
The thickness of can be similarly defined. As an example,
In the cases of 0 (b) and (c), if the opening of the mask is a square with one side a, there is no problem if the thickness of D is 20% or less of a.

Similar to the embodiment shown in FIG. 8, an opening having a double step can be formed on an adhesive substrate using another crystal plane. This is shown in FIG. In addition, in FIG.
9A is a plan view, and FIG. 9B is a sectional view taken along the line CC ′ of FIG. In the fifth embodiment, the Si substrates 91, 93 and 95 are directly bonded only through the SiO ₂ films 92 and 94 as in FIG. 8, but the S on the Si substrate 91 (arbitrary crystal orientation) is used.
Both the i substrate 93 and the Si substrate 95 have {100} planes, and the <011> direction of the Si substrate 93 and the Si substrate 95.
The bonding is performed so that the <011> direction of the above is shifted, for example, shifted by 45 °. Using this adhesive substrate, as in the case of FIG. 8, a mask pattern along the <011> and <01-1> directions is formed on the surface of the Si substrate 95 to perform anisotropic chemical etching of Si and the exposed SiO ₂ film. Etching removal of 94 is performed, followed by anisotropic chemical etching of Si.

As a result, the respective Si substrates 93 and 95 are
Shows a geometrical {111} crystal plane according to the shape of the mask, and in particular, the middle portion of the Si substrate 93 is etched into a square or rectangle inscribed with the mask pattern, as in 93 '. This square or rectangular pattern has {111} planes on the side faces, and there is a problem in that the corner portions do not form a flat bottom face with respect to the square or rectangular mask opening. However, even in such a case, the purpose can be achieved by using the deformed mask, and the application as a holder of the lens 97 as shown in FIG. 11 is possible.

Further, such a double step can be applied to a surface input / output type semiconductor module as shown in FIG. In the sixth embodiment, the Si substrates 93 and 95 are directly bonded via the SiO ₂ film 94, and the Si substrates 93 and 9 are bonded together.
5 both on the {100} plane and <0 on the Si substrate 93.
Bonding is performed so that the <11> direction and the <011> direction of the Si substrate 95 are deviated from each other, for example, by 45 °. Also, Si
A protective mask such as SiO ₂ is provided on the back surface of the substrate 93. Using this adhesive substrate, as in the case of FIG. 8, a mask pattern along the <011> and <01-1> directions is formed on the surface of the Si substrate 95 to perform anisotropic chemical etching of Si and the exposed SiO ₂ film. Etching away 94, followed by Si
Anisotropic chemical etching is performed.

As a result, the respective Si substrates 93 and 95 are
Shows a geometrical {111} crystal plane according to the shape of the mask, and is etched into a square or rectangle inscribed with the pattern to be the mask, particularly 93 'in the middle portion of the Si substrate 93. After that, the protective mask on the back surface of the Si substrate 93 is removed, and the surface input / output type semiconductor element (semiconductor laser, light emitting diode, photodiode, etc.) 101 and the lens 97 'are mounted and electrically connected.

The present invention is not limited to the above embodiment. For example, the wafers to be bonded are not limited to Si, but Si and Ge, GaAs, In
Various combinations such as P and InSb are possible. The wafer to be bonded is not limited to the semiconductor material, and a dielectric substrate or the like can be used. For example, a ceramic material such as Al ₂ O ₃ , AlN, C-BN, or SiC, a polyimide material, or the like. Polymeric materials can also be used. Furthermore, when different types of wafers are bonded, or even between wafers of the same type, by sandwiching the modified layer by changing the crystal orientation, etching can be automatically determined at the bonding surface without interposing an oxide film between them. It is possible. Further, not only optical elements and electronic elements can be mounted in the recesses, but also fibers, pins, screws, etc. can be fitted and aligned. In addition, various modifications can be made without departing from the scope of the present invention.

[0052]

As described above in detail, according to the present invention, since the adhesive substrate directly bonded with a plurality of wafers is provided with the concave portion reaching the wafer bonding portion, and the semiconductor chip is mounted in the concave portion, The positional relationship between the semiconductor chip and the other module components can be accurately maintained, and the semiconductor chip can be mechanically and firmly supported.

[Brief description of drawings]

FIG. 1 is a perspective view showing a main configuration of a semiconductor module according to a first embodiment of the present invention,

FIG. 2 is a perspective view showing an application example of a laser module to a submount,

FIG. 3 is an exploded perspective view and a sectional view showing an application example to a laser module using an MT connector,

FIG. 4 is an exploded perspective view showing a modified example of FIG.

5 is an exploded perspective view showing a modified example of FIG. 3,

FIG. 6 is a cross-sectional view showing the main configuration of a semiconductor module according to a second embodiment,

FIG. 7 is a plan view and a cross-sectional view showing a main part configuration of a semiconductor module according to a third embodiment.

FIG. 8 is a plan view and a cross-sectional view showing the main configuration of a semiconductor module according to a fourth embodiment;

FIG. 9 is a schematic view for explaining the operation of the fourth embodiment,

FIG. 10 is a schematic view showing a case where the wafers to be bonded have different crystal directions,

FIG. 11 is a cross-sectional view showing the main configuration of a lens holder according to a fifth embodiment,

FIG. 12 is a cross-sectional view showing the main configuration of a semiconductor module according to a sixth embodiment,

FIG. 13 is an exploded perspective view showing an example of a conventional laser module,

FIG. 14 is a sectional view for explaining a conventional surface mounting method,

FIG. 15 is a cross-sectional view for explaining a method of molding an element in a conventional IC card,

FIG. 16 is a perspective view showing a configuration example of an MT connector.

[Explanation of symbols]

 1, 2 ... Silicon wafer, 3 ... Oxide film, 4 ... Recessed portion, 5 ... Electrode wiring, 6 ... Module component (chip mounting substrate), 7 ... Laser chip, 8 ... Base, 9 ... Lid, 10 ... Holder plate , 41 ... Adhesive substrate, 42 ... Electronic element, 43 ... Electronic element chip, 141 ... Pin, 142 ... Fiber end face, 143 ... Connector, 144 ... Clip, 145 ... Optical fiber.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Fumihiko Shimizu 1 Komukai-shiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Toshiba Komukai factory

Claims (4)

[Claims] 1. An adhesive substrate obtained by bonding the surfaces of a plurality of semiconductor wafers having a predetermined thickness and smooth surfaces to each other, and a part of the adhesive substrate is etched to a depth reaching the bonding portion of the wafer. A semiconductor module comprising a formed recess and a semiconductor chip mounted in the recess. 2. An adhesive substrate formed by joining the surfaces of a plurality of semiconductor wafers having a predetermined thickness and smooth surfaces to each other, and a part of the adhesive substrate is etched to a depth reaching the joint portion of the wafer, A semiconductor module comprising: a recess formed so that a cross-sectional diameter of a top portion or an abdominal portion is smaller than a cross-sectional diameter of a bottom portion, and a semiconductor chip mounted in this recess. 3. An adhesive substrate in which at least three semiconductor wafers each having a predetermined thickness and a smooth surface are laminated by directly bonding the surfaces of the wafers, and a part of the adhesive substrate is bonded to the wafer. And a semiconductor chip mounted in this recess, which is formed so that the cross-sectional diameter of the abdomen is smaller than the cross-sectional diameter of the bottom by etching to a depth that exceeds one of the A semiconductor module comprising: 4. A connector having a predetermined guide pin or capable of being held by the guide pin is positioned by a chip mounting board which is cut out in accordance with the guide pin and a space between the guide pins and has a semiconductor chip at a predetermined position. A semiconductor module characterized by being formed.