JPH0737932A - Semiconductor device and its mounting method - Google Patents
Semiconductor device and its mounting methodInfo
- Publication number
- JPH0737932A JPH0737932A JP18102293A JP18102293A JPH0737932A JP H0737932 A JPH0737932 A JP H0737932A JP 18102293 A JP18102293 A JP 18102293A JP 18102293 A JP18102293 A JP 18102293A JP H0737932 A JPH0737932 A JP H0737932A
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- board
- semiconductor
- semiconductor package
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、たとえば半導体装置
およびその実装方法に関するもので、特に半田バンプを
介して実装基板上に半導体部品を実装してなる表面実装
型の半導体装置に使用されるものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a semiconductor device and its mounting method, and more particularly to a semiconductor device of a surface mounting type in which a semiconductor component is mounted on a mounting substrate via solder bumps. Is.
【０００２】[0002]
【従来の技術】従来、表面実装型の半導体装置は、たと
えば図６に示すように、半田バンプ１を用いて半導体パ
ッケージ装置２とボード３とを接合することで、構成さ
れている。2. Description of the Related Art Conventionally, a surface mount type semiconductor device is constructed by joining a semiconductor package device 2 and a board 3 with a solder bump 1 as shown in FIG.
【０００３】そして、その接合の際には、半田バンプ１
のつぶれ過多を防ぐために、スペーサとよばれる座板４
を用いて半導体パッケージ装置２とボード３との間隔を
一定に保ち、実装時のボード３からの半導体パッケージ
装置２の取り付け位置の高さを制御するようになってい
た。Then, at the time of joining, the solder bump 1
Seat plate 4 called a spacer to prevent excessive crushing
The distance between the semiconductor package device 2 and the board 3 is kept constant by using the, and the height of the mounting position of the semiconductor package device 2 from the board 3 at the time of mounting is controlled.
【０００４】しかしながら、この種の表面実装型の半導
体装置においては、以下のような問題があった。すなわ
ち、半田バンプにより接合を行うものの場合、半導体パ
ッケージ装置はボードのスルーホールとのかみ合わせ用
のアウタリードピンを有しないため、位置合わせが難し
い。However, the surface mounting type semiconductor device of this type has the following problems. That is, in the case of joining by means of solder bumps, the semiconductor package device does not have outer lead pins for engaging with the through holes of the board, so that alignment is difficult.
【０００５】この位置合わせの重要性は、たとえば半導
体パッケージ装置２における外部パッドが小さくなれば
なるほど、パッドの間隔が狭くなればなるほど、ますま
す大きくなってくる。The importance of this alignment becomes more and more important, for example, as the external pads in the semiconductor package device 2 become smaller and as the pad spacing becomes smaller.
【０００６】[0006]
【発明が解決しようとする課題】上記したように、従来
においては、実装時のボードからの半導体パッケージ装
置の取り付け位置の高さは制御できるものの、ボードと
半導体パッケージ装置との位置合わせが難しいという欠
点があった。As described above, in the past, although the height of the mounting position of the semiconductor package device from the board at the time of mounting can be controlled, it is difficult to align the board and the semiconductor package device. There was a flaw.
【０００７】そこで、この発明は、取り付け位置の高さ
の制御のみでなく、実装基板と半導体部品との位置合わ
せを高精度化でき、接合の信頼性を高めることが可能な
半導体装置およびその実装方法を提供することを目的と
している。Therefore, according to the present invention, not only the height of the mounting position can be controlled, but also the positioning of the mounting substrate and the semiconductor component can be highly accurate, and the reliability of the bonding can be improved, and the mounting thereof. It is intended to provide a way.
【０００８】[0008]
【課題を解決するための手段】上記の目的を達成するた
めに、この発明の半導体装置にあっては、半田バンプを
介して実装基板上に半導体部品を実装してなるものにお
いて、前記実装基板の実装面に形成された凹部と、前記
半導体部品の実装面に前記半田バンプよりも高さを有し
て設けられ、その一部が前記実装基板上の凹部と係合さ
れる凸部とから構成されている。In order to achieve the above object, in the semiconductor device of the present invention, a semiconductor component is mounted on a mounting board via solder bumps. From a concave portion formed on the mounting surface of the semiconductor component and a convex portion provided on the mounting surface of the semiconductor component with a height higher than that of the solder bump, and a part of which is engaged with the concave portion on the mounting substrate. It is configured.
【０００９】また、この発明の半導体装置の実装方法に
あっては、半田バンプを介して実装基板上に半導体部品
を実装する場合において、半田バンプの形成された半導
体部品の実装面に、前記半田バンプよりも高さを有した
凸部を設け、この凸部の一部を、実装基板上の実装面に
形成された凹部に係合させつつ、前記半田バンプによる
接続を行うようになっている。Further, according to the semiconductor device mounting method of the present invention, when the semiconductor component is mounted on the mounting substrate via the solder bump, the solder is formed on the mounting surface of the semiconductor component on which the solder bump is formed. A convex portion having a height higher than that of the bump is provided, and a part of the convex portion is engaged with a concave portion formed on the mounting surface of the mounting board while the solder bump is used for connection. .
【００１０】[0010]
【作用】この発明は、上記した手段により、半田バンプ
のつぶれ過多を防止しつつ、簡単に位置合わせできるよ
うになるため、整合性をも向上することが可能となるも
のである。According to the present invention, by the above-mentioned means, the solder bumps can be prevented from being excessively crushed and can be easily aligned, so that the matching can be improved.
【００１１】[0011]
【実施例】以下、この発明の実施例について図面を参照
して説明する。図１は、本発明の第１の実施例にかかる
表面実装型半導体装置（フェイスアップタイプ）の概略
を示すものである。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a surface mount semiconductor device (face-up type) according to a first embodiment of the present invention.
【００１２】すなわち、この半導体装置は、たとえば半
田バンプ１１を介して、半導体部品としての半導体パッ
ケージ装置１２が、実装基板としてのボード１３上に実
装された構成とされている。That is, this semiconductor device is constructed such that a semiconductor package device 12 as a semiconductor component is mounted on a board 13 as a mounting substrate via, for example, a solder bump 11.
【００１３】そして、半導体パッケージ装置１２とボー
ド１３との間にはスペーサ（座板）１４が介在されて、
実装時の、ボード１３からの半導体パッケージ装置１２
の取り付け位置の高さの制御、および半導体パッケージ
装置１２のボード１３との位置合わせが行われるように
なっている。A spacer (seat plate) 14 is interposed between the semiconductor package device 12 and the board 13,
Semiconductor package device 12 from board 13 during mounting
The height of the mounting position is controlled and the position of the semiconductor package device 12 with the board 13 is adjusted.
【００１４】半導体パッケージ装置１２は、たとえばア
ルミナなどの基材１２ａと、この基材１２ａ上にマウン
トされた半導体チップ１２ｂと、この半導体チップ１２
ｂ上の電極パッドと基材１２ａ上の配線とを電気的に接
続するボンディングワイヤ１２ｃ、および基材１２ａ上
の半導体チップ１２ｂなどを覆うようにして設けられた
封止用リッド１２ｄからなっている。The semiconductor package device 12 includes a base material 12a such as alumina, a semiconductor chip 12b mounted on the base material 12a, and the semiconductor chip 12.
The bonding wire 12c electrically connects the electrode pad on the substrate b to the wiring on the substrate 12a, and the sealing lid 12d provided so as to cover the semiconductor chip 12b on the substrate 12a. .
【００１５】そして、基材１２ａの下面、つまり半導体
パッケージ装置１２のボード１３との実装面には外部パ
ッドが設けられ、この外部パッドに対応して上記半田バ
ンプ１１が形成されるようになっている。An external pad is provided on the lower surface of the base material 12a, that is, the mounting surface of the semiconductor package device 12 on which the board 13 is mounted, and the solder bump 11 is formed corresponding to the external pad. There is.
【００１６】ボード１３は、上記半導体パッケージ装置
１２が実装される、その実装面に、上記半田バンプ１１
の接合先である配線パターン（フットプリント）が設け
られるとともに、上記半導体パッケージ装置１２とのア
ライメントを行うための凹部１３ａが形成されている。The board 13 is mounted with the semiconductor package device 12, and the solder bumps 11 are mounted on the mounting surface thereof.
Is provided with a wiring pattern (footprint), and a concave portion 13a for alignment with the semiconductor package device 12 is formed.
【００１７】この凹部１３ａは、これに係合されるスペ
ーサ１４の凸部（後述する）の高さを逃がせるだけの深
さを有して形成されている。スペーサ１４は、接合の際
の半田バンプ１１のつぶれ過多を防止するためのもので
あり、このスペーサ１４の厚みにより、半導体パッケー
ジ装置１２とボード１３との間隔を一定に保つようにな
っている。The recess 13a is formed to have a depth enough to allow the height of a protrusion (described later) of the spacer 14 engaged with the recess 13a to escape. The spacer 14 is for preventing the solder bumps 11 from being excessively crushed at the time of joining, and the thickness of the spacer 14 keeps the gap between the semiconductor package device 12 and the board 13 constant.
【００１８】また、このスペーサ１４には、その下部
に、ボード１３の実装面上に設けられた凹部１３ａと係
合される凸部１４ａが形成されている。すなわち、半導
体パッケージ装置１２のボード１３との実装面の所定位
置に取り付けられたスペーサ１４の、その凸部１４ａを
ボード１３の実装面上の凹部１３ａに係合させること
で、アライメント、つまり半導体パッケージ装置１２の
ボード１３との位置合わせが行われる。Further, the spacer 14 is provided at its lower portion with a convex portion 14a which engages with the concave portion 13a provided on the mounting surface of the board 13. That is, by engaging the convex portion 14a of the spacer 14 attached at a predetermined position on the mounting surface of the board 13 of the semiconductor package device 12 with the concave portion 13a on the mounting surface of the board 13, alignment, that is, the semiconductor package. The alignment of the device 12 with the board 13 is performed.
【００１９】なお、凸部１４ａは、少なくとも０．３ｍ
ｍ以上の高さを有して構成されるようになっている。し
かして、半導体パッケージ装置１２のボード１３上への
実装は、以下のようにして行われる。The convex portion 14a has at least 0.3 m.
It is configured to have a height of m or more. The mounting of the semiconductor package device 12 on the board 13 is performed as follows.
【００２０】まず、半導体パッケージ装置１２の実装面
上の外部パッドのそれぞれに、半田バンプ１１が形成さ
れる。また、半導体パッケージ装置１２の実装面上の所
定位置に、スペーサ１４が接着または銀ロウなどにより
取り付けられる。First, the solder bumps 11 are formed on each of the external pads on the mounting surface of the semiconductor package device 12. Further, the spacer 14 is attached to a predetermined position on the mounting surface of the semiconductor package device 12 by adhesion or silver brazing.
【００２１】そして、上記スペーサ１４の凸部１４ａ
を、ボード１３の実装面上の凹部１３ａに係合させるべ
く、半導体パッケージ装置１２とボード１３との位置合
わせが行われる。Then, the convex portion 14a of the spacer 14 is formed.
The semiconductor package device 12 and the board 13 are aligned with each other so as to engage with the recess 13a on the mounting surface of the board 13.
【００２２】こうして、実装の際に、スペーサ１４の凸
部１４ａがボード１３の実装面上の凹部１３ａに係合さ
れることにより、半導体パッケージ装置１２とボード１
３とが位置合わせされつつ、半導体パッケージ装置１２
とボード１３との間隔が一定に保たれた状態で、半田バ
ンプ１１とボード１３の実装面上のフットプリントとの
接合が行われる。Thus, during mounting, the convex portion 14a of the spacer 14 is engaged with the concave portion 13a on the mounting surface of the board 13, so that the semiconductor package device 12 and the board 1 are mounted.
And the semiconductor package device 12 are aligned with each other.
The solder bumps 11 and the footprints on the mounting surface of the board 13 are joined in a state where the distance between the solder bumps 11 and the board 13 is kept constant.
【００２３】この結果、半田バンプ１１がつぶれ過ぎた
りすることなく、しかも半導体パッケージ装置１２とボ
ード１３とのアライメントが良好な状態で、実装は完了
される。As a result, the mounting is completed without the solder bumps 11 being excessively crushed and the semiconductor package device 12 and the board 13 being in good alignment.
【００２４】図２は、この発明の第２の実施例にかかる
表面実装型半導体装置（フェイスアップタイプ）の概略
を示すものである。この実施例は、半田バンプ１１の一
部をコバールなどからなるピン形状のピン構造体（凸
部）１５とし、アライメントを良好に行えるようにする
ために、たとえば半導体パッケージ装置１２の外辺に近
い２か所以上の場所（さらにいえば、対向長を長くとれ
るところ）に配置するようにしたものである。FIG. 2 shows an outline of a surface mount semiconductor device (face-up type) according to a second embodiment of the present invention. In this embodiment, a part of the solder bump 11 is a pin-shaped pin structure (projection) 15 made of Kovar or the like, and is close to, for example, the outer periphery of the semiconductor package device 12 in order to perform good alignment. It is arranged at two or more places (more specifically, places where the facing length can be long).
【００２５】そして、このピン構造体１５の先端をボー
ド１３の実装面上のスルーホール１３ｂに係合させるこ
とで、位置合わせは勿論、そのスルーホール１３ｂと係
合される先端以外の部分がスペーサとしても十分に機能
するようにしている。By engaging the tip of the pin structure 15 with the through hole 13b on the mounting surface of the board 13, not only the positioning but also the portion other than the tip engaged with the through hole 13b is a spacer. As well as trying to work well.
【００２６】この場合、第１の実施例に示したような大
型のスペーサ１４を必要としない分、その取り付けの位
置（半導体パッケージ装置１２の中央部付近１２ｅ）に
も外部パッドを配置できるようになる。In this case, since the large-sized spacer 14 as shown in the first embodiment is not necessary, the external pad can be arranged at the mounting position (near the central portion 12e of the semiconductor package device 12). Become.
【００２７】このため、外部パッドの増設、もしくは同
じパッド数の場合には、その中央部付近１２ｅにもパッ
ドを配置することで、パッドの間隔を広くできる、また
はパッケージの小型化なども容易に可能である。Therefore, if external pads are added, or if the same number of pads is used, the pads can be arranged near the central portion 12e to widen the interval between the pads or to easily downsize the package. It is possible.
【００２８】図３は、この発明の第３の実施例にかかる
表面実装型半導体装置（フェイスアップタイプ）の概略
を示すものである。この実施例は、半田バンプ１１の一
部を、半田の融点（約１８０℃）よりも約１００℃も高
い融点をもつ金属からなる金属バンプ（凸部）１６とし
たものである。FIG. 3 schematically shows a surface mount type semiconductor device (face-up type) according to a third embodiment of the present invention. In this embodiment, a part of the solder bump 11 is a metal bump (projection) 16 made of a metal having a melting point higher by about 100 ° C. than the melting point of solder (about 180 ° C.).
【００２９】この金属バンプ１６は、半田バンプ１１よ
り高い融点をもつため、半導体パッケージ装置１２がボ
ード１３上に実装される場合においても溶けることな
く、したがって金属バンプ１６の先端をボード１３の実
装面上の凹部１３ｃに係合させることで、位置合わせは
勿論、スペーサとしての役目も果たすことができる。Since the metal bumps 16 have a higher melting point than the solder bumps 11, they do not melt even when the semiconductor package device 12 is mounted on the board 13. Therefore, the tips of the metal bumps 16 are mounted on the mounting surface of the board 13. By engaging with the upper recess 13c, not only the position alignment but also the role of a spacer can be achieved.
【００３０】この場合も、上記した第２の実施例と同様
の効果、つまり大型のスペーサ１４を必要としない分、
外部パッドの増設、もしくはパッド間隔の拡張、または
パッケージの小型化などが容易に可能である。Also in this case, the same effect as that of the second embodiment described above, that is, the large spacer 14 is not required,
It is easy to add external pads, expand the pad spacing, or reduce the package size.
【００３１】図４は、この発明の第４の実施例にかかる
表面実装型半導体装置（フェイスアップタイプ）の概略
を示すものである。この実施例は、半導体パッケージ装
置１２の基材１２ａに直に凸部１７を形成し、この凸部
１７の一部をボード１３上の凹部１３ｄに係合させるこ
とにより、位置合わせと高さの制御（スペーサとしての
機能）とを行うようにしたものである。FIG. 4 schematically shows a surface mount type semiconductor device (face-up type) according to a fourth embodiment of the present invention. In this embodiment, the convex portion 17 is formed directly on the base material 12a of the semiconductor package device 12, and a part of the convex portion 17 is engaged with the concave portion 13d on the board 13 to adjust the alignment and height. Control (function as a spacer) is performed.
【００３２】この場合、基材１２ａと凸部１７とが一体
化されるため、先に説明したいずれの実施例の場合より
も、多少、アライメントの精度を向上できる。図５は、
この発明の第５の実施例にかかる表面実装型半導体装置
（キャビティダウンタイプ）の概略を示すものである。In this case, since the base material 12a and the convex portion 17 are integrated, the alignment accuracy can be improved to some extent as compared with the case of any of the above-described embodiments. Figure 5
9 is a schematic view of a surface mount type semiconductor device (cavity down type) according to a fifth embodiment of the present invention.
【００３３】この実施例は、半導体パッケージ装置２１
の、基材２１ａのキャビティ内にマウントされた半導体
チップ２１ｂ、およびボンディング接続用のワイヤ２１
ｃなどを封止するための封止用リッド２１ｄを用い、こ
のリッド２１ｄの一部をボード１３上の凹部１３ｅに係
合させることにより、位置合わせと高さの制御（スペー
サとしての機能）とを行うようにしたものである。In this embodiment, the semiconductor package device 21 is used.
, The semiconductor chip 21b mounted in the cavity of the base material 21a, and the wire 21 for bonding connection.
By using a sealing lid 21d for sealing c or the like and engaging a part of the lid 21d with the recess 13e on the board 13, alignment and height control (function as a spacer) can be achieved. Is to do.
【００３４】この場合、封止用リッド２１ｄを、スペー
サおよび凸部としても兼用できるため、スペーサなどを
用いない分だけ、コスト的に期待できる。上記したよう
に、半田バンプのつぶれ過多を防止しつつ、簡単に位置
合わせできるようにしている。In this case, since the sealing lid 21d can be used also as a spacer and a convex portion, the cost can be expected because the spacer is not used. As described above, the solder bumps are prevented from being excessively crushed, and the alignment can be easily performed.
【００３５】すなわち、半導体パッケージ装置の実装面
に設けられた凸部の先端と、ボードの実装面に形成され
た凹部とを実装時に係合させ、その状態で半田バンプに
よる接合を行うようにしている。これにより、ボードと
半導体パッケージ装置との位置合わせを精度良く行うこ
とができるようになるため、実装時のボードからの半導
体パッケージ装置の取り付け位置の高さの制御のみでな
く、整合性をも向上することが可能となる。したがっ
て、たとえ位置合わせの重要性が増した場合にも、正確
な位置合わせが可能となり、接合の信頼性をより高める
ことができるものである。That is, the tip of the convex portion provided on the mounting surface of the semiconductor package device and the concave portion formed on the mounting surface of the board are engaged at the time of mounting, and solder bump bonding is performed in this state. There is. As a result, the board and the semiconductor package device can be aligned with high accuracy, so that not only the height of the mounting position of the semiconductor package device from the board at the time of mounting is controlled, but also the consistency is improved. It becomes possible to do. Therefore, even if the importance of alignment increases, accurate alignment becomes possible, and the reliability of bonding can be further improved.
【００３６】なお、上記実施例においては、いずれも封
止用リッドが設けられた封止型の半導体部品を例に説明
したが、これに限らず、たとえば樹脂などによる他の封
止型半導体部品や封止型以外の半導体部品など、アウタ
リードを用いない表面実装型の各種の半導体部品に適用
できる。その他、この発明の要旨を変えない範囲におい
て、種々変形実施可能なことは勿論である。In each of the above embodiments, the sealing type semiconductor component provided with the sealing lid has been described as an example, but the present invention is not limited to this, and other sealing type semiconductor components made of, for example, resin are used. It can be applied to various surface mount type semiconductor components that do not use outer leads, such as semiconductor components other than the sealed type. Of course, various modifications can be made without departing from the scope of the invention.
【００３７】[0037]
【発明の効果】以上、詳述したようにこの発明によれ
ば、取り付け位置の高さの制御のみでなく、実装基板と
半導体部品との位置合わせを高精度化でき、接合の信頼
性を高めることが可能な半導体装置およびその実装方法
を提供できる。As described above in detail, according to the present invention, not only the height of the mounting position can be controlled, but also the mounting substrate and the semiconductor component can be aligned with high precision, and the reliability of bonding can be improved. It is possible to provide a semiconductor device and a method of mounting the same.
【図１】この発明の第１の実施例にかかる表面実装型半
導体装置の概略を示す断面図。FIG. 1 is a sectional view schematically showing a surface mount semiconductor device according to a first embodiment of the present invention.
【図２】この発明の第２の実施例にかかる表面実装型半
導体装置の概略を示す断面図。FIG. 2 is a sectional view showing an outline of a surface mount semiconductor device according to a second embodiment of the present invention.
【図３】この発明の第３の実施例にかかる表面実装型半
導体装置の概略を示す断面図。FIG. 3 is a sectional view showing the outline of a surface mount semiconductor device according to a third embodiment of the present invention.
【図４】この発明の第４の実施例にかかる表面実装型半
導体装置の概略を示す断面図。FIG. 4 is a sectional view showing the outline of a surface mount semiconductor device according to a fourth embodiment of the present invention.
【図５】この発明の第５の実施例にかかる表面実装型半
導体装置の概略を示す断面図。FIG. 5 is a sectional view showing the outline of a surface mount semiconductor device according to a fifth embodiment of the present invention.
【図６】従来技術とその問題点を説明するために示す表
面実装型半導体装置の断面図。FIG. 6 is a cross-sectional view of a surface-mounted semiconductor device shown for explaining the related art and its problems.
１１…半田バンプ、１２…半導体パッケージ装置（半導
体部品）、１３…ボード（実装基板）、１３ａ…凹部、
１４…スペーサ（座板）、１４ａ…凸部。11 ... Solder bumps, 12 ... Semiconductor package device (semiconductor component), 13 ... Board (mounting substrate), 13a ... Recess,
14 ... Spacers (seat plates), 14a ... Projections.
Claims (7)
部品を実装してなる装置において、 前記実装基板の実装面に形成された凹部と、 前記半導体部品の実装面に前記半田バンプよりも高さを
有して設けられ、その一部が前記実装基板上の凹部と係
合される凸部とを具備したことを特徴とする半導体装
置。1. A device in which a semiconductor component is mounted on a mounting substrate via a solder bump, and a recess formed on a mounting surface of the mounting substrate and a mounting surface of the semiconductor component higher than the solder bump. A semiconductor device comprising: a protrusion having a height, a part of which is engaged with the recess on the mounting substrate.
基板との間に介在される座板の一部であることを特徴と
する請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the convex portion is a part of a seat plate interposed between the semiconductor component and the mounting substrate.
をピン形状に形成したピン構造体からなることを特徴と
する請求項１に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the convex portion is formed of a pin structure in which some of the solder bumps are formed in a pin shape.
を半田バンプよりも融点の高い金属を用いて形成した金
属バンプからなることを特徴とする請求項１に記載の半
導体装置。4. The semiconductor device according to claim 1, wherein the protrusions are metal bumps formed by using some of the solder bumps using a metal having a melting point higher than that of the solder bumps.
部により形成されることを特徴とする請求項１に記載の
半導体装置。5. The semiconductor device according to claim 1, wherein the convex portion is formed by a part of a base material of the semiconductor component.
ドにより兼用されることを特徴とする請求項１に記載の
半導体装置。6. The semiconductor device according to claim 1, wherein the convex portion is also used as a sealing lid of the semiconductor component.
部品を実装する方法において、 半田バンプの形成された半導体部品の実装面に、前記半
田バンプよりも高さを有した凸部を設け、 この凸部の一部を、実装基板上の実装面に形成された凹
部に係合させつつ、前記半田バンプによる接続を行うこ
とを特徴とする半導体装置の実装方法。7. A method of mounting a semiconductor component on a mounting substrate via a solder bump, wherein a convex portion having a height higher than the solder bump is provided on a mounting surface of the semiconductor component on which the solder bump is formed, A method for mounting a semiconductor device, wherein a part of the convex portion is engaged with a concave portion formed on a mounting surface of a mounting substrate, and the connection is performed by the solder bump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18102293A JPH0737932A (en) | 1993-07-22 | 1993-07-22 | Semiconductor device and its mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18102293A JPH0737932A (en) | 1993-07-22 | 1993-07-22 | Semiconductor device and its mounting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0737932A true JPH0737932A (en) | 1995-02-07 |
Family
ID=16093398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18102293A Pending JPH0737932A (en) | 1993-07-22 | 1993-07-22 | Semiconductor device and its mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0737932A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7608138B2 (en) | 2003-12-12 | 2009-10-27 | Ngk Insulators, Inc. | Device for measuring filter pressure loss |
| CN102403296A (en) * | 2010-09-13 | 2012-04-04 | 英飞凌科技股份有限公司 | Semiconductor module and method for production thereof |
| JP2014123690A (en) * | 2012-12-24 | 2014-07-03 | Denso Corp | Circuit board |
-
1993
- 1993-07-22 JP JP18102293A patent/JPH0737932A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7608138B2 (en) | 2003-12-12 | 2009-10-27 | Ngk Insulators, Inc. | Device for measuring filter pressure loss |
| CN102403296A (en) * | 2010-09-13 | 2012-04-04 | 英飞凌科技股份有限公司 | Semiconductor module and method for production thereof |
| JP2014123690A (en) * | 2012-12-24 | 2014-07-03 | Denso Corp | Circuit board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5563445A (en) | Semiconductor device | |
| JP2000223622A (en) | Semiconductor device, its manufacture, and mounting structure using the same | |
| JPH08306724A (en) | Semiconductor device, manufacturing method and its mounting method | |
| JPH0737932A (en) | Semiconductor device and its mounting method | |
| JP2003110080A (en) | Semiconductor device | |
| JP2949969B2 (en) | Film carrier semiconductor device | |
| JPH03125440A (en) | Electronic parts | |
| JP3670371B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP4577686B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2000077458A (en) | Flip-chip mounting method | |
| JPS58202540A (en) | Method of bonding fine positioning by stand-off | |
| JP2000164628A (en) | Electronic part and face-down mounting structure | |
| JPH07273146A (en) | Mounting method for semiconductor device | |
| JPH05160316A (en) | Semiconductor element | |
| JP3270883B2 (en) | Semiconductor device | |
| JP2815984B2 (en) | Semiconductor device | |
| JPH07106470A (en) | Semiconductor device | |
| JP3745106B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH08181168A (en) | Semiconductor device | |
| JPH0541460A (en) | Electronic component packaging board | |
| JPH11288978A (en) | Semiconductor device | |
| JPS634690A (en) | Thick film hybrid integrated circuit substrate | |
| JPS6249636A (en) | Substrate for mounting flip chip | |
| JPH08307045A (en) | Wiring board | |
| JP2000077591A (en) | Semiconductor device and assembling method thereof |