JPH08307045A - Wiring board - Google Patents
Wiring boardInfo
- Publication number
- JPH08307045A JPH08307045A JP12896595A JP12896595A JPH08307045A JP H08307045 A JPH08307045 A JP H08307045A JP 12896595 A JP12896595 A JP 12896595A JP 12896595 A JP12896595 A JP 12896595A JP H08307045 A JPH08307045 A JP H08307045A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- wiring board
- substrate
- semiconductor chip
- resist film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は配線基板に関し、例えば
フリツプチツプ(F/C)実装用の配線基板に適用して
好適なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board, and is suitable for application to, for example, a wiring board for flip chip (F / C) mounting.
【0002】[0002]
【従来の技術】従来、ICチツプを配線基板上に実装す
る実装方法の1つとして、ICチツプの各電極(パツ
ド)上にそれぞれバンプを形成し、当該ICチツプをフ
エースダウン方式により配線基板上に位置決めマウント
した後、各バンプを溶融することによりICチツプの各
パツドと配線基板の対応する電極(ランド)とを接合す
るようにして行う、いわゆるフリツプチツプ実装方法が
ある。2. Description of the Related Art Conventionally, as one mounting method for mounting an IC chip on a wiring board, bumps are formed on respective electrodes (pads) of the IC chip and the IC chip is mounted on the wiring board by a face-down method. There is a so-called flip-chip mounting method in which each pad of the IC chip and the corresponding electrode (land) of the wiring substrate are joined by melting each bump after positioning and mounting.
【0003】このようなフリツプチツプ実装に用いられ
る配線基板は、通常、図3に示すように構成されてお
り、ガラスエポキシ材等でなる基板2の一面に実装対象
のICチツプのパツド位置にそれぞれ対応させて複数の
ランド3が設けられている。また基板2の一面上には、
はんだ付け領域の制限や、絶縁性の確保等を目的として
絶縁材からなるレジスト膜4が基板2の各ランド3の周
囲を避けて被着されており、かくして形成されるレジス
ト膜4の枠状の開口部4Aを通して図4のように実装対
象のICチツプ5の各パツド(図示せず)と配線基板1
の対応するランド3とをバンプ6を介して接合させるこ
とができるようになされている。The wiring board used for such flip chip mounting is usually constructed as shown in FIG. 3, and corresponds to the pad position of the IC chip to be mounted on one surface of the substrate 2 made of glass epoxy material or the like. Thus, a plurality of lands 3 are provided. Also, on one surface of the substrate 2,
A resist film 4 made of an insulating material is applied so as to avoid the periphery of each land 3 of the substrate 2 for the purpose of limiting the soldering area and ensuring insulation, and thus the frame shape of the resist film 4 thus formed. As shown in FIG. 4, the pads (not shown) of the IC chip 5 to be mounted and the wiring board 1 are passed through the openings 4A of the wiring board 1.
The corresponding land 3 can be bonded via the bump 6.
【0004】[0004]
【発明が解決しようとする課題】ところで、近年、配線
基板への電子部品の高密度実装化に伴いICチツプ5の
パツドの間隔がますます狭くなつてきている。この場合
パツド間隔の狭いICチツプ5をフリツプチツプ実装方
法により配線基板1上に実装するに際して、配線基板1
の各ランド3間(及びICチツプ5の各パツド間)にシ
ヨートを発生させないためには、ICチツプ5の各パツ
ドと配線基板1の対応するランド3とを接合するバンプ
6の大きさを従来に比べて小さくする必要がある。By the way, in recent years, the spacing between the pads of the IC chip 5 has become narrower due to the high density mounting of electronic components on a wiring board. In this case, when the IC chip 5 having a narrow pad interval is mounted on the wiring board 1 by the flip chip mounting method, the wiring board 1
In order to prevent shorts from being generated between the respective lands 3 (and between the respective pads of the IC chip 5), the size of the bumps 6 for joining the respective pads of the IC chip 5 and the corresponding lands 3 of the wiring board 1 is conventionally set. Need to be smaller than.
【0005】このため一般的にパツド間隔の狭いICチ
ツプ5では、各パツド上に形成するバンプ6の高さが必
然的に低くなる傾向にある。ところが、従来のフリツプ
チツプ実装用の配線基板1では、レジスト膜4の厚みが
約20〔μm 〕もあるため、ICチツプ5のバンプ6の高
さをより低くしようとすると、レジスト膜4の厚みがバ
ンプ6の高さを上回ることがあり、この結果ICチツプ
5の下面がレジスト膜4の上面と当接した状態において
当該ICチツプ5の各パツド上に形成された各バンプ6
が配線基板1の対応するランド3と接触できず、ICチ
ツプ6を配線基板1上に実装できなくなる(すわなちI
Cチツプ5の各パツドをそれぞれ配線基板1の対応する
ランド3にバンプ6を介して確実かつ正確に接合できな
くなる)おそれがあつた。Therefore, generally, in the IC chip 5 having a narrow pad interval, the height of the bump 6 formed on each pad tends to be inevitably lowered. However, in the conventional wiring board 1 for flip chip mounting, the thickness of the resist film 4 is about 20 [μm], so that if the height of the bump 6 of the IC chip 5 is made lower, the thickness of the resist film 4 becomes smaller. The bumps 6 may exceed the height of the bumps 6, and as a result, the bumps 6 formed on the pads of the IC chip 5 with the lower surface of the IC chip 5 in contact with the upper surface of the resist film 4.
Cannot contact the corresponding land 3 of the wiring board 1 and the IC chip 6 cannot be mounted on the wiring board 1 (that is, I
There is a possibility that each pad of the C-chip 5 cannot be reliably and accurately joined to the corresponding land 3 of the wiring board 1 via the bump 6.
【0006】本発明は以上の点を考慮してなされたもの
で、電極間隔の狭いICチツプの実装に対応し得る配線
基板を提案しようとするものである。The present invention has been made in consideration of the above points, and an object thereof is to propose a wiring board that can be mounted on an IC chip having a narrow electrode interval.
【0007】[0007]
【課題を解決するための手段】かかる課題を解決するた
め本発明においては、配線基板上に実装される半導体チ
ツプの実装位置に対応させて、基板上に被着されるレジ
スト膜に半導体チツプの基板との対向面とほぼ同等又は
当該対向面よりも大きい開口部を設けるようにした。In order to solve such a problem, in the present invention, the semiconductor chip is formed on a resist film deposited on the substrate in correspondence with the mounting position of the semiconductor chip mounted on the wiring substrate. An opening portion that is substantially equal to or larger than the surface facing the substrate is provided.
【0008】[0008]
【作用】レジスト膜に半導体チツプの基板との対向面と
ほぼ同等又は当該対向面よりも大きい開口部を設けるよ
うにしたことにより、半導体チツプをこのレジスト膜の
開口部内に嵌め込むようにして基板上にマウントし、実
装することができる。従つて半導体チツプの各電極及び
配線基板の対応する電極間を接合するためのバンプの高
さや、レジスト膜の高さに関わりなく、半導体チツプの
各電極と、これら各電極にそれぞれ対応させて配線基板
の基板に設けられた各電極とをバンプを介して確実に接
合させることができる。By providing an opening in the resist film which is substantially equal to or larger than the surface of the semiconductor chip facing the substrate, the semiconductor chip is fitted into the opening of the resist film on the substrate. Can be mounted and implemented. Therefore, regardless of the height of the bumps for joining the electrodes of the semiconductor chip and the corresponding electrodes of the wiring board and the height of the resist film, the electrodes of the semiconductor chip and the wirings corresponding to these electrodes are provided. The electrodes of the substrate can be reliably bonded to the electrodes provided on the substrate via the bumps.
【0009】[0009]
【実施例】以下図面について、本発明の一実施例を詳述
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.
【0010】図3及び図4との対応部分に同一符号を付
して示す図1及び図2において、10は全体として実施
例によるフリツプチツプ実装用の配線基板を示し、基板
2上に絶縁体からなるレジスト膜11が被着されてい
る。この場合レジスト膜11には、ICチツプ5の実装
位置に当該ICチツプ5の基板2との対向面とほぼ同等
の大きさの開口部11Aが設けられており、これにより
実装対象のICチツプ5をレジスト膜11の開口部11
A内に完全に嵌め込み得るようになされている。1 and 2 in which parts corresponding to those in FIGS. 3 and 4 are designated by the same reference numerals, 10 denotes a wiring board for flip-chip mounting according to the embodiment as a whole, and an insulating material is provided on the board 2. The resist film 11 is formed. In this case, the resist film 11 is provided with an opening 11A at a mounting position of the IC chip 5 and having substantially the same size as the surface of the IC chip 5 facing the substrate 2, and thus the IC chip 5 to be mounted is mounted. The opening 11 of the resist film 11
It is designed so that it can be completely fitted into A.
【0011】以上の構成において、この配線基板10で
は、実装対象のICチツプ5をその実装位置に設けられ
たレジスト膜11の開口部11A内に嵌め込むようにし
てマウントし、実装することができる。従つてICチツ
プ5の各パツド上にそれぞれ形成されたバンプ6をその
高さやレジスト膜11の厚みに関わりなく確実に対応す
るランド3と当接させ、接合させることができるため、
パツド間隔の小さいICチツプ5でも確実かつ正確に実
装することができる。In the above structure, the wiring board 10 can be mounted by mounting the IC chip 5 to be mounted so as to be fitted into the opening 11A of the resist film 11 provided at the mounting position. Therefore, the bumps 6 formed on the respective pads of the IC chip 5 can be reliably brought into contact with and bonded to the corresponding land 3 regardless of the height thereof or the thickness of the resist film 11.
Even the IC chip 5 having a small pad interval can be mounted surely and accurately.
【0012】実際上例えばバンプ6として金スタツドバ
ンプを用いた場合、ICチツプ5のパツドピツチが150
〔μm 〕以下になると、従来の配線基板1(図3)では
ICチツプ5を実装する際、ICチツプ5下側のレジス
ト膜4(厚み約20〔μm 〕)によつて当該ICチツプ5
を確実に実装し難い(すなわちICチツプ5の各パツド
に形成されたバンプ5をそれぞれ配線基板1の対応する
ランド3に接触させ、接合させ難い)ことが実験により
確認されていたが、この実施例の配線基板10ではこの
ようなICチツプ5でも確実かつ正確に実装することが
できる。In practice, for example, when a gold stud bump is used as the bump 6, the pad pitch of the IC chip 5 is 150.
When the thickness is less than [μm], when the IC chip 5 is mounted in the conventional wiring board 1 (FIG. 3), the resist film 4 (thickness of about 20 [μm]) below the IC chip 5 allows the IC chip 5 to be removed.
It has been confirmed by an experiment that it is difficult to surely mount (that is, it is difficult to bring the bumps 5 formed on each pad of the IC chip 5 into contact with the corresponding lands 3 of the wiring board 1 to join them). In the wiring board 10 of the example, such an IC chip 5 can be mounted surely and accurately.
【0013】以上の構成によれば、基板2上に被着する
レジスト膜11に対して、ICチツプ5の実装位置に当
該ICチツプ5の基板2との対向面とほぼ同等の大きさ
の開口部11Aを形成するようにしたことにより、パツ
ド間隔の小さいICチツプ5でも確実に実装することが
でき、かくして電極間隔の狭いICチツプの実装に対応
し得る配線基板を実現できる。According to the above structure, an opening having a size substantially equal to the surface of the IC chip 5 facing the substrate 2 is formed at the mounting position of the IC chip 5 on the resist film 11 deposited on the substrate 2. By forming the portion 11A, the IC chip 5 having a small pad interval can be surely mounted, and thus a wiring board that can be mounted to the IC chip having a narrow electrode interval can be realized.
【0014】なお上述の実施例においては、基板2上に
被着されるレジスト膜11に対して、ICチツプ5の実
装位置に当該ICチツプ5の基板2との対向面とほぼ同
等の大きさの開口部11Aを設けるようにした場合につ
いて述べたが、本発明はこれに限らず、要は、実装対象
の半導体チツプを完全に嵌め込み得るように半導体チツ
プの基板との対向面よりも大きい開口部を設けるのであ
れば、レジスト膜11の開口部11Aの大きさとしては
ICチツプ5の基板2との対向面とほぼ同等の大きさ以
外であつても良い。In the above-described embodiment, the size of the resist film 11 deposited on the substrate 2 is substantially the same as the surface of the IC chip 5 facing the substrate 2 at the mounting position of the IC chip 5. However, the present invention is not limited to this, and the point is that an opening larger than the surface of the semiconductor chip facing the substrate can be completely fitted into the semiconductor chip to be mounted. If a portion is provided, the size of the opening 11A of the resist film 11 may be other than substantially the same size as the surface of the IC chip 5 facing the substrate 2.
【0015】[0015]
【発明の効果】上述のように本発明によれば、配線基板
の基板上に被着されるレジスト膜に対して、半導体チツ
プの実装位置に当該半導体チツプの基板との対向面とほ
ぼ同等又は当該対向面よりも大きい開口部を設けるよう
にしたことにより、半導体チツプの各電極と、これら各
電極にそれぞれ対応させて基板に設けられた各電極とを
バンプの高さや、レジスト膜の高さに関わりなくバンプ
を介して確実に接合させることができ、かくして電極間
ピツチの狭いICチツプの実装に対応し得る配線基板を
実現できる。As described above, according to the present invention, with respect to the resist film deposited on the substrate of the wiring substrate, the mounting position of the semiconductor chip is almost the same as the surface of the semiconductor chip facing the substrate or By providing an opening larger than the facing surface, each electrode of the semiconductor chip and each electrode provided on the substrate corresponding to each of these electrodes are provided with bump heights and resist film heights. Regardless of this, it is possible to surely bond the bumps via the bumps, and thus it is possible to realize a wiring board which can be mounted on an IC chip having a narrow pitch between electrodes.
【図1】実施例によるフリツプチツプ実装用の配線基板
の構成を示す上面図である。FIG. 1 is a top view showing a configuration of a wiring board for flip-chip mounting according to an embodiment.
【図2】図1の配線基板上にICチツプを実装したとき
のようすを示す断面図である。FIG. 2 is a cross-sectional view showing how an IC chip is mounted on the wiring board shown in FIG.
【図3】従来のフリツプチツプ実装用の配線基板の構成
を示す上面図である。FIG. 3 is a top view showing a configuration of a conventional wiring board for flip-chip mounting.
【図4】図3の配線基板上にICチツプを実装したとき
のようすを示す断面図である。FIG. 4 is a cross-sectional view showing how an IC chip is mounted on the wiring board shown in FIG.
2……基板、3……ランド、5……ICチツプ、6……
バンプ、10……配線基板、11……レジスト膜、11
A……開口部。2 ... Board, 3 ... Land, 5 ... IC chip, 6 ...
Bump, 10 ... Wiring board, 11 ... Resist film, 11
A: Opening.
Claims (2)
ぞれ対応させて一面にランドが形成された基板と、上記
基板の上記一面上に被着された絶縁材からなるレジスト
膜とを有し、上記半導体チツプの上記電極を上記基板の
対応する上記ランドにバンプを介して接合するようにし
て上記半導体チツプを実装する配線基板において、 上記レジスト膜に対して、上記半導体チツプの実装位置
に上記半導体チツプの上記基板との対向面とほぼ同等又
は当該対向面よりも大きい開口部を設けるようにしたこ
とを特徴とする配線基板。1. A substrate having a land formed on one surface corresponding to electrode positions of a semiconductor chip to be mounted, and a resist film made of an insulating material deposited on the one surface of the substrate, In a wiring board for mounting the semiconductor chip by bonding the electrodes of the semiconductor chip to the corresponding lands of the substrate via bumps, the semiconductor is mounted at the mounting position of the semiconductor chip with respect to the resist film. A wiring board having an opening substantially equal to or larger than the surface of the chip facing the substrate.
以下でなることを特徴とする請求項1に記載の配線基
板。2. The bump is a gold-stud bump, and the semiconductor chip has a pitch of the electrode of 150 [μm].
The wiring board according to claim 1, wherein:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12896595A JPH08307045A (en) | 1995-04-28 | 1995-04-28 | Wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12896595A JPH08307045A (en) | 1995-04-28 | 1995-04-28 | Wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08307045A true JPH08307045A (en) | 1996-11-22 |
Family
ID=14997800
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12896595A Abandoned JPH08307045A (en) | 1995-04-28 | 1995-04-28 | Wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH08307045A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021171671A1 (en) * | 2020-02-27 | 2021-09-02 | 株式会社村田製作所 | Ic module and method for manufacturing ic module |
-
1995
- 1995-04-28 JP JP12896595A patent/JPH08307045A/en not_active Abandoned
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021171671A1 (en) * | 2020-02-27 | 2021-09-02 | 株式会社村田製作所 | Ic module and method for manufacturing ic module |
JP7001211B1 (en) * | 2020-02-27 | 2022-01-19 | 株式会社村田製作所 | IC module and IC module manufacturing method |
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