JPS62266851A - Forming method for solder bump electrode - Google Patents

Forming method for solder bump electrode

Info

Publication number
JPS62266851A
JPS62266851A JP61111412A JP11141286A JPS62266851A JP S62266851 A JPS62266851 A JP S62266851A JP 61111412 A JP61111412 A JP 61111412A JP 11141286 A JP11141286 A JP 11141286A JP S62266851 A JPS62266851 A JP S62266851A
Authority
JP
Japan
Prior art keywords
electrode
dry film
film resist
solder
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61111412A
Other languages
Japanese (ja)
Inventor
Yoshifumi Moriyama
森山 好文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61111412A priority Critical patent/JPS62266851A/en
Publication of JPS62266851A publication Critical patent/JPS62266851A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To form solder bump electrodes on a wafer substrate at a relatively narrow pitch interval, by including a patterning process, by which an opening part is provided on an aluminum electrode on a wafer substrate, an electrolytic plating process, by which a solder layer is grown, and a removing process of dry film resist. CONSTITUTION:A barrier metal 4 is formed on an aluminum pad electrode 2 on a wafer substrate 1. Dry film resist 6 is further laminated and developed. Thereafter, with the barrier metal 4 as an electrode, electrolytic plating is performed. As the dry film resist 6, the material having the thickness of about 25mum or more is used. On the aluminum pad electrode 2, a solder pad electrode 5 having the thickness of about 25mum or more is grown. The dry film resist 6 is separated, and the extra barrier metal material is etched away. When fused molding process (wet back) process is performed in accordance with ordinary processes, a semi-spherical solder bump electrode 5 can be obtained. The pitch interval between the bump electrodes can be made very narrow.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半田バンブ電極の形成方法に関し、特にフリッ
プチップ用半田バンプ電極の形成に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming a solder bump electrode, and particularly to a method for forming a solder bump electrode for a flip chip.

〔従来の技術〕[Conventional technology]

従来、半田メッキ法による半田バンブ電極の形成方法で
はメツキレシストとして液状レジストが用いられて米た
Conventionally, in a method of forming a solder bump electrode by a solder plating method, a liquid resist has been used as a metal resist.

第2図(a)〜(C1は従来の半田バング電極の形成方
法を示すもので、ワエハ基板1上のアルミ・バット電極
2上VCは1ずバリア・メタル層4が設けられ、ついで
液状レジスト7のパターニングエ[を経て半田バンブ電
極5が電解メッキ法により形成される。この際、バット
電極2の形成領域を大きくはみ出した半田バンブ電極5
は第2図(blに示すようにレジスト剥離およびバリア
・メタルのエツチング除去工8を終えた後溶融成形され
、第2図(C)の如き所望のバンプ高嘔ヲもつ半球状の
ものに整形される。
FIGS. 2(a) to (C1) show a conventional method of forming solder bang electrodes, in which VC is first provided with a barrier metal layer 4 on an aluminum butt electrode 2 on a wafer substrate 1, and then a liquid resist is formed on the aluminum butt electrode 2. After the patterning step 7, the solder bump electrode 5 is formed by electrolytic plating.
As shown in Fig. 2 (bl), after completing the resist stripping and barrier metal etching removal process 8, it is melt-molded and shaped into a hemispherical shape with the desired bump height as shown in Fig. 2 (C). be done.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、この従来の半田バンプの形成方法では、
液状レジスト7が使用されているのでレジスト膜厚を大
さくとることが難しく、通常はたかだか数μm程度の膜
厚条件で使用される。−・投に液状レジストは約20μ
m の膜厚までは塗布することもパターニングすること
も可能とされているが、実際にはグリベーク前の液ダレ
等の影響によって膜厚を均一に形成することが難しく、
また、パターン精度も低下するので、20μm厚以上の
膜厚に形成することは通常行なわれない。従って、約3
〜5μmの膜厚に塗布した場合を考えると、電解メッキ
によシ形成でれる半田は全ての方向に等しく成長する性
質を有するので、いま、メッキ半田層の庫を30〜70
μmに形成しようとすると、アのとなる。すなわち、半
田バンブ電極のピッチ間隔を狭めたい場合には、この半
田層7の横方向の広がりは大きな障讐となる。液状レジ
ストはその個有の性質としてパターン形成プロセス中に
は必ずプリベーク工程を挿入する必要があるので液状レ
ジストを使用する限りピッチ間隔の狭い半田バンブ電極
を形成することははとんど不可能となる。
However, in this conventional method of forming solder bumps,
Since the liquid resist 7 is used, it is difficult to increase the resist film thickness, and the resist film is normally used with a film thickness of several μm at most. -・Liquid resist is approximately 20μ
It is said that it is possible to coat and pattern a film up to a thickness of m, but in reality it is difficult to form a film with a uniform thickness due to the effects of liquid dripping before gribake, etc.
Furthermore, since the pattern accuracy also decreases, it is usually not possible to form a film with a thickness of 20 μm or more. Therefore, about 3
Considering the case where the coating is applied to a film thickness of ~5 μm, the solder formed by electrolytic plating has the property of growing equally in all directions, so the thickness of the plated solder layer is 30 to 70 μm.
If you try to form it to μm, it will become as shown in A. That is, when it is desired to narrow the pitch interval of the solder bump electrodes, the lateral spread of the solder layer 7 becomes a major obstacle. As a unique property of liquid resist, it is necessary to insert a pre-bake step during the pattern formation process, so as long as liquid resist is used, it is almost impossible to form solder bump electrodes with narrow pitch intervals. Become.

本発明の目的は、上記の情況に鑑み、半田バンブ電極を
比較的狭いピッチ間隔を以ってウニへ基板上に形成し得
る半田バンブ電極の形成方法を提供することである。
SUMMARY OF THE INVENTION In view of the above-mentioned circumstances, an object of the present invention is to provide a method for forming solder bump electrodes that can form solder bump electrodes on a substrate at relatively narrow pitch intervals.

〔問題点を解決するための手段〕 本発明のバンブ電極の形成方法は、ウェハ基板のアルミ
・バンド!極上に開口部を設けるドライ・フィルム・レ
ジストのパターニング工程ト、前記ドライ、フィルム・
レジストを介し前記アルミ・パッド′に穢土に半田層を
成長せしめる電解メッキ工程と、前記ドライ・フィルム
・レジストt−’7エハ基板上から除去するレジスト除
去工程とを含む。
[Means for Solving the Problems] The method for forming bump electrodes of the present invention is based on an aluminum band of a wafer substrate! Dry film resist patterning process with openings at the top;
The process includes an electrolytic plating process in which a solder layer is grown on the aluminum pad' through a resist, and a resist removal process in which the dry film resist is removed from the T-'7 wafer substrate.

すなわち1本発明によtLは半田の電解メツ中工程にお
けるレジストには、従来の液体レジストに代えてドライ
・フィルム・レジストが使用される。
That is, according to the present invention, a dry film resist is used in place of the conventional liquid resist for the resist during the soldering electrolytic process.

〔実施例〕〔Example〕

以下、図面を参照して本発明の詳細な説明する。 Hereinafter, the present invention will be described in detail with reference to the drawings.

第1図(al〜(C1は本発明の一実施例を示す工程順
序図である。まず第1図(alに示すようにワエハl基
板1のアルミパッド電極2上にバリアメタル4全形成し
、更にドライ・フィルム・レジスト6をラミネートして
現像した後、バリアメタル4を電極として電解メッキが
施される。ここで、ドライフィルムレジスト6には約2
5μm 以上の膜厚のものを使用する。ただし、その稚
類には水溶性形なたけ済剤形のどちらを使用してもよい
。かくしてアルミ・パッド′j1.極2上には約25μ
m 以上の半田パッド電極5が成長される。
FIG. 1(al~(C1) is a process sequence diagram showing one embodiment of the present invention. First, as shown in FIG. 1(al), the barrier metal 4 is entirely formed on the aluminum pad electrode 2 of the wafer l substrate 1. After further laminating and developing a dry film resist 6, electrolytic plating is performed using the barrier metal 4 as an electrode.
Use a film with a thickness of 5 μm or more. However, either the water-soluble form or the ready-to-drink form may be used for the young. Thus the aluminum pad'j1. Approximately 25μ on pole 2
m or more solder pad electrodes 5 are grown.

エツチングして除去し、更VC通常の工程に従い溶融B
Z形(ワエット・バック)工程を行えは、第1図(C1
の如き半球状の半田バンク電極5を得ることができる。
Etch to remove and further VC melt B according to normal process.
To perform the Z-shaped (waet-back) process, see Figure 1 (C1
A hemispherical solder bank electrode 5 can be obtained.

本発明ではこの最後の溶融成形工程ヲ行なわすとも第1
図(blの工程で残でれた半田バンブ電極5の高さは少
くとも25μm はあるのでこの!!まの形状で光分便
用することも可能である。
In the present invention, this last melt-forming step is carried out in the first step.
Since the height of the solder bump electrode 5 left in the process of Fig. BL is at least 25 μm, it is also possible to use the shape shown in Fig. 1 for optical separation.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように本発明によt″Lは、従来の
液状レジストに代わシトライフイルムレシストが半田メ
ッキ用のレジストとして用いられているので、レジスト
の膜厚を格段に厚膜とすることができ、半田材ヶ縦方向
にのみ成長させて横方向の広がりを押づえることができ
るので、バンブ電極のピッチ間隔をきわめて狭く形成す
ることが可能である。
As explained in detail above, in accordance with the present invention, t''L is achieved by using Citrifilm resist as a resist for solder plating instead of the conventional liquid resist, so that the film thickness of the resist can be made much thicker. Since the solder material can be grown only in the vertical direction and its spread in the lateral direction can be suppressed, it is possible to form the pitch of the bump electrodes to be extremely narrow.

この際、ドライ・フィルム・レジスト6は50μm以上
の膜厚であってもパターニングすること可能であるので
、溶融成形を行なわすとも50μm以上のバンブ電極を
形成することも可能となり、必要に応じ特別な用途に応
じることができる。
At this time, since the dry film resist 6 can be patterned even if it has a thickness of 50 μm or more, it is also possible to form bump electrodes with a thickness of 50 μm or more by melt molding. It can be used for various purposes.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(at〜(C)は不発明の一実施例を示す工程順
序図、第2図(al〜(C)は従来の半田バンブ電極の
形成方法の代表的工程に1(序口である。 1・・・・・・ウェハーf基板、2・・・・・・アルミ
パッド電極、3・・・・・・パッシベーション膜、4・
・・・・・バリアメタル層、5・・・・・・半田バンブ
電極、6・・・・・・ドライ・フィルム・レジスト、7
・・・・・・液状レジスト。 (C) 第 1 回
FIG. 1 (at to (C)) is a process sequence diagram showing an embodiment of the invention, and FIG. 1... Wafer f substrate, 2... Aluminum pad electrode, 3... Passivation film, 4...
... Barrier metal layer, 5 ... Solder bump electrode, 6 ... Dry film resist, 7
...Liquid resist. (C) 1st session

Claims (1)

【特許請求の範囲】[Claims] ウェハ基板のアルミ・パッド電極上に開口部を設けるド
ライ・フィルム・レジストのパターニング工程と、前記
ドライ・フィルム・レジストを介し前記アルミ・パッド
電極上に半田層を成長せしめる電解メッキ工程と、前記
ドライ・フィルム・レジストをウェハ基板上から除去す
るレジスト除去工程とを含むことを特徴とする半田バン
プ電極の形成方法。
a dry film resist patterning process for forming openings on the aluminum pad electrodes of the wafer substrate; an electrolytic plating process for growing a solder layer on the aluminum pad electrodes through the dry film resist; - A method for forming a solder bump electrode, comprising a resist removal step of removing a film resist from a wafer substrate.
JP61111412A 1986-05-14 1986-05-14 Forming method for solder bump electrode Pending JPS62266851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61111412A JPS62266851A (en) 1986-05-14 1986-05-14 Forming method for solder bump electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61111412A JPS62266851A (en) 1986-05-14 1986-05-14 Forming method for solder bump electrode

Publications (1)

Publication Number Publication Date
JPS62266851A true JPS62266851A (en) 1987-11-19

Family

ID=14560505

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61111412A Pending JPS62266851A (en) 1986-05-14 1986-05-14 Forming method for solder bump electrode

Country Status (1)

Country Link
JP (1) JPS62266851A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6417449A (en) * 1987-07-10 1989-01-20 Fuji Electric Co Ltd Formation of bump electrode of semiconductor device
JPH02244722A (en) * 1989-03-17 1990-09-28 Casio Comput Co Ltd Forming method for bump electrode of semiconductor element
JPH0346233A (en) * 1989-07-13 1991-02-27 Sharp Corp Manufacture of bump
EP0655779A1 (en) * 1993-11-26 1995-05-31 Delco Electronics Corporation Method of forming solder bumps on an integrated circuit flip chip
US6461953B1 (en) 1998-08-10 2002-10-08 Fujitsu Limited Solder bump forming method, electronic component mounting method, and electronic component mounting structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6417449A (en) * 1987-07-10 1989-01-20 Fuji Electric Co Ltd Formation of bump electrode of semiconductor device
JPH02244722A (en) * 1989-03-17 1990-09-28 Casio Comput Co Ltd Forming method for bump electrode of semiconductor element
JPH0346233A (en) * 1989-07-13 1991-02-27 Sharp Corp Manufacture of bump
EP0655779A1 (en) * 1993-11-26 1995-05-31 Delco Electronics Corporation Method of forming solder bumps on an integrated circuit flip chip
US6461953B1 (en) 1998-08-10 2002-10-08 Fujitsu Limited Solder bump forming method, electronic component mounting method, and electronic component mounting structure

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