JPS6226542A - Pipeline system instruction processor - Google Patents

Abstract

PURPOSE:To execute a processing at a high speed by performing in parallel the first and the second operand processings by plural operand obtaining mechanisms, inhibiting an obtaining processing of each operand in response to a detection of the prescribed condition of the second operand, and starting a cyle for executing a processing which follows said inhibition. CONSTITUTION:Read-out of the first and the second operands of the translation test instruction of an instruction register 100 is opertaed asynchronously and independently by incrementers 110, 111, adders 130, 131, BSs 150, 151, aligners 160, 161, and operand buffers 170, 171, and the second operand byte is decided to be zero by an arithmetic unit 180. When non-zero byte is detected by the unit 180, its signal is sent to an end deciding circuit 400, the address calculation of the following first operand and read-out of the operand are inhibited, and also the address calculation of the following second operand and read-out of the operand are inhibited.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data processing device that executes instructions in a pipeline control manner, and in particular, in this type of device, translation testing ('l'ranslate and test) is performed.
It relates to a mechanism for processing specific types of instructions represented by instructions.

[Background of the invention]

The processing of a translation test instruction basically consists of reading successive bytes of the first operand from the first operand address specified by the instruction, and reading each byte of the first operand thus obtained and the second operand specified by the instruction. The process of reading successive bytes of the second operand from the address given by the sum with the address, and checking whether each byte of the second operand thus obtained is zero, and if it is zero, proceeding to processing the next byte. If it is not zero, write the value and address of the second operand byte to the general-purpose register, and
It consists of the process of setting a condition code according to the processing situation and aborting the execution of the instruction.

FIG. 2 shows an outline of a conventional instruction processing device.

A translation test instruction is set in the instruction register 10. The B1 and B2 fields specify general registers that hold the base addresses for the first and second operand addresses, respectively, and the B1 and B2 fields indicate the possible displacement values for the first and second operand addresses, respectively. Processing of this instruction is performed as follows.

First, selectors 20 and 21 select Bl, respectively.

Select Dl, and use the selector 22 to set the increment value (
0'') and calculates the first operand address by the adder 13.The calculated address value is stored in the buffer storage (BS) in order to read the first operand.
) Sent to 15.

N bytes of data are read from B515 at a time, and the n bytes of first operand data thus read are:
The data is stored in the operand buffer 17. Next, the 1-byte extraction circuit 23 extracts the first byte from the operand buffer 17 and outputs it to the signal line 52.

Next, selectors 20, 21, and 22 select B2. D
, 2. The signal line 52 is selected and the adder 13 calculates the second operand address. B according to the calculated address
The first byte of the second operand is read from 515 and stored in the operand buffer 17. This byte is then transferred from the operand buffer 17 to the arithmetic unit 18.

The arithmetic unit 18 determines whether this byte is zero or not,
If it is zero, the 1-byte extraction circuit 23 extracts the next 1 byte of the first operand, inputs it to the adder 13,
Calculate the address of the next second operand byte. At this time, selectors 20°, 21.22 are set to B2. D2
．． The signal line 52 remains selected. The second operand byte read by B515 using this newly calculated address is sent to the arithmetic unit 18 in the same manner as described above, and is determined whether it is zero or not. Specified operand length (
The above operation is repeated until L) is exceeded or the read second operand byte becomes non-zero.

If a zero determination is made for all of the specified operand lengths, the processing status is set to the condition code and the instruction processing is terminated. In this case, general-purpose registers are not rewritten. On the other hand, if a non-zero second operand byte is read, the condition code is set and the address and value of this second operand byte are written to a general-purpose register, and subsequent reads of the first and second operand bytes are executed. Suppress and terminate the instruction.

FIG. 3 shows this instruction processing in terms of the processing stages of each cycle of the pipeline. In FIG. 3, D, A, L, E, and P each represent an instruction processing stage in the pipeline system. D is an instruction decode stage which decodes the instruction in the instruction register 10, generates information necessary for processing this instruction, and performs address calculation necessary for reading the memory operand of this instruction in an address adder 13. . In the A stage, based on the operand address calculated in the D stage, B51
The operand is read from 5 and stored in the operand buffer 17 at the L stage. In the E stage, calculation unit 1
8 performs arithmetic processing, and the result of the arithmetic operation is transferred to the P stage and stored in a general-purpose register.

In Figure 3, the address of the first operand is added in the first cycle, and the address of the first byte of the second operand is added in the fourth cycle using the first byte of the first operand read in the third cycle. , the first byte of the second operand is read in the sixth cycle, and the read first byte of the second operand is determined to be zero in the E stage of the seventh cycle.Since it is zero, the second operand is read in the eighth cycle. The address of the second byte of is added. After repeating this operation, a non-zero second operand byte was detected at the E stage of the 23rd cycle, so a condition code was set according to the processing situation at that time, and this non-zero byte was detected at the P stage of the 24th cycle. writes the address of the second operand byte and its value to the general-purpose register. At this point, the processing of this translation test command is finished, and the second
Processing of the next instruction can be started in the 5th cycle.

As can be seen from the above explanation, the address calculation and operand reading of the next second operand byte cannot be performed until the zero determination of the % capacity cylinder 2 operand byte is performed, and therefore the processing of the second operand is performed in 4 cycle pitch. This can only be done by Furthermore, when the first n bytes of the first operand read out are exhausted, it becomes necessary to read out the subsequent byte group of the first operand anew.

It is possible to speed up the processing of translation test instructions by providing two sets of mechanisms for address calculation and operand reading, and reading the first and second operands in parallel. There is a problem with the processing when a non-zero operand byte is detected. That is, when a non-zero operand byte is detected, it is necessary to write the value and address of this non-zero operand byte into a general-purpose register in addition to inhibiting subsequent reading of the first and second operand bytes. However, if you try to start writing to a general-purpose register at the stage where a non-zero operand byte is detected, a step is required to determine whether writing to the general-purpose register is necessary, and this step is required even if the operand byte is zero. Therefore, each calculation stage cannot be accommodated in one cycle.

[Purpose of the invention]

An object of the present invention is to perform the reading of the first operand byte and the reading and determination of the second operand byte in parallel in the processing of translation test instructions and instructions of the same type as the same, and to condition the processing at each calculation stage. The objective is to achieve as high a processing speed as possible for only the determination.

[Summary of the invention]

In addition to performing the processing of the first and second operands in parallel by a plurality of operand acquisition mechanisms, the present invention provides the following features:
In response to detecting that the second operand satisfies a predetermined condition (e.g., the presence of a non-zero operand byte), the processing for obtaining each operand is suppressed and the predetermined processing for reading it (e.g., writing to a general-purpose register) is performed. ) starts a series of processing cycles for execution. This leads to life.

During the instruction processing period, the arithmetic stage only needs to make a determination on a predetermined condition (for example, zero determination), so it is always completed in one cycle, and therefore the speed-up effect of the parallel processing described above is maximized.

[Embodiments of the invention]

FIG. 1 shows a schematic configuration of an instruction processing device according to the present invention. In processing an instruction requiring two memory operands, this device includes an adder for calculating the address of each operand; It has independent buffer storage, and the first and second operands can be read out independently using completely separate circuits. Incrementer 110°111, adder 130, 131 . B5150゜151, aligners 160, 161, and operand buffers 170, 171 are each provided with two sides, and each circuit indicated by +1 is used for address calculation and data reading of the first operand, and address calculation and data reading of the second operand. Each circuit indicated by +2 is used for data reading.

This instruction processing device has two types of operating modes. That is,
A case where the first operand read circuit (+1) and the second operand read circuit (+2) operate synchronously with each other;
This is a case where both operate completely asynchronously and independently. For example, when an instruction requiring two storage operands is set in the instruction register 100, the synchronous operation calculates the addresses of the first and second operands and reads the operands, respectively. Refers to operations that are executed synchronously and simultaneously using each of the two circuits.

In the present invention, the synchronous operation is not directly related, so a detailed explanation will be omitted.

Next, asynchronous operation will be explained. Consider a case where a translation test instruction is set in the instruction register 100 of FIG. At this time, as in the case of synchronous operation, the adder hand 113
0. BS+1150. Ally+1160. The operand buffer +1170 is used for calculating the address of the first operand and reading the operand, and the adder +1170 is used for calculating the address of the first operand and reading the operand.
．． BS+215'l, aligner $2161. The operand buffer analyzer 2171 is used for calculating the address of the second operand and reading the operand.

In the asynchronous operation, first, adder+1130 calculates the start address of the first operand (increment value=0), and reads the first byte of the first operand from BS+1 150. The read data is sent to the aligner 116
After being aligned by 0 so that it can be used for the subsequent address calculation of the second operand, it is stored in the operand buffer analyzer 1170. The above operation is performed in a pipelined manner regardless of whether operand address calculation or operand reading of the corresponding second operand has started, and regardless of whether or not the second operand is determined to be zero. Overlapping processing is possible. Therefore, address calculation can be performed one after another by the adder≠1130 for successive bytes after the second of the first operand, and the address can be read out. During this time, the value of increment/re+1110 is increased by 1, 1, 2, and so on.

On the other hand, recognizing that the read data of the first operand is stored in the operand buffer analyzer 1170, the selector 220 selects the 1 byte read from the operand buffer ≠1170.

Adder 2131 calculates the operand address of the second operand. One byte of the second operand is read using the address thus calculated and stored in the operand buffer analyzer 2171.

Thereafter, the second operand byte read from the operand buffer +2171 is transferred to the arithmetic unit 180, and a zero determination is made. If the result of the determination is that the byte is zero, the next byte is stored in the operand buffer +2171. Read from.

In this way, the reading of the first operand byte, the reading of the second operand byte, and the zero determination of the second operand byte are successively processed one after another, and Figure 4 shows the flow of the processing. . Here, DI, AI,
L+ is a processing stage required to read the first operand byte, and h D21 A21 L21 E2 is a processing stage required to read the second operand byte and make a zero determination. In the E2 stage, only zero determination is performed. As a result, as shown in FIG. 4, the zero determination of the second operand byte can be performed at one cycle pitch.

Next, consider a case where the arithmetic unit 180 detects a non-zero byte. When the arithmetic unit 180 detects a non-zero byte, it notifies the termination determination circuit 400 via the signal line 300. FIG. 5 shows the configuration of the end determination circuit 400. The translation test instruction ends instruction processing when all bytes of the specified operand are determined to be zero, or when a non-zero byte is detected. register 401
The operand length (L) specified by the instruction is set in , and is subtracted by 1 by the subtracter 403 each time one byte is processed. The contents of register 401 are set to a predetermined value (usually "
When the comparator 404 detects that O
From the R circuit 405 through the AND circuit 406, the register 4
After the timing is adjusted at step 02, an instruction to end the command processing is issued through the signal line 310. On the other hand, when the signal line 300 notifies the detection of a non-zero byte, it passes directly through the OR circuit 405 and the AND circuit 406. A termination instruction is output to the signal line 310 via the register 402. The signal line 50 is a command decode signal and enables a termination instruction according to the command.

When the signal line 310 instructing the end of instruction processing is set, subsequent address calculation of the first operand and operand reading are immediately inhibited. This signal is also stored in a buffer 410 that corresponds in timing to the operand buffer analyzer 1170, and the termination instruction outputted from the buffer 410 to the signal line 320 inhibits subsequent second operand address calculation and operand reading. Signal line 3
The signal No. 20 is also temporarily held in a buffer 420 that corresponds in timing to the operand buffer $2171, and then
It is read out and sent to the arithmetic unit 180 via the signal line 330. In this way.

Processing of each operand is inhibited in turn.

FIG. 6 shows the structure of the end determination section of the arithmetic unit 180. The comparator 181 performs a zero determination on the second operand byte input through the signal line 360, and when a non-zero byte is detected, the signal line 300 determines whether the second operand byte is zero or not.
At the same time, the value of this non-zero byte and its address are stored in the finalization processing circuit 182. Thereafter, the termination instruction signal issued by the termination determination circuit 400 is transmitted to the buffer 4.
20 to the signal line 330, the termination processing circuit 18
2 generates write data and a write signal to the general-purpose register 120, and at the same time writes to the general-purpose register 120 through the signal line 340, a non-zero byte is detected.

The processing status at high times is set in a condition code and output via the signal line 350. In FIG. 6, 183 to 185 indicate registers necessary for timing adjustment.

FIG. 4 shows termination processing due to detection of a non-zero byte. That is, the first operand byte whose address was calculated in the third cycle and read out in the fourth and fifth cycles is used to calculate the address of the second operand byte in the sixth cycle, and from the address thus obtained, the first operand byte is read out in the fourth and fifth cycles.
, the second operand byte read in eight cycles was determined to be zero in the ninth cycle, and was detected to be non-zero. As a result, an end cycle is generated in the 10th cycle, and operand processing after the 11th cycle is inhibited. When the termination cycle enters processing stage P2, the necessary information is written to general purpose registers.

And a condition code is set.

In this way, by generating a new end cycle and then writing to the general-purpose register and setting the condition code, the arithmetic unit 1
80 only needs to perform a zero determination, and in the end cycle only needs to write to a general-purpose register and set a condition code.

As a result, the arithmetic processing stage (E2 stage in FIG. 4) of the pipeline is completed in a short time, and successive bytes can be processed at one cycle pitch.

The present invention is applicable not only to translation test instructions but also to the same type of processing as that, in which the second operand is read using an address calculated from the data read from the first operand address and the second operand address. 2nd opera °
The present invention can equally be applied to a type of processing that executes a predetermined process and ends when the value of the command satisfies a predetermined condition. For example, multiple table search processing can be specified using this type of command.

〔Effect of the invention〕

According to the present invention, in processing a translation test type instruction,
The acquisition processing of the first operand and the acquisition processing and determination processing of the second operand can be performed in parallel at one cycle pitch without waiting for the condition judgment result for the second operand, The speed improvement is noticeable.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of an instruction processing device according to the present invention, FIG. 2 is a block diagram of a conventional instruction processing device, FIG. 3 is a progress diagram of processing in a conventional instruction processing device, and FIG. FIG. 5 is a block diagram of the completion determination circuit in FIG. 1, and FIG. 6 is a block diagram of the arithmetic unit in FIG. 1. 130.131... 1st. Adder for calculating the address of the second operand, 150, 151...1st, 2nd
Buffer storage for operands, 170.17
1... 1st. Operand buffer for second operand, 180... Arithmetic unit, 400... End determination circuit %401, 402... Buffer for end instruction signal.

Claims (1)

[Claims] 1. A first operand is read based on a first reference address specified by the instruction, and a second operand is read from an address calculated using the read successive element data and a second reference address specified by the instruction. A system that operates asynchronously in a device that processes instructions that sequentially check successive element data of operands, and when the values satisfy a predetermined condition, executes a predetermined process and terminates the processing of the instruction. an operand acquisition processing section that has a plurality of sets of address calculation means and operand reading means capable of performing the acquisition processing of the first and second operands in parallel in a pipeline manner; an arithmetic unit including a determination means for detecting that the predetermined condition is met; and a calculation unit that causes the operand acquisition unit to complete the acquisition process for each operand in response to the detection output of the determination unit, and the predetermined process that follows. an instruction processing device comprising means for initiating a series of processing cycles for executing.