JPS62263672A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce a memory cell area by constituting two bits in one memory cell and by directly connecting the first and the second channel formation regions in series without interposing a semiconductor region and the like. CONSTITUTION:The memory cells M1-M4 of a mask ROM memory are provided at the intersections of a data line DL, a source line SL and each independently selected word lines W1, W2 respectively. The memory cells M1-M4 connect in series two n-channel MISFET Q which have each a separately connected gate electrode. In other words, the memory cells M1-M4 connect in series two channel formation regions which are each controlled by a separate gate electrode. Each channel formation region is set with one threshold voltage (Vth) of three threshold voltages and the information of the memory cell is written. That is, a two bit information is written since each memory cell M has two channel formation regions.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit 3A device, and particularly relates to a technique that is effective when applied to a semiconductor integrated circuit 'lP1 device having a non-volatile memory function. .

[Conventional technology]

As a semiconductor integrated circuit device with non-volatile memory function,
Mask ROM (Read Only Me+mory)
It has been known. The memory cell of the mask ROM is l[b
it: 1 MISFE that can write 1 information
It is composed of T. The mask ROM has a feature that it is easy to achieve high integration because the memory cell area can be reduced as the IMISFET becomes smaller.

Mask ROM shortens the time required to complete a product (
The following information writing method is used to reduce the amount of time required to send information.

First, an MI S FET (
memory cells). The MISFET is configured such that its source or drain region is shared with the respective source or drain regions of three other adjacent MISFETs, forming a memory cell array.

This type of mask ROM is characterized by the ability to reduce the area of isolation regions between memory cells and achieve high integration.

After the MISFET is formed, a photoresist mask is formed in which a channel formation region of the MISFET into which information is written is opened.

A predetermined impurity (
For example, boron) is introduced. By introducing this impurity, a predetermined M of the MISFET of the first threshold voltage is
The I S FET can be formed to a second threshold voltage. In other words, information can be written.

Thereafter, an interlayer insulating film is formed to cover the MISFET, and data lines and source lines are formed, thereby completing the mask ROM.

Note that a method for writing information into a mask ROM is described in Japanese Patent Application Laid-Open No. 111364/1983.

[Problem that the invention seeks to solve]

The inventor of the present invention has studied the above-mentioned high integration of the mask ROM and has found that the first problem arises.

The above-mentioned mask ROM requires a margin for mask alignment in the manufacturing process between the opening of the photoresist mask and the channel forming region in the information writing process. Although the memory cell area can be reduced with the progress of microfabrication, since a margin for mask alignment is required, there is a limit to the reduction of the memory cell area, and as a result, high integration cannot be achieved.

An object of the present invention is to provide a technique that allows high integration in a semiconductor integrated circuit '3Av1 having non-volatile storage capability.

Another object of the present invention is to provide a technique that can reduce the mask alignment allowance in the manufacturing process in the information writing process of a semiconductor integrated circuit device having nonvolatile memory.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

Outline of typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device having a non-volatile memory function, the memory cell is provided with first and second channel forming regions connected in series and on the first and second channel forming regions with a gate insulating film interposed therebetween. , each independently selected first
, the second gate fR pole, and tIu? ! 2 series t: Consists of a drain region provided at one end of the connected first and second channel forming regions, and a source region provided at the other end.

Further, after forming a first gate electrode on the first channel formation region via a gate insulating film, a second channel formation region is formed in a self-aligned manner with respect to the first gate electrode, and the second channel formation region is formed in a self-aligned manner with respect to the first gate electrode. A second gate electrode is formed on the region with a gate insulating film interposed therebetween.

[For production]

According to the above-mentioned means, 2 [b
ij], and the first. Since the second channel forming regions are directly connected in series without intervening a semiconductor region or the like, the memory cell area can be reduced.

The degree of integration can be improved.

Furthermore, since the second channel formation region is formed in a self-aligned manner with respect to the first gate electrode on the first channel formation region, when the first channel formation region and the second channel formation region having information are connected in series, , the mask alignment margin dimension in the manufacturing process can be reduced.

〔Example〕

The configuration of the present invention will be described below along with an embodiment in which the present invention is applied to a horizontal mask ROM.

In all the figures, parts having the same functions are denoted by the same reference numerals, and explanations of the edges are omitted.

FIG. 1 (equivalent circuit diagram) shows a memory cell of a mask ROM which is an embodiment of the present invention.

As shown in FIG.
M,~M41:! , Data aDL, So4aSL,
and are provided at the intersections of the independently selected word lines W + and W 2, respectively.

Memory cell MI-M4 is connected to word line W1. 2, each with a separately connected gate electrode
It is configured by connecting channel MISFETQ in series. In other words, each of the memory cells M1 to M4 is configured by connecting in series two channel forming regions controlled by separate gate electrodes.

Each channel forming region has three types of threshold voltages (
A threshold voltage of one of Vt, h) is set, and information in the memory cell is written. That is, since each memory cell M has two channel formation regions, it is configured so that 2 [bitl,] of information is written therein.

FIG. 1 shows memory cells M1 to M4 in which 2 bits of information are written.

In other words, the memory cell MI is composed of an M I S F E T Q e I having a first threshold voltage and an M I S F E T Q e 2 having a second threshold voltage. The first threshold voltage is, for example, 1
[V], enhancement type MISFET
Configure Q. The second threshold voltage is, for example, 2 [V
], an enhancement type M I S FET
Configure Q.

Memory cell M2 has two first threshold voltages~
It is composed of I I S F E T Q e I.

Memory cell M3 is a MISF having a third threshold voltage.
ETQd and M I S F having a second threshold voltage
' E T Q c 2. The third threshold voltage is, for example, −1 [V], and a depletion type M[5FETQ is formed.

Memory cell M2. is the MTS with the third threshold voltage
FETQd and an M I S having a first threshold voltage
It is composed of F ET Q e +.

When 1 is selected for the word line W1, MISF
Make E ``I' Q d conductive and M I S F
For example, O [V] that can make E T Q el non-conductive.
is applied. In addition, the word line WI has Mr 5FETQe 1. For example, 5 [■] is applied to make each of Qd conductive. This word line W+
(MISFETQ on the source line SL side) has 1MIS
FET Q, e r or Qd is to be connected. When a predetermined memory cell M is selected, other memory cells are unselected, so basically the word, VA
It is sufficient to provide a cutoff MLSFETQd on either the Wl side or the W2 side (data line DL side). However, MISFETQd is
Since the pn junction area with the substrate is larger than each of r and Q e2, the parasitic capacitance becomes larger. In other words, when it is provided on the data WDL side.

In order to prevent this from reducing the speed of the information read operation, MISFETQd is arranged on the "/-" side aSL side.

The word line W2 has M1sF E when not selected.
T Q c 1. For example, O[V] which can make each of Q c 2 non-conductive is applied. In addition, the word line W2
At the time of selection, M I S F E T Q
Make e r conductive and MIS F E T Q e
For example, 2 [v] is applied, which can make 2 into a non-conducting state.

moreover.

The word line W2 has a MISFETQ when selected.
For example, 5 [■] is applied to make each of e + and Q e 2 conductive. This word line W2 (MISFETQ on the data line DL side) has a MISFE T
Q e I or Q e 2 is connected.

For example, 3 [■] is applied to the data line DL as a precharge voltage. The source line SL has a reference voltage (
When the circuit is grounded, O[V] is applied.

The information read operation of the mask ○M configured as described above is performed according to the potential relationship shown in Table 1 listed at the end of the specification.

Next, the specific structure of this embodiment will be explained with reference to FIG. 2 (a sectional view of a main part of a memory cell of a mask ROM).

In FIG. 2, l is a P-type semiconductor substrate (or well region) made of single crystal silicon. A field insulating film 2 is formed on the main surface of the semiconductor substrate 1 between the memory cell formation regions.
, p-type channel stopper regions 3 are provided, respectively.

Each of the memory cells M1 to M4 is basically an n-channel MrS composed of a semiconductor substrate 1, a gate insulating film 4, a gate electrode 5, and an n-type semiconductor region 8 which is a source region.
FETQ, semiconductor region 1° gate insulating film 6, gate f
f1ti7, and an n-channel MISI"ETQ composed of a semiconductor region 8 of rr""1 which is a drain region.

Semiconductor substrate 1 is used as a channel formation region of MISFETQ. In one memory cell, the channel formation region under the gate electrode 5 and the channel formation region under the gate FF electrode 7 are formed without intervening a semiconductor region 8 used as a source region or a drain region, a field insulating film 2, etc. , directly.

connected in series.

Channel formation region of MISFETQd (semiconductor substrate 1)
is composed of an impurity concentration that forms a depletion type third threshold voltage.

The channel forming region of M I S F E T Q e + is an enhancement-type first threshold where a p-type impurity (for example, boron) 9 or 10 is introduced into the channel forming region of the third threshold voltage. The impurity concentration that forms the voltage value is also 1.

The channel forming region of M I S F E T Q G 2 has P-type impurities (for example, boron) 9 and 11 . in the channel forming region of the third threshold voltage. or 10 and 1
It is composed of an impurity concentration that forms an enhancement type second threshold voltage of 4 people.

Although not shown, the gate electrode 5 is constructed integrally with the word line Wl. Although not shown, the gate electrode 7 is configured integrally with the word ad2. Gate? 11
Although not labeled, tM5 and tM7 are electrically isolated with an insulating film interposed therebetween.

Is the gate electrode 5.7 a gate made of polycrystalline silicon 1if2, polycide film, high melting point all-reflective film, etc.? ! Constructed from i-pole material.

In the semiconductor region 8, which is a source region, there is a source line (S L) 14 provided in an interlayer insulating film 12 on the MISFETQ.
are connected through the connection hole 13.

An interlayer insulating film 12 is provided in the semiconductor region 8 which is the drain region.
A data line (DL) 14 provided above is connected through the connection hole 13. The source line and data line 14 are made of a wiring material such as an aluminum film, for example.

In this way, the first . a second channel forming region (semiconductor substrate 1); The independently selected gates ff1tfi5.7 are provided on the second channel forming region via the gate insulating film 4.6, and the gates ff1tfi5.7 are provided on one end side of the first and second channel forming regions connected in series. By configuring the memory cell M with the provided drain region (semiconductor region 8) and the source region (semiconductor region 8) provided on the other end side, 2 [b
it,] 'x configuration, and the first and second channel forming regions are directly connected in series without intervening the semiconductor region 8, etc., so that the area of the memory cell M can be reduced and the degree of integration can be improved. Can be done.

Next, a specific WJ manufacturing method of this embodiment will be explained using FIGS. 3 to 6 (cross-sectional views of main parts of the memory cell in each manufacturing process of the mask ROM).

First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared. In this semiconductor substrate 1, at least the main surface of the channel forming region has a third threshold voltage (for example,
−1 [V]) at an impurity concentration. That is, in the memory cells M3 to M4 formation region, each M
The channel formation region of ISFETQd is set to a third threshold voltage.

Then, a field insulating film 2 and a P-type channel stopper region 3 are sequentially formed on the main surface of the semiconductor substrate l between the memory cell M forming regions.

Thereafter, a gate insulating film 4 is formed on the soil surface of the semiconductor substrate 1 in the memory cell M formation region.

As shown in FIG. 3, a first threshold voltage (
For example, an impurity 9 forming ][V]) is introduced. The impurity 9 is, for example, boron, and is introduced through the gate insulating film 4 by ion implantation. Memory cell M+, ~
In each of the 12 formation regions, the impurity 9 is introduced in a self-aligned manner with respect to the field insulating film 2. In the memory cells M3 and M4 formation regions, when introducing the impurity 9, an impurity introduction mask indicated by the reference numeral 15 and dotted lines in FIG. 3 is formed, and the impurity 9 is not introduced. The impurity introduction mask is formed of, for example, a photoresist film.

By the step of introducing impurity 9 shown in FIG. 3, the husband's M
The channel formation region of I S F E T Q e or Q e 2 is set to the first threshold voltage.

After the step of introducing impurity 9 shown in FIG. on each channel forming region of the third threshold voltage,
A gate electrode 5 and a word aW+ formed integrally with the gate electrode 5 are formed on the gate insulating film 4.

Then, the gate insulating film 4 on the sides of the gate electrode 5 is removed (almost all of it is removed during the formation of the gate electrode 5), the gate insulating film 6 is placed on the removed part, and the insulating film covering the gate electrode 5 (the reference numerals are not included). form) respectively.

Thereafter, as shown in FIG. 4, the main surface of the semiconductor substrate 1 in each of the memory cell M3 and M4 forming regions is coated.

An impurity 10 forming a first threshold voltage is introduced. The impurity 10 is introduced through the gate insulating film 6 in substantially the same way as the introduction of the impurity 9 described above. In each of the memory cell M3 and M4 forming regions, the impurity 10 is introduced in a self-aligned manner with respect to the field insulating film 2 and the gate electrode 5. Impurity 1 is added to the memory cell M1 and M2 forming regions.
When introducing 0, an impurity introduction mask indicated by the reference numeral 16 and dotted lines in FIG. 4 is formed, and the impurity 10 is not introduced. The impurity introduction mask is formed of, for example, a photoresist film.

By the step of introducing impurity 10 shown in FIG. 4, M I
The channel formation regions of S F E T Q e I and Q e 2 are set to the first threshold voltage.

After the step of introducing the impurity 10 shown in FIG. 4, as shown in FIG. 5, a second threshold voltage (for example, 2 [V]') is introduced. The impurity 11 is introduced through the gate insulating film 6 in substantially the same way as the introduction of the impurity 10 described above. Memory cell M
+, in each of the M3 formation regions, the impurity 11
is introduced in a self-aligned manner with respect to the field insulation film 2 and the gate electrode 5. When introducing the impurity 11 into the memory cells M2 and M4 forming regions, an impurity introduction mask indicated by the reference numeral 17 and dotted lines in FIG. 5 is formed, and the impurity 11 is introduced. The impurity introduction mask is formed of, for example, a photoresist layer.

By this step of introducing impurity 11 shown in FIG. 5, in each of the memory cell M + and M 3 forming regions,
The channel forming region of M I S F' ET Q e 2 is set to the second threshold voltage.

After the step of introducing the impurity 11 shown in FIG.
A gate electrode 7 and a word line W2 integrally formed therewith are formed on the gate insulating film 6 on each channel formation region of the second threshold voltage.

Thereafter, as shown in FIG. 6, using the gate electrodes 5 and 7 and the field insulating film 2 as masks for impurity introduction, semiconductor regions 8. Semiconductor regions 8, which are drain regions, are formed on the sides of gates Rtl and 7, respectively. The semiconductor region 8 can be formed by introducing an n-type impurity (for example, arsenic) by ion implantation.

In this way, after forming the gate ttt electrode 5 on the first channel formation region (the semiconductor substrate 1 or the semiconductor substrate 1 into which the impurity 9 has been introduced) via the gate insulating film 4, the gate ttt electrode 5 is formed. −
The second channel forming region (semiconductor substrate 1 into which impurity 10 is introduced, impurities 9 and 11) is formed in a self-aligned manner with respect to electrode 5.
Semiconductor substrate introduced with 1. By forming a semiconductor substrate 1) into which impurities 10 and 11 are introduced, and forming a gate electrode 7 on the second channel forming region via the insulating film 1, the gate electrode 7 on the first channel forming region is formed. (Since the second channel forming region was formed in a self-aligned manner for the crystal 5 (each of the impurities 10 and 11 were introduced in a self-aligning manner), the first channel forming region and the second channel forming region having information were formed in a self-aligned manner. When connecting in series with , it is possible to reduce the mask alignment allowance dimension in the manufacturing process (information writing process).

The memory cell area can be reduced and the degree of integration of the mask ROM can be further improved.

Furthermore, by overlapping the gate electrode 7 on the gate electrode S, the area occupied by the gate electrodes S and 7 can be reduced, so the memory cell area can be reduced and the mask ROM
The degree of integration can be improved. Note that even if the gate electrode 7 does not overlap the gate electrode 5 due to mask misalignment during the manufacturing process, impurities forming the semiconductor region 8 are introduced between the gate electrodes 5 and 7.
1st. The second channel forming regions are electrically connected in series.

In the step of forming the semi-four-body region 8, MI S FE
TQ d, Q e 1. Memory cells M, ~M in which each of Q e 2 is formed and information is written
2 is formed.

Thereafter, as shown in FIG. 2, the interlayer insulating film 12, connection hole 13, source line, and data line 14 are sequentially formed.

By performing these series of manufacturing steps, the horizontal mask ROM of this embodiment is completed.

As above, the invention made by the present inventor has been specifically explained with reference to the above-mentioned embodiments, but the present invention is not limited to the above-mentioned embodiments, and may be modified in various ways without continuing the gist thereof. Of course you can get it.

For example, the present invention can be applied to a vertical mask ROM.

Further, the present invention can be applied to a semiconductor integrated circuit device (EP'ROM) having an ultraviolet erasable nonvolatile memory function. In other words, the memory cells of the EPROM are
, the second channel forming regions are connected in series;
A gate electrode, a floating gate electrode, and a control electrode are provided on the second channel forming region, respectively.

Furthermore, the present invention can be applied to a semiconductor integrated circuit device (EEPRO-1) having an electrically erasable nonvolatile memory function.

〔Effect of the invention〕

Among the inventions disclosed in this application, some representative ones! ) can be briefly explained as follows.

In a semiconductor integrated circuit device having a non-volatile memory function, the memory cells are connected in series. a second channel forming region; The independently selected first
, and a second gate electrode.

By configuring the drain region provided at one end of the first and second channel forming regions connected in series and the source region provided at the other end, 2 [bit, However, since the first and second channel forming regions are directly connected in series without intervening a semiconductor region or the like, the memory cell area can be reduced and the degree of integration can be improved.

Further, after forming the first gate ff1tl on the first channel forming region via a gate insulating film, the first gate t
By forming a second channel forming region in a self-aligned manner with respect to tttl and forming a second gate electrode on the second channel forming region via a gate insulating film, the first channel forming region on the first channel forming region is formed. Since the second channel forming region is formed in a self-aligned manner with respect to the gate electrode, the mask alignment margin dimension in the manufacturing process is reduced when the first channel forming region having information and the second channel forming region are connected in series. I can do it.

(Table 1) Margin below

[Brief explanation of drawings]

1 is an equivalent circuit diagram of a memory cell of a mask ROM which is an embodiment of the present invention; FIG. 2 is a cross-sectional view of a main part of a memory cell of a mask λ○M shown in FIG. 1; 6th IA is the mask RO shown in FIG.
FIG. 3 is a cross-sectional view of a main part of a memory cell of M at each manufacturing process. In the figure, 1: semiconductor substrate, 2: field insulating film. 4.6...Goo 1-insulating film, 5,7...gate electrode,
8. Semiconductor region, 12... Interlayer insulating film, 14. SL・
- Source line, 14. DL...Data line, 13...Connection hole, M, ~M4 ・Memory cell-W + , W2 ・
・Two 1- line, Q d , Q Q + , Q e 2-
MISFET.

Claims (1)

[Claims] 1. At each intersection of the data line, source line, and word line,
In a semiconductor integrated circuit device having a nonvolatile memory function and provided with a memory cell, the memory cell is provided with first and second channel forming regions connected in series, and the first and second channel forming regions are connected in series.
First and second gate electrodes connected to independently selected first and second word lines are provided on each of the second channel formation regions via a gate insulating film, and the first and second gate electrodes are connected in series. A semiconductor integrated circuit device characterized in that a drain region connected to a data line is provided at one end side of the first and second channel forming regions, and a source region connected to a source line is provided at the other end side. . 2. The semiconductor integrated circuit device according to claim 1, wherein the memory cell constitutes 2 bits of information. 3. Each of the first and second channel forming regions of the memory cell is set at one threshold voltage among three types of threshold voltages. 2. The semiconductor integrated circuit device described in 2. 4. At each intersection of the data line, source line, and word line,
In a method of manufacturing a semiconductor integrated circuit device having a nonvolatile memory function in which a memory cell is provided, the step of forming a first channel formation region having a first threshold voltage in a main surface portion of a semiconductor substrate in a memory cell formation region; forming a first gate electrode on a predetermined main surface of the first channel forming region via a gate insulating film; and forming a first gate electrode in a self-aligned manner with respect to the first gate electrode. forming a second channel forming region having a second threshold voltage equal to or different from the first threshold voltage in a first channel forming region other than the second channel forming region; and forming a first gate electrode in the second channel forming region. forming a second gate electrode on the main surface of the side part via a gate insulating film; and forming a second gate electrode on the main surface of the semiconductor substrate on one side of each of the second gate electrode and the first gate electrode. 1. A method of manufacturing a semiconductor integrated circuit device, comprising the step of forming a source region and a drain region in a self-aligned manner with respect to each other.