JP3085684B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile semiconductor memory device in which a NAND cell block is constituted by a plurality of MOS memory cells.

(Prior Art) Conventionally, as this type of NAND cell type nonvolatile semiconductor memory, there is a mask ROM in which information is fixedly written by threshold control at the time of manufacturing. FIG. 8 shows the layout of such a mask ROM, and FIG. 9 shows its layout along AA 'and BB'.
3 shows a cross section. FIG. 10 is an equivalent circuit.

In this example, a NAND cell block having _eight memory cells M _{1 to} M ₈ and two select gates Q _D1 and Q _D2 is arranged in a region surrounded by the element isolation insulating film 2 of the silicon substrate 1. . The memory cell of the NAND cell block has a half control gate 4 (4 ₁ , 4 ₃ , 4 ₅ , 4) formed on the substrate 1 by a first polycrystalline silicon film via a first gate insulating film 3 made of a thermal oxide film. ₇ )
Are formed, and the remaining control gates 6 (6 ₂ , 6 ₄ , 6 ₂₎ are formed by the second polycrystalline silicon film via the second gate insulating film 5.
6 ₆ , 6 ₈ ) are formed. Control gate of each memory cell
The word lines WL _{1 and} 4 are formed continuously in the row direction.
The ~WL _8. Gate electrodes of two select gates Q _D1 and Q _D2
4 ₉ 6 ₁₀ are respectively controlled gates 4,6 simultaneously with patterning. The gate electrode 4 ₉ 6 ₁₀ are connected to the respective selection control line SG _D1, SG _D2. For example, the drain diffusion layer 8 of each NAND cell is commonly connected to the bit line (BL) 10 for every two adjacent NAND cells. The source diffusion layer 9 is formed as a common source line SL for a plurality of NAND cells.

Focusing on two NAND cell blocks A, B adjacent shown in FIG. 10, in one of the NAND cell block A, select gate Q _D1 which is controlled by the first selection control line SG _D1 is normally-
ON type, select gate controlled by second select control line SG _D2
Q _D2 is normally-off type, in other NAND cell block B, select gate Q _D1 'is normally off type controlled by a first selection control line SG _D1, the second selection control line SG _D2 The controlled select gate Q _D2 ′ is a normally-on type. This is _achieved by two selection control lines SG _D1 and SG _D2 .
This is for selecting the AND cell blocks A and B.

The threshold voltage of each memory cell constituting the NAND cell block is changed to information “0”, “1” by selective ion implantation.
Are set so that, for example, one becomes positive and the other becomes negative.

Data reading of the mask ROM of such NAND cell type, for example, will be described as an example the case of reading the memory cell M ₆ of NAND cell block A, is as follows.
For example, 5V is applied to the selected bit line BL, the first selection control line _SGD1 is set to 0V, and the second selection control line _SGD2 is set to 5V. As a result, both the selection gates Q _D1 and Q _{D2 become} conductive, and the NAND cell block A is connected to the bit line. At this time, the other NAND cell block B is not connected to the bit line BL because the select gate Q _D1 ′ is off. The unselected word lines _{WL 1 ~WL 5, WL 7,} WL 8 is a 5V, and 0V only the selected word line WL _6. As a result, the non-selected memory cells in the NAND cell block A serves as a transfer gate, "0" of the selected memory cell M _6, or does not flow or current flowing in the bit line BL in response to the "1" is detected.

In this manner, in the mask ROM of the NAND cell type, all the sources are commonly connected, and adjacent ones controlled by the same word line are connected.
Attempting to connect the drains of NAND cells to a common bit line requires two select gates in each NAND cell block. Of the control gates, normally-on type, that is, the control gate Q on the NAND cell block A side in FIG.
_D1 and the control gate Q _D2 ′ on the NAND cell block B side are:
It is not necessary to be a transistor. However, since it is essential to dispose the two selection control lines SG _D1, SG _D2 in order to perform block selection, the space of the two transistors content needs.

(Problems to be Solved by the Invention) As described above, in the conventional NAND cell type mask ROM, two control gates are required for one NAND cell block in order to perform block selection. There was a problem that it was difficult.

Similar problems are not limited to mask ROMs, but also when a NAND cell block is configured and it is necessary to pass a current through a plurality of memory cells in the selected NAND cell block.
For example, EP using hot electron injection for writing
There is also in ROM etc.

The present invention has been made in view of the above points, and has as its object to provide a non-volatile semiconductor memory device that achieves high integration by reducing the number of select gates.

[Configuration of the Invention] (Means for Solving the Problems) The present invention relates to a nonvolatile semiconductor memory device in which a plurality of NAND cell blocks each including a plurality of MOS type memory cells are arranged in a matrix on a semiconductor substrate. Wherein the drain diffusion layers of two adjacent NAND cell blocks are connected to a common bit line directly or via a first selection gate driven by a common word line, and a NAND cell block connected to an adjacent bit line The source diffusion layers of two adjacent NAND cell blocks are connected to a common source selection line.

(Operation) In the present invention, a plurality of NAND cell blocks arranged in the word line direction share a common source diffusion layer. For example, two adjacent NAND cell blocks are connected in common to a source line. In this case, a pair of NAND cell blocks commonly connected to a source line is two adjacent NAND cell blocks whose drains are not connected to a common bit line. The drain side is connected to the bit line via a first selection gate or directly, and the adjacent source line is connected to a reference potential via second and third selection gates controlled by different control lines.

Thereby, in the memory of the present invention, the number of select gates can be significantly reduced as compared with the conventional case. In other words, while it has conventionally been necessary to provide two selection gates for each NAND cell, in the present invention, the number of selection gates on the drain side is reduced to one for each NAND cell block, or is omitted. You can do it. This is because the second and third selection gates connected to the source line are not required for each NAND cell block, but may be provided in common for a plurality of NAND cells arranged in the bit line direction.

(Example) Hereinafter, an example of the present invention will be described.

FIG. 1 is a layout of a NAND cell type mask ROM of one embodiment, and FIGS. 2 (a) and 2 (b) are A-
It is A ', BB' sectional drawing. FIG. 3 is an equivalent circuit thereof.

To explain by focusing on one NAND cell, in this embodiment, eight MOS memory cells M _{1 to} M ₈ and one MOS cell are provided in a region partitioned by the element isolation insulating film 2 of the p-type silicon substrate 1. type select gate (first selection gate) Q _D are formed. Each memory cell is controlled by the first-layer polycrystalline silicon film through a first gate insulating film 3 made of a thermal oxide film gate 4 (4 _2, 4 _4, 4 _6, 4 ₈₎ is formed on the substrate 1 further control gate 6 by the second layer polycrystalline silicon film (6 _1, 6 _3, 6 _5, 6 ₇₎ is formed through a second gate insulating film 5, is formed. Before forming the control gate, the threshold value of the memory cell is set by selectively ion-implanting each channel region in accordance with the write data “0” and “1”. For example, a memory cell of “0” has a threshold value set to a negative value, and a memory cell of “1” has a threshold value of 0 V to 5 V, for example, 2 V.
Set to about. The gate electrode 4 ₉ selection gate Q _D is, and this with the same first-layer polycrystalline silicon film and the control gate 4 of the memory cells are patterned simultaneously. The control gates 4 and 6 of the memory cells arranged in the row direction are arranged in common and become word lines WL (WL _{1 to} WL ₈ ). A drain diffusion layer 8 and a source diffusion layer 9 are formed at both ends of the NAND cell, respectively. CV on the substrate on which the elements are formed
The D wiring is covered with a D insulating film 7, a contact hole is formed in the D insulating film 7, and an Al wiring
Bits BL (BL ₁ , BL ₂ ,...) And source lines
SL (SL ₁ , SL ₂ ,...) Are configured.

Each drain diffusion layer 8 commonly formed for every two adjacent NAND cell blocks is connected to one bit line BL, and each source diffusion layer 8 commonly formed for every two adjacent NAND cell blocks is connected. Each 9 is connected to one source line SL. Here, the combination of the NAND cell blocks commonly connected to the bit line BL and the combination of the NAND cell blocks commonly connected to the source line SL are alternated. That will be described by paying attention to the four NAND cell blocks A~D in the equivalent circuit of FIG. 3, two adjacent NAND cell blocks A, the bit line drain of B via a first select gate Q _D It is commonly connected to BL _2. Adjacent NAND without being connected to a common bit line
The source sides of the cell blocks A and C and B and D are commonly connected to source lines SL ₁ and SL ₂ . The source line SL ₁ is connected to a reference potential via a second select gate Q _S1 which is controlled by the selection control line SG _S1, the source line SL ₂ next door is controlled by a separate select control line SG _S2 It is connected to the reference potential via the third selection gate _QS2 .

The operation of the NAND cell type mask ROM thus configured is as follows. Describing the case of currently selected memory cell M _6, the 5V is applied to the word line _{WL 1 ~WL 5, WL 7,} WL 8 5V, the selected bit line BL ₂ 5V, the selection control line SG _D of the drain-side ,
Selection control line SG _S1, SG _S2 on the source side, whereas the SG _S1 5V, while
Giving 0V to SG _S2, it gives 0V to the selected word line WL _6. At this time, if the memory cell M ₆ is “0”, the bit line BL ₂
Through D cell blocks A, through the source lines SL _1, current flows through further second selection gate Q _S1. Memory cell M
_{If 6} is "1", no current flows. Thus, the data of the memory cell M ₆ is determined.

In the above read operation, the drain side of the NAND cell block B is also connected to the selected bit line BL via the first selection gate.
Connect to ₂ . However, the source side of the NAND cell block B, because the third selection gate Q _S2 of the source line SL ₂ is turned off, the current is also a memory cell is driven by a selected word line WL ₆ are turned even flow Absent. Two NAND cell block thus connected to a common bit line BL ₂
A and B are selected by the selection gates Q _S1 and Q _S2 , so that only the data of the NAND cell block A is selectively read.

In this embodiment, there is only one select gate on the drain side of the NAND cell block. In order to select a block, a selection gate is provided on the source side for each source line. The source-side selection gates for performing the block selection may be provided one by one in common for a large number of NAND cell blocks arranged in the column direction, so that only a small number of cell arrays are required. Therefore, according to this embodiment, the number of select gates is significantly reduced as compared with the conventional case, and high integration of the NAND cell type mask ROM is achieved.

4 and 5 show a layout and an equivalent circuit of a NAND cell type mask ROM of another embodiment. Parts corresponding to those in the previous embodiment are denoted by the same reference numerals, and detailed description is omitted. In this embodiment, the selection gate on the drain side is omitted by setting the threshold value of both the “0” and “1” data of the memory cell to positive. For example, “0” data is the threshold
1V, and “1” data is set to the threshold value 3V.

In the case of this embodiment, at the time of reading, the unselected word line is set to 0 V, the unselected word line of the selected NAND cell block is set to 5 V,
3V is applied to the selected word line. Source side selection control line
SG _S1, SG _S2 is one 5V, while the a 0V. As a result, selective reading can be performed similarly to the previous embodiment.

Also in the previous embodiment, the bit lines BL
The selection of the NAND cell block commonly connected to the
Since carried out by the selection gates Q _S1, Q _S2, not enter the first selection gate Q _D on the drain side when viewed by the row direction. However, in the column direction, there are a plurality of
Looking at the NAND cell block, even if all the word lines of the non-selected block are set to 0V, if the memory cell data in them is all “0”, if there is no drain side select gate, the current will flow through this NAND cell block. Penetrates. Therefore, when a negative threshold value is used, the first select gate on the drain side is indispensable. On the other hand, if the thresholds of both “0” and “1” are made positive as in this embodiment,
Since the word line of the unselected block in the column direction is set to 0V and the block selection is performed without fail, the drain side select gate can be omitted.

6 and 7 are a layout and a sectional view of a NAND cell type mask ROM of still another embodiment. Parts corresponding to those in the previous embodiment are denoted by the same reference numerals, and detailed description is omitted. In this embodiment, the control gates of the memory cells in the NAND cell are not overlapped, and the control gates 4 are patterned using only one polycrystalline silicon film, and the diffusion layers 12 are formed between the memory cells. . Other 4th
This is the same as the embodiment described in FIGS.

In this embodiment, the degree of integration is lower than in the previous embodiment, but the process is simplified. This embodiment is a case where the drain side select gate is omitted, but the structure in which the select gate is provided on the drain side as in the embodiment of FIGS. Can also be formed.

The present invention is not limited to the above embodiment. For example, in the embodiments, the mask ROM is exclusively described, but the present invention can be applied to an EPROM. For example, in an EPROM in which writing is performed by hot electron injection by flowing a channel current, when the drains of NAND cells adjacent in the row direction are commonly connected to a bit line, as in the above-described embodiment, the drain-side select gate is connected. By providing a selection gate for the source line, block selection can be performed, which is useful.

In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a NAND cell type nonvolatile semiconductor memory device which achieves high integration by reducing the number of select gates.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing a NAND cell type mask ROM according to one embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are AA 'and BB' in FIG.
FIG. 3 is an equivalent circuit diagram, FIG. 4 is a layout diagram showing a NAND cell type mask ROM of another embodiment, FIG. 5 is an equivalent circuit diagram thereof, and FIG. 6 is a NAND of another embodiment. 7A and 7B are layout diagrams showing a cell type mask ROM, and FIGS. 7A and 7B are AA 'and BB' in FIG.
FIG. 8 is a layout diagram of a conventional NAND cell type mask ROM, and FIGS. 9A and 9B are AA 'and BB' of FIG.
FIG. 10 is a sectional view, and FIG. 10 is an equivalent circuit diagram. M ₁ ~M ₈ ...... memory cell, BL ...... bit lines, WL ...... word line, SL ...... source _{line, SG D, SG S1, SG} S2 ...... select control lines, Q
_D ... First select gate, Q _S1 ... Second select gate, Q
_S2 ... Third selection gate, 1... Silicon substrate, 2.
Element isolation insulating film, 3,5 ... gate insulating film, 4,6 ... control gate, 7 ... CVD insulating film, 8 ... drain diffusion layer, 9 ...
... source diffusion layer, 10 ... bit line, 11 ... source line.

Claims (3)

(57) [Claims] In a nonvolatile semiconductor memory device in which a plurality of NAND cell blocks each including a plurality of MOS type memory cells are arranged in a matrix on a semiconductor substrate, a drain diffusion of two adjacent NAND cell blocks is provided. The layers are connected to a common bit line via a first selection gate driven directly or by a common word line, and source diffusion of two adjacent NAND cell blocks among NAND cell blocks connected to adjacent bit lines A non-volatile semiconductor memory device, wherein the layers are connected to a common source selection line. 2. The non-volatile semiconductor memory device according to claim 1, wherein said MOS memory cell stores information with a fixed threshold voltage set at the time of manufacture. 3. The non-volatile semiconductor device according to claim 1, wherein adjacent source selection lines are connected to a reference potential via second and third selection gates controlled by different control lines. Memory device.