JPS62260348A - Assembly method for semiconductor device - Google Patents
Assembly method for semiconductor deviceInfo
- Publication number
- JPS62260348A JPS62260348A JP61105315A JP10531586A JPS62260348A JP S62260348 A JPS62260348 A JP S62260348A JP 61105315 A JP61105315 A JP 61105315A JP 10531586 A JP10531586 A JP 10531586A JP S62260348 A JPS62260348 A JP S62260348A
- Authority
- JP
- Japan
- Prior art keywords
- plating film
- lead frame
- boron
- resin
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000007747 plating Methods 0.000 claims abstract description 67
- 239000011347 resin Substances 0.000 claims abstract description 24
- 229920005989 resin Polymers 0.000 claims abstract description 24
- 229910000990 Ni alloy Inorganic materials 0.000 claims abstract description 21
- QDWJUBJKEHXSMT-UHFFFAOYSA-N boranylidynenickel Chemical compound [Ni]#B QDWJUBJKEHXSMT-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910001174 tin-lead alloy Inorganic materials 0.000 claims abstract description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052802 copper Inorganic materials 0.000 claims abstract description 9
- 239000010949 copper Substances 0.000 claims abstract description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052796 boron Inorganic materials 0.000 claims abstract description 5
- 238000007789 sealing Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 abstract description 8
- 239000000463 material Substances 0.000 abstract description 6
- 229910052709 silver Inorganic materials 0.000 abstract description 5
- 239000004332 silver Substances 0.000 abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 239000010931 gold Substances 0.000 abstract description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 16
- 229910052759 nickel Inorganic materials 0.000 description 8
- 230000004913 activation Effects 0.000 description 7
- 238000011282 treatment Methods 0.000 description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 229910000978 Pb alloy Inorganic materials 0.000 description 3
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910052717 sulfur Inorganic materials 0.000 description 2
- 239000011593 sulfur Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48639—Silver (Ag) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85439—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の組立方法、特にリードフレームの
めっき処理に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for assembling a semiconductor device, and in particular to a plating process for a lead frame.
この種の半導体装置として、銅を主成分とするリードフ
レーム上に半導体素子を搭載し、この半導体素子を樹脂
封止して組立てたものがある。This type of semiconductor device includes one in which a semiconductor element is mounted on a lead frame whose main component is copper, and the semiconductor element is sealed with a resin and assembled.
ところで、半導体装置においては、半導体素子とリード
フレームとの接合および半導体素子から電気信号を取出
すための配線を確実に行い、かつ半導体装置をプリント
基板へ実装する際のはんだ付は性を良くする必要がある
ため、従来、リードフレームの表面にめっき処理を施す
ようにしている。By the way, in semiconductor devices, it is necessary to ensure the bonding of the semiconductor element and lead frame and the wiring for extracting electrical signals from the semiconductor element, and to improve the soldering properties when mounting the semiconductor device on a printed circuit board. Conventionally, the surface of the lead frame is plated.
すなわち、第３図に従来の半導体装置の断面図を示し、
第４図に従来のリードフレームの断面図を示すように、
先ずリードフレーム１の表面全体に、いおうを含む光沢
ニッケルめっき膜２を施し、このニッケルめっき膜２上
に銅フラッシュめっき膜３を施した後、さらにこのめっ
き膜３上の必要な部分に銀の部分めっき膜４を施してい
る。そして、この部分めっき膜４上に半導体素子５を搭
載し、金線６によって配線した後に、半導体素子５を樹
脂材７で樹脂封止している。詳述すれば、部分めっき膜
４は半導体素子５の接合および配線を行うためのもので
、ニッケルめっき膜２はリードフレーム１の銅と部分め
っき膜４との金属拡散防化膜として作用すると共に、樹
脂材７との密着力の向上に寄与するものである。That is, FIG. 3 shows a cross-sectional view of a conventional semiconductor device,
As shown in Figure 4, a cross-sectional view of a conventional lead frame,
First, a bright nickel plating film 2 containing sulfur is applied to the entire surface of the lead frame 1, a copper flash plating film 3 is applied on the nickel plating film 2, and then silver is applied to the necessary areas on this plating film 3. A partial plating film 4 is applied. Then, a semiconductor element 5 is mounted on this partially plated film 4 and wired with gold wires 6, and then the semiconductor element 5 is resin-sealed with a resin material 7. Specifically, the partial plating film 4 is for bonding and wiring the semiconductor element 5, and the nickel plating film 2 acts as a metal diffusion prevention film between the copper of the lead frame 1 and the partial plating film 4. , which contributes to improving the adhesion with the resin material 7.
しかしながら、ニッケルめっき膜２は上述したような利
点□がある反面、ダイポンディング、ワイヤポンディン
グおよび樹脂封止時の熱によって、表面が酸化され不働
態化皮膜が形成され易い。そのため、リードフレーム１
の樹脂封止されない部分に施されたニッケルめっき膜２
を剥離除去した後に−１はんだ付は性を良くするための
錫−鉛合金めっき膜８を施さなければならなかった。す
なわち、酸化されたニッケルめっき膜２を化学薬品で表
面活性化するのが困難であり、この活性化不良が前記錫
−鉛合金めっき膜８の密着不良の原因となるからである
。However, although the nickel plating film 2 has the above-mentioned advantages, the surface is easily oxidized and a passivation film is formed due to heat during die bonding, wire bonding, and resin sealing. Therefore, lead frame 1
Nickel plating film 2 applied to the parts that are not sealed with resin
After peeling off and removing -1, a tin-lead alloy plating film 8 had to be applied to improve soldering properties. That is, it is difficult to surface activate the oxidized nickel plating film 2 with chemicals, and this activation failure causes poor adhesion of the tin-lead alloy plating film 8.
したがって、工程数が多くなり、しかも剥離除去に使用
する薬品の消費量も多くなるために、製造コストの上昇
を招く原因となっている。Therefore, the number of steps increases and the amount of chemicals used for peeling and removal also increases, leading to an increase in manufacturing costs.
本発明はこのような事情に鑑みなされたもので、その目
的は、製造コストの低減がはかれる半導体装置の組立方
法を提供するものである。The present invention has been made in view of the above circumstances, and an object thereof is to provide a method for assembling a semiconductor device that can reduce manufacturing costs.
本発明に係る半導体装置の組立方法は、リードフレーム
の表面全体に、０．１〜２．０％のボロンを含有するボ
ロン−ニッケル合金めっきを０．１〜１．０μの膜厚に
施し、半導体素子を搭載して樹脂封止した後、リードフ
レームの樹脂封止されない部分の前記ボロン−ニッケル
合金めっき膜上に、錫−鉛合金めっきを施すものである
。The method for assembling a semiconductor device according to the present invention includes applying boron-nickel alloy plating containing 0.1 to 2.0% boron to a film thickness of 0.1 to 1.0 μ over the entire surface of a lead frame; After the semiconductor element is mounted and sealed with resin, tin-lead alloy plating is applied to the boron-nickel alloy plating film on the portion of the lead frame that is not sealed with resin.
本発明においては、ボロン−ニッケル合金めっき膜は、
組立工程の途中において不働態化皮膜が形成されにくい
ので、化学薬品による簡単な表面活性化処理のみで密着
性の良好な錫−鉛合金めっき膜が形成される。In the present invention, the boron-nickel alloy plating film is
Since a passivation film is difficult to form during the assembly process, a tin-lead alloy plating film with good adhesion can be formed with only a simple surface activation treatment using chemicals.
以下、本発明の一実施例を図により詳細に説明する。第
１図は本発明に係る半導体装置の組立方法が実施された
半導体装置を示す断面図、第２図は同じくリードフレー
ムの断面図で、これらの図において、ｌは銅を主成分と
するリードフレーム、３は銅フラッシュめっき膜、４は
銀の部分めっき膜、５は半導体素子、６は金線、７は樹
脂材、８は錫−鉛合金めっき膜でこれらは従来のものと
何ら変わるところがない。１０は０．１〜２．０％のボ
ロンを含有するボロン−ニッケル合金めっき膜で、前記
リードフレーム１の表面全体に０．１〜１．０μの膜厚
に施されている。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view showing a semiconductor device in which the method for assembling a semiconductor device according to the present invention is implemented, and FIG. 2 is a cross-sectional view of a lead frame. The frame, 3 is a copper flash plating film, 4 is a silver partial plating film, 5 is a semiconductor element, 6 is a gold wire, 7 is a resin material, 8 is a tin-lead alloy plating film, and these are no different from conventional ones. do not have. Reference numeral 10 denotes a boron-nickel alloy plating film containing 0.1 to 2.0% boron, which is applied to the entire surface of the lead frame 1 to a thickness of 0.1 to 1.0 μm.
次に組立方法について説明すると、先ずリードフレーム
１を周知の脱脂処理および活性化処理を施し、その後に
リードフレーム１の表面全体に前記ボロン−ニッケル合
金めっき膜ｌＯをめっき処理によって形成する。そして
、このボロン−ニッケル合金めっき膜１０上に従来と同
様な周知のめっき処理を施して銅フラッシュめっき膜３
を形成し、さらにこのめっき膜３上の必要な部分に銀の
部分めっき膜４を形成する。次いで、この部分めっき膜
４上に半導体素子５を搭載しグイポンドを行って、半導
体素子５をリードフレームｌに接合し、ワイヤボンドを
行って金線６を形成する。その後、前記半導体素子５を
樹脂材７で樹脂封止する。Next, the assembly method will be described. First, the lead frame 1 is subjected to well-known degreasing and activation treatments, and then the boron-nickel alloy plating film 10 is formed on the entire surface of the lead frame 1 by plating. Then, on this boron-nickel alloy plating film 10, a well-known plating process similar to the conventional one is performed to form a copper flash plating film 3.
A silver partial plating film 4 is further formed on the required portions on this plating film 3. Next, a semiconductor element 5 is mounted on this partial plating film 4 and bonded to bond the semiconductor element 5 to a lead frame l, and wire bonding is performed to form a gold wire 6. After that, the semiconductor element 5 is resin-sealed with a resin material 7.
樹脂封止に続く次の工程では、リードフレーム１の樹脂
封止されない部分の前記ボロン−ニッケル合金めっきｙ
、１０上に、錫−鉛合金めっき処理を施して錫−鉛合金
めっき膜８を形成する。詳述すれば、このめっき処理は
、ボロン−ニッケル合金めっき膜１０を、化学薬品によ
って表面活性化処理した後に行う。この活性化処理は例
えば５０℃に温められた２５〜３０％硫酸溶液を用い、
この溶液中に１分間浸漬させることによって行うことが
できる。前記錫−鉛合金めっき膜８は８μ程度の膜厚に
施す。In the next step following the resin sealing, the boron-nickel alloy plating is applied to the portions of the lead frame 1 that are not sealed with the resin.
, 10, a tin-lead alloy plating process is performed to form a tin-lead alloy plating film 8. Specifically, this plating treatment is performed after surface activation treatment of the boron-nickel alloy plating film 10 is performed using chemicals. This activation treatment uses, for example, a 25-30% sulfuric acid solution heated to 50°C.
This can be done by immersing it in this solution for 1 minute. The tin-lead alloy plating film 8 is applied to a thickness of about 8μ.
このような組立方法においては、ボロン−ニッケル合金
めっき膜１０は、リードフレーム１の銅と銀の部分めっ
き膜４との拡散防止性があり、しかも組立工程中の熱に
よっても不働態化皮膜が形成されにくいので、安定した
表面を維持することができる。したがって、錫−鉛合金
めっき膜８を施す際は、化学薬品による簡単な表面活性
化処理のみによって表面を活性化することができるから
、ボロン−ニッケル合金めっきＷｌ、ｌＯを剥離除去す
ることなく、密着性の良好な錫−鉛合金めっき膜８を形
成することができる。その結果、従来不可欠であったリ
ードフレーム１の樹脂封止されない部分に施されためっ
き膜を剥離除去する工程を省略することができる。In such an assembly method, the boron-nickel alloy plating film 10 has the property of preventing diffusion between the copper and silver partial plating films 4 of the lead frame 1, and also prevents the passivation film from being damaged by heat during the assembly process. Since it is difficult to form, a stable surface can be maintained. Therefore, when applying the tin-lead alloy plating film 8, the surface can be activated by only a simple surface activation treatment using chemicals, so the boron-nickel alloy plating Wl, IO is not peeled off and removed. A tin-lead alloy plating film 8 with good adhesion can be formed. As a result, it is possible to omit the step of peeling off and removing the plating film applied to the parts of the lead frame 1 that are not sealed with resin, which was conventionally indispensable.
実験によれば、ボロン−ニッケル合金めっきおよび錫−
鉛合金めっきが施されたリードフレーム１を、１７５℃
に加熱されたオーブン中に１６８時間保持した後に、３
６０’のねじり試験を行ったが、密着不良による錫−鉛
合金めっき膜８の剥離は観察されなかった。一方、この
ような実験を従来のいおうを含む光沢ニッケルめっき膜
２上に錫−鉛合金めっき膜８を施したものについて行っ
た結果、オーブン中に４８時間保持しただけでニッケル
めっき膜２と錫−鉛合金めっき膜８との間に剥離が生ず
ることがわかった。According to experiments, boron-nickel alloy plating and tin-
Lead frame 1 plated with lead alloy is heated to 175°C.
After 168 hours in an oven heated to 3
Although a 60' torsion test was conducted, no peeling of the tin-lead alloy plating film 8 due to poor adhesion was observed. On the other hand, as a result of conducting such an experiment on a conventional bright nickel plating film 2 containing sulfur with a tin-lead alloy plating film 8 applied thereto, it was found that the nickel plating film 2 and tin were separated by just 48 hours in an oven. - It was found that peeling occurred between the lead alloy plating film 8 and the lead alloy plating film 8.
（発明の効果）
以上説明したように本発明によれば、リードフレームの
表面全体に、０．１〜２゜０％のボロンを含有するボロ
ン−ニッケル合金めっきを０．１〜１．０μの膜厚に施
し、半導体素子を搭載して樹脂封止した後、リードフレ
ームの樹脂封止されない部分の前記ボロン−ニッケル合
金めっき膜上に、錫−鉛合金めっきを施したから、ボロ
ン−ニッケル合金めっき膜は、組立工程の途中において
不働態化皮膜が形成されにくいので、化学薬品による簡
単な表面活性化処理のみで密着性の良好な錫−鉛合金め
っき膜が形成される。(Effects of the Invention) As explained above, according to the present invention, boron-nickel alloy plating containing 0.1 to 2.0% boron is applied to the entire surface of the lead frame in a thickness of 0.1 to 1.0μ. After the semiconductor element is mounted and sealed with resin, tin-lead alloy plating is applied to the boron-nickel alloy plating film on the part of the lead frame that is not sealed with resin. Since a passivation film is not easily formed on the plating film during the assembly process, a tin-lead alloy plating film with good adhesion can be formed by only a simple surface activation treatment using chemicals.
したがって、従来不可欠であったリードフレームの樹脂
封止されない部分に施されためっき膜を剥離除去する工
程を省略することができる。その結果、組立工程を簡素
化し、薬品の消費量も少なくなるから、製造コストの低
減がはかれる。Therefore, the step of peeling off and removing the plating film applied to the parts of the lead frame that are not sealed with resin, which was conventionally essential, can be omitted. As a result, the assembly process is simplified and the consumption of chemicals is reduced, leading to a reduction in manufacturing costs.
第１図は本発明に係る半導体装置の組立方法が実施され
た半導体装置を示す断面図、第２図は同じくリードフレ
ームの断面図、第３図は従来の半導体装置を示す断面図
、第４図は同じくリードフレ一ムの断面図である。
１・・・・リードフレーム、５・・・・半導体素子、７
・・・・樹脂材、８・・・・錫−鉛合金めっき膜、１０
・・・・ボロン−ニッケル合金めっき膜。FIG. 1 is a sectional view showing a semiconductor device in which the method for assembling a semiconductor device according to the present invention is implemented, FIG. 2 is a sectional view of a lead frame, FIG. 3 is a sectional view showing a conventional semiconductor device, and FIG. The figure is also a sectional view of the lead frame. 1...Lead frame, 5...Semiconductor element, 7
...Resin material, 8...Tin-lead alloy plating film, 10
...Boron-nickel alloy plating film.
Claims (1)
〜２．０％のボロンを含有するボロン−ニッケル合金め
っきを０．１〜１．０μの膜厚に施し、このリードフレ
ームに半導体素子を搭載して樹脂封止した後、リードフ
レームの樹脂封止されない部分の前記ボロン−ニッケル
合金めっき膜上に、錫−鉛合金めっきを施すことを特徴
とする半導体装置の組立方法。0.1 on the entire surface of the lead frame whose main component is copper.
Boron-nickel alloy plating containing ~2.0% boron is applied to a film thickness of 0.1 to 1.0μ, and after mounting a semiconductor element on this lead frame and sealing it with resin, the lead frame is sealed with resin. A method for assembling a semiconductor device, characterized in that tin-lead alloy plating is applied on the boron-nickel alloy plating film on the unstopped portions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61105315A JPS62260348A (en) | 1986-05-06 | 1986-05-06 | Assembly method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61105315A JPS62260348A (en) | 1986-05-06 | 1986-05-06 | Assembly method for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62260348A true JPS62260348A (en) | 1987-11-12 |
Family
ID=14404273
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61105315A Pending JPS62260348A (en) | 1986-05-06 | 1986-05-06 | Assembly method for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62260348A (en) |
-
1986
- 1986-05-06 JP JP61105315A patent/JPS62260348A/en active Pending
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