JPS6225467A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form switching elements of the prescribed function on the same substrate by connecting in parallel photodiodes and normal-closed transistors between the gates and the sources of the elements, and connecting in parallel another photodiode and a discharging resistor between the gate and the source, thereby interrupting light by the normal-closed element and the resistor. CONSTITUTION:A (100) plane of a p-type Si substrate 1 is anisotropically etched to form a V-shaped groove 2, and an SiO2 film 3 is coated. A polysilicon 4 is superposed, the substrate 1is polished to nform separated islands 1a.... An SiO2 film 6 are coated, windows are selectively opened to expose the islands 1a, 1b. Then, with PH3 as a dopant single crystal Sis 7a, 7b are formed on the islands 1a, 1b and a polysilicon film 8 on a masl 6 by thermal decomposition of SiH4. The single crystal layers 7a, 7b are selectively masked with SiO2 films 9, and the film 8 is removed by etching. Thereafter, a normal-closed transistor 15, a diffused resistor 19 and a photodiode 17 are provided in the single crystal islands as prescribed, connected as prescribed, the element 15 and the resistor 19 are selectively shielded by an aluminum film 22 to complete it.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device serving as a light receiving section of a solid state relay.

[Background technology]

As a solid state relay circuit, there is a circuit as shown in FIG.

This circuit includes a switching element 25 of a solid state relay, a photodiode 23, 24' as a circuit for discharging the gate accumulated charge of this element 25, a resistor 19.
Normally-on transistor (junction FET) 15
are connected. In this circuit, a current is passed through the light emitting diode 27 to cause it to emit light, and the photodiodes 23 and 24 receive the light and convert it into current. Junction type FE
T15 is normally in the on state, but when light is
When the diodes 23 and 24 are irradiated, a potential difference occurs between their gates and sources, so they turn off.
In this state, the switching element 25 starts storing electricity. In other words, if such a circuit is used for discharging, the circuit will be in an open state when light is irradiated and will be in a short-circuited state when light is interrupted, so that the switching speed can be increased (the turn-on time can be shortened). Furthermore, it is also possible to prevent the switching element 25 from being neither on nor off when the light irradiation is insufficient.

However, when trying to form each of the above elements that make up such a circuit on the same substrate to form a single chip, the distance between each element is short, so the light only needs to be incident on the photodiode. The light from the supposed light emitting diode is
Elements other than photodiodes are also irradiated. When light irradiates elements other than photodiodes (transistors, resistors, etc.), electron and hole pairs are generated in these elements, and in the case of junction transistors, for example, they cannot be completely shut off and In this case, the resistance value fluctuates, which is a problem.

[Purpose of the invention]

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device in which elements such as transistors and resistors are not damaged by light.

[Disclosure of the invention]

In order to achieve the above object, the present invention includes a first photodiode inserted between the gate and source of a switching element, a normally-on transistor provided in parallel with the first photodiode, A semiconductor device including a second photodiode and a discharging resistor provided in parallel between the gate and source, and serving as a light receiving section of a switching device, the semiconductor device comprising at least the normally-on transistor and the discharging resistor. The gist of the semiconductor device is a semiconductor device characterized in that both are shielded from light.

Hereinafter, one embodiment of the present invention will be explained based on a hail diagram.

In the embodiment shown in the figure, the substrate is of DI type (Dielectric type).
rs.

1tion type). This is because, although it is not necessarily necessary to use a DI substrate in this invention, by using a DI substrate, it becomes possible to completely insulate each element formed on the same chip.

Figures 3 (al~(h) and Figure 4 (al~(g)
1 shows an example of a process for manufacturing the semiconductor device of the present invention.

Grooves 2 are formed by etching or the like on the surface of a single crystal silicon wafer 1 into which p-type impurities have been diffused.

At this time, the shape of the groove 2 is not limited to the V-shape as in the illustrated embodiment, but may be U-shape or other shapes.The method of forming the groove 2 is also not particularly limited, but for example, <100> One method is to etch the grooves 2 in the flat single crystal silicon wafer 1 using an alkaline etching solution containing KOH or the like as a main component. In this method, the etching rate of the alkaline etching solution for 111> plane single crystal silicon is as follows:
This takes advantage of the fact that the etching rate is extremely slow compared to the etching rate for <100> plane single crystal silicon.
When a part of the single-crystal silicon wafer 1 is etched with this alkaline etching solution, a V-shaped groove 2 consisting of a 111> plane making a 54'' angle with this <100> plane is automatically formed. [Figure 3 (a)].

An insulating layer 3 is formed by deposition or growth on the surface of the silicon wafer 1 on the side where the grooves 2 are formed [FIG. 3(b)].

A polysilicon layer 4 is formed on the insulating layer 3 to fill the trench 2 [FIG. 3(C)].

The silicon wafer 1 is polished from the opposite side, and the polishing is continued until the silicon wafer 1 is separated into a plurality of isolation islands 1a by the grooves 2, to obtain a DI substrate 5 (see FIG. 3).
d)].

A masking 6 having a crystal plane different from the surface of the isolation island 1a is formed on the entire side surface of the isolation island 1a of the DI substrate 5. The material of the masking 6 is the isolation island 1a.
...There is no particular limitation as long as it has a crystal plane different from the surface, but for example, if the isolation island 1a... is single crystal silicon, it may be easier to make or the main component is the same as the isolation island 1.
Since it is the same as a..., silicon oxide (S
ion) as the material for the masking 6 [FIG. 3(e)].

A predetermined portion of the DI substrate 5 (isolated island 1a in the figure).

The masking 6 on the Ib surface) is removed to form a predetermined shape [FIG. 3(f)].

5 sides of DI board. At this time, in the part where the masking 6 has been removed, that is, in the part where the isolation islands 1a and lb are exposed, a single crystal silicon layer 7a is formed on the single crystal surface of the back surface of the isolation islands 1a and lb.
, 7b are epitaxially grown, and the other parts, that is, the isolation islands 1a. Polysilicon N8 grows on masking 6 having a crystal plane different from 1b. Although the conditions for crystal growth are not particularly limited, for example, when growing an n-type crystal as in this example, it is preferable to perform a thermal decomposition reaction of SiH4 using PH3 as a dopant gas. This is because single-crystal silicon layers formed by hydrogenation reactions such as 5iC14 and 5iHzC1□ grow and spread laterally beyond the boundary area with the masking, but SiH
This is because the thermal decomposition reaction of , is suitable for forming fine patterns [Figure 3 (along)].

Masking 9 is formed on single crystal silicon layers 7a and 7b. The material of this masking is also not particularly limited, but for the same reason as the masking 6 mentioned above, Sin. It is preferable to use [Figure 3 (h)].

Etched and masked single crystal silicon 1
Portions of the polysilicon layer 8 other than 7a and 7b are removed.

The etching method is not particularly limited either, but plasma etching is preferably used in view of etching accuracy, ease of automation, and pollution control issues. Various reactive gases can be used for plasma etching, but if the material of the masking 9 is SiO□ as described above, for example, single crystal silicon and polysilicon can be etched. But, Sin,
is a CF with almost no etching.

+0□ mixed gas etc. are generally used. Although the component ratio of this mixed gas is not particularly limited, for example, CF.
It is common to use a ratio of 96%, 0.24%, etc. [Figure 4(a)].

By the process explained above, the p-type isolation island 1 on the substrate 5 is
a, Ib, n-type single crystal silicon layers 7a. Form 7b.

Next, each masking 6, 9 on the substrate 5 is removed, and a p-type impurity is diffused into both ends of the single-crystal silicon layer 7a to form a p-type layer 10 that will become a back gate [FIG. 4(b)] .

A p-type impurity is diffused into the center of the single crystal silicon layer 7a to form a gate (2). A p-type layer 11 is formed, and a p-type layer 12 is formed on top of a plurality of isolated island ICs on which no single crystal silicon layer is formed [Fig. 4(C)]
].

The single crystal silicon layer 7a includes the p-type layers 10 and 11.
During this period, the n
Diffuse type impurities and drain V.

In addition, an n-type layer 13, 14 which becomes the source 5 is formed to create a junction FET 15, and a plurality of isolated island ICs are formed.
. . . On top, an n-type layer 16 is formed to create a photodiode 17. An n-type layer 18.1 is formed by diffusing n-type impurities into both ends of the single-crystal silicon layer 7b to form a terminal portion.
8 to create a resistor 19 (FIG. 4(d)).

Each of the diffusion steps in FIGS. 4(b) to (dl) explained above is as follows:
Although not particularly limited, when a DI substrate is used as the substrate as in this example, it is preferable to conduct the diffusion at a diffusion temperature of 1100° C. or lower. This is because the DI substrate consists of an isolated island of single crystal silicon and a polysilicon layer, and due to the difference in thermal expansion coefficient between the two, at temperatures above 1100°C, as shown in Fig. This is because it becomes thick (warped) with the inner side, making it difficult to form an element.

Electrodes 2o are formed on the surface of each impurity layer by Al vapor deposition or the like [FIG. 4(e)].

A SiO□ film 21 is applied over the entire surface of the substrate 5 to stabilize the surface [FIG. 4(f)].

Isolation island 1a and resistor 1 on which junction type FET 15 is formed
The light shielding 22 is provided over the entire surface of the isolation island 1b where the
Although there are no particular limitations on the light shielding method used, it is preferable to use an AI vapor-deposited film as the light shield 22 from the viewpoint of ease of production and cost.

In this case, for example, the Al film thickness may be set to about 1.5 μm [FIG. 4(g)].

Furthermore, a plurality of light receiving elements (photodiodes) 17 formed on a plurality of isolated island ICs are connected to form a first photodiode array 23 and a second photodiode array 24. do.

If this is wired to the switching element 25 as shown in FIGS. 1 and 2, the switching element 25. Junction type FET15. Resistance 19. The semiconductor device of the present invention consisting of the first photo diode array 23 and the second photo diode array 24 can be manufactured as a single chip. The middle part shows the part that requires light shielding 22, that is, the part surrounded by the two-dot chain line in FIG.

FIG. 6 shows an example of a solid state relay using the semiconductor device of the present invention as a light receiving section of a diisoting element.

The substrate 5 placed on the lead frame 26 on the output side
As described above, the junction FET 15 and the resistor 19.
First and second photodiode play 23.24
is formed as a single chip. A light emitting diode 27 which is an input element of the solid state relay is connected to a lead frame 28 on the input side so as to face this substrate 5.
It is supported and placed. On the output side lead frame 26, an MO which is a switching element is mounted on another board.
3I-transistor 25 is formed, and its gate ■
. and source (2) are connected to the substrate 5 and the lead frame 26 on the output side by wire bonding. After this, as shown by the one-dot chain line in the figure, the substrate 5.
The circuit portion (the circuit shown in FIG. 2) consisting of the MO3I transistor 25 and the light emitting diode 27 is sealed with resin, and the connection portions 26a..., 28a of the lead frames 26, 28 on the output side and the input side are sealed. By cutting..., a solid state relay made into a monolithic IC is completed.

Solid state relays manufactured in this way are
As mentioned above, the switching MOS transistor 2
A photo diode array 23 as a discharge circuit of 5,
24. Resistance 19. It uses a normally ion junction type FET15.

In this circuit, a current is applied to the light emitting diode 27 to cause it to emit light, and this light is transmitted to the photodiode array 23, 24.
receives light and converts it into electric current. The junction FET 15 is always in the on state, but when the photodiode arrays 23 and 24 are irradiated with light, a potential difference is generated between the gate and source, so the junction FET 15 is in the off state, and in that state, the switching The MO3I-transistor 25 starts storing power. In other words, if such a circuit is used for discharging, the circuit will be in an open state when light is irradiated and will be in a short-circuited state when light is interrupted, so that the switching speed can be increased (the turn-on time can be shortened). Furthermore, it is possible to prevent the MOS transistor 25 from being neither on nor off when the light irradiation is insufficient.

Moreover, as explained above, the junction type FET15
The light emitting diode 2 and the resistor 19 are shielded from light.
The light of 7 will not be irradiated to these elements, and accidents such as the junction FET 15 not being able to completely shut off or the resistance value of the resistor 19 changing will not occur. Even in one-chip solid-state relays, where the element and other elements must be made very close together, the chip can be made smaller because elements other than the light-receiving element will not be distorted by light. In the embodiments described above, only the junction FET and the resistor are shielded from light. However, in the semiconductor device of the present invention, when other elements are formed on the same substrate, For example, if a MOS transistor (switching element) is on the same substrate as a light receiving element, this element can be shielded from light. The light-shielding area is not limited to the entire isolation island, and if the element is much smaller than the isolation island, it may be only the area around the element.

〔Effect of the invention〕

The semiconductor device of the present invention is constructed as described above, and since elements such as transistors and resistors are completely shielded from light from the light emitting element, these elements are not distorted by light. , it becomes possible to downsize solid state relays.

[Brief explanation of the drawing]

Fig. 1 is a structural explanatory diagram showing the main part of an embodiment of the present invention, Fig. 2 is a circuit diagram showing an example of the circuit of this embodiment, Figs. 3(a) to (h) and 4. Figures (- to (g) are explanatory diagrams showing an example of the manufacturing process of this embodiment, Figure 5 is a graph showing the relationship between the diffusion temperature and the amount of warpage of the substrate in this process, and Figure 6 is a graph showing the relationship between the diffusion temperature and the amount of warpage of the substrate in this process. 15 is a plan view showing the mounting state of the embodiment.Transistor 19.
... Resistance 22... Light shielding 23.24... Photo diode 25... Switching element agent Patent attorney Takehiko Matsumoto Figure 1 Figure 2 Figure 5 Expanded thermal skin (1C) Figure 3 Figure 4 (a) (f) Figure 6 Procedural Amendment (November 15, 1985 3, Relationship with the person making the amendment Patent application location 1048 Kadoma, Kadoma City, Osaka Prefecture Name)
Name (583) Matsushita Electric Works Co., Ltd. Representative f (Jachi Forged Sadao Fujii 4, no agent 6, Specification subject to amendment 7, Contents of amendment (1) The entire text of the specification is corrected as shown in the attached sheet. This correction also includes the correction of the title of the invention. ``Silicon'' is added to the description 1, name of the invention 2, method for manufacturing a semiconductor device 2, and claims, and then this ``°'' date 1 is added.
Con 4゛ On the death of the above bird body 11 [l old friend. 3. Detailed Description of the Invention [Technical Field] The present invention relates to a method for manufacturing a semiconductor device that is inserted between the gate and source of a switching element and serves as a light receiving section of a solid state relay. [Background Art] As a solid state relay circuit, there is a circuit as shown in FIG. This circuit includes a switching element 25 of a solid state relay, a photodiode array 23, 2.4, a resistor 19, and a normally-on transistor (junction FET) as a circuit for discharging the gate accumulated charge of this element 25.
)15 are connected. In this circuit, a current is passed through the light emitting diode 27 to cause it to emit light, and the photodiode arrays 23 and 24 receive the light and convert it into a current. The normally-on transistor 15 is normally in the on state, but light is transmitted to the photodiode play 23.
When the light is irradiated onto the switching element 24, a potential difference is generated between the gate and the source thereof, so that the switching element 25 is turned off, and in this state, the switching element 25 starts storing electricity. In other words, if such a circuit is used for discharging, the circuit will be in an open state when irradiated with light, and will be in a short-circuited state when light is interrupted, so that the switching speed can be increased (the turn-on time can be shortened). Furthermore, it is also possible to prevent the switching element 25 from being neither on nor off when the light irradiation is insufficient. However, if we try to form each of the above elements that make up such a circuit on the same substrate to form one chip, a very large number of elements must be formed on the same very small chip. . For example, in the case of the solid-state relay, a silicon photodiode formed on a chip can only generate an electromotive force of about 0.7 V at maximum, whereas a MOS photodiode formed on the same chip
) A transistor requires a power of 6V or more to operate, and if you want to operate this MOS transistor with the photodiode, you need to connect 12 photodiodes in series as shown in Figure 2. The photodiode array must be connected as above. In this way, creating a device such as the solid state relay on the same chip requires more elements than forming the same circuit using independent elements. Furthermore, the resistor 19 is connected to the normally-on transistor 1.
It is used for discharging the charge accumulated in the gate junction of 106. In order to make the photo diode array 24 connected in parallel work efficiently,
The resistance must be high, on the order of Ω or higher. However, such a high resistance cannot be achieved with a diffused resistor that can be formed using a normal IC process. Therefore, the inventor thought that if such a resistor 19 was to be formed on the same chip, it would be sufficient to form a thin band-shaped resistor using a single crystal silicon layer grown by epitaxial crystal growth. In order to realize this idea, it is necessary to form elements that require a single crystal silicon layer and elements that do not on the isolation island of the DI substrate. It is required to form these elements with high precision. Recently, as a method to differentiate between devices that require a single-crystal silicon layer and devices that do not, the surface of the isolation island of single-crystal silicon is masked with 5 int, and a layer of silicon that requires a single-crystal silicon layer is masked. A method has been developed in which only SiO□ on a remote island is removed and epitaxial crystal growth is selectively performed under reduced pressure using a mixed gas of SiH, CI2 and HCI. In this method, a single-crystal silicon layer is grown in areas where the Sing masking is not formed, but polysilicon is generated in areas where SiOz is formed, and this polysilicon is absorbed by the gas mixture. The purpose is to grow only a single crystal silicon layer on the substrate by etching and removing it with the HCI component. However, with this method, HCI also damages the single crystal silicon layer.
Because of the slight etching, the growth rate of this single crystal silicon layer is slow (also, this crystal growth has to be done under reduced pressure, which makes the equipment expensive, which is a problem). [Object of the invention] This invention was made in view of the above circumstances, and
It is an object of the present invention to provide a method for manufacturing a semiconductor device that allows a plurality of different elements to be easily formed on the same chip with a small number of steps. [Disclosure of the Invention] In order to achieve the above object, the present invention includes a first photo diode array inserted between the gate and source of a switching element, and a first photo diode array connected in parallel with the first photo diode array. A semiconductor device comprising a normally-on transistor, a second photodiode array and a discharge resistor connected in parallel between the gate and source of this normally-on transistor, and serves as the light receiving part of the solid-state relay. To create the device, the surface of the DI substrate is masked into a predetermined shape and epitaxial crystal growth is performed without considering selectivity, and a single crystal silicon layer is formed on the unmasked isolation islands.
A polysilicon layer is formed in other parts, and then the surface of the single crystal silicon layer is masked and etched to leave the single crystal silicon layer on a predetermined isolated island on the substrate. , impurity diffusion is performed at a predetermined position on the substrate including this single crystal silicon layer, the normally-on L transistor and a resistor are formed in the single crystal silicon layer on the isolation island, and the other parts are The gist of the present invention is a method for manufacturing a semiconductor device, characterized in that the first and second photodiode arrays are formed on a remote island. An embodiment of the present invention will be described below with reference to the accompanying drawings. In this invention, the substrate is of DI type (Dielectric type).
Is. type). This is because by using a DI substrate, it becomes possible to completely insulate each element formed on the same chip. An example of the manufacturing process for such an I-board is shown in Figure 3 (
Based on steps a) to (d), grooves 2 are formed by etching or the like on the surface of single crystal silicon wafer 1 into which p-type impurities to be described are diffused. At this time, the shape of the groove 2 is not limited to the V-shape as in the illustrated embodiment, but may be U-shape or other shapes.The method of forming the groove 2 is also not particularly limited, but for example, <100> One method is to etch grooves 2 in a flat single-crystal silicon wafer 1 using an alkaline etching solution containing KOH or the like as a main component. In this method, the etching rate of the alkaline etching solution for 111> plane single crystal silicon is as follows:
This takes advantage of the fact that the etching rate is extremely slow compared to the etching rate for single crystal silicon in the <100> plane.
When a part of the single-crystal silicon wafer 1 is etched with this alkaline etching solution, a V-shaped groove 2 consisting of a <111> plane making a 54° angle with this <100> plane is automatically formed. (Fig. 3(a)). An insulating layer 3 is formed by deposition or growth on the surface of the silicon wafer 1 on the side where the grooves 2 are formed [see FIG.
)). A polysilicon layer 4 is formed on the insulating layer 3 to fill the trench 2 [FIG. 3(C)]. The silicon wafer 1 is polished from the opposite side, and the polishing is continued until the silicon wafer 1 is separated into a plurality of isolation islands 1a by the grooves 2, to obtain the DII plate 5 [Fig.
d)). Next, FIG. 3 (81 to (h
) and FIGS. 4(a) to (I will explain in detail while looking at the illusion. The entire side surface of the separation island 1a of the DII plate 5 has a crystal plane different from the surface of the separation island 1a. Form a masking 6. The material of the masking 6 is the isolation island 1a.
...There is no particular limitation as long as it has a crystal plane different from the surface, but for example, if the isolation island 1a... is single crystal silicon, it may be easier to make or the main component is the same as the isolation island 1.
Since it is the same as a..., silicon oxide (S
Foh) is preferably used as the material for the masking 6 [FIG. 3 (41)]. The masking 6 on a predetermined portion of the DII plate 5 (the surfaces of the separation islands 1a and 1b in the figure) is removed so as to have a predetermined shape [FIG. 3(f)]. 5 sides of DI board. At this time, in the part where the masking 6 has been removed, that is, in the part where the isolation islands 1a and lb are exposed, a single crystal silicon layer 7a is formed on the single crystal surface of the back surface of the isolation islands 1a and lb.
, 7b are epitaxially grown, and a polysilicon layer 8 is grown on the other portions, that is, on the masking 6 having a crystal plane different from that of the isolation islands 1a and 1b. The conditions for crystal growth are not particularly limited either, but for example, when growing an n-type crystal as in this example, the conditions are PH. S i H. as the dopant gas. It is preferable to carry out the thermal decomposition reaction. Because 3 i C 1 a and St
Single-crystal silicon layers formed by hydrogenation reactions such as H, CI, etc. grow and spread laterally beyond the boundary area with the masking, but this does not occur with thermal decomposition reactions of SiH4, and it is difficult to form fine patterns. This is because it is suitable (Fig. 3 (g)
)). Single crystal silicon layer 7a. Masking 9 is formed on 7b. Although the material of this masking 9 is not particularly limited, Sin. It is preferable to use [Figure 3 (h)]. Etching is performed to remove portions of the polysilicon layer 8 other than the masked single crystal silicon layers 7a and 7b.
The etching method is not particularly limited either, but plasma etching is preferably used from the viewpoint of etching accuracy, ease of automation, and pollution control issues. Various reactive gases can be used for plasma etching, but as mentioned above, the material of the masking 9 is Sin. For example, single crystal silicon and polysilicon are etched, but Sin,
is a CF with almost no etching. +0□ mixed gas etc. are generally used. The component ratio of this mixed gas is also not particularly limited, but for example, CF4
It is generally used at a ratio of 96%, 0□4%, etc. [Figure 4(a)]. By the process explained above, the p-type isolation island 1 on the substrate 5 is
N-type single crystal silicon layers 7a and 7b are formed on layers a and lb. Next, each of the masking layers 6 and 9 on the substrate 5 is removed, and n-type impurities are diffused into both ends of the single-crystal silicon layer 7a to form a p-type layer 10 that will become a back gate (see Figure 4). An n-type impurity is diffused into the center of the single crystal silicon layer 7a to form a gate V. A p-type layer 11 is formed, and a p-type layer 12 is formed on top of a plurality of isolated island ICs on which no single crystal silicon layer is formed [Fig. 4(C)]
]. The single crystal silicon layer 7a includes the p-type layers 10 and 11.
During this period, the n
Diffuse type impurities and drain V. N-type layers 13 and 14, which will become the source V, are formed to form a normally-on transistor 15, and an n-type layer 16 is formed on the plurality of isolation island ICs to form a photodiode. Create 17. In the single-crystal silicon layer 7b, n-type impurities are diffused into both ends thereof to form n-type layers 18 and 18 that will serve as terminal portions to create a resistor 19.
Figure 4 (dl). Each of the diffusion steps in Figures 4 (b) to (d) explained above is
Although not particularly limited, as a substrate, D
When using an I-substrate, it is preferable to perform the diffusion at a temperature of 1100° C. or lower. This is because the DI substrate consists of an isolated island of single crystal silicon and a polysilicon layer, and due to the difference in thermal expansion coefficient between the two, at temperatures above 1100°C,
This is because, as shown in FIG. 5, the substrate is greatly warped with the single-crystal silicon side inward, making it difficult to form elements. Electrodes 20 are formed on the surface of each impurity layer by AI vapor deposition or the like [FIG. 4(e)]. A SiO film 21 is formed on the entire surface of the substrate 5 to stabilize the surface [FIG. 4(f)]. If necessary, light shielding 22 is provided over the entire surface of the isolation island 1a where the normally-on transistor 15 is formed and the isolation island 1b where the resistor 19 is formed. Although the method of blocking light is not particularly limited, it is preferable to use an AI vapor deposited film as the light blocking layer 22 from the viewpoint of ease of production and cost. In this case, the Al film thickness may be set to about 1.5μ, for example. Although the light shielding 22 is not necessarily necessary in this invention, it is possible to shield the normally-on transistor 15, the resistor 19, etc. from light in this way. If this is done, the light from the light emitting diode 27 will not be irradiated to these elements, and accidents such as the normally-on transistor 15 not being able to completely shut off or the resistance value of the resistor 19 fluctuating may occur. There will be no more. Therefore, even in one-chip solid-state relays in which the light-receiving element and other elements must be made very close together, the elements other than the light-receiving element will not be distorted by light, making the chip smaller. [Figure 4 (along)]. Furthermore, a plurality of light receiving elements (photodiodes) 17 formed on a plurality of isolated island ICs are connected to form a first photodiode array 23 and a second photodiode array 24. Form. If this is wired to the switching element 25 as shown in FIGS. 1 and 2, the switching element 25. Normally-on transistor 15° resistor 19. A semiconductor device including the first photo diode array 23 and the second photo diode array 24 can be manufactured as one chip. Note that the portion shown in FIG. 1 is the part shown in the circuit of FIG.
2 shows the necessary part, that is, the part surrounded by the two-dot chain line in FIG. FIG. 6 shows an example of a solid state relay using a semiconductor device manufactured by the method of the present invention as a light receiving section of a switching element. The substrate 5 placed on the lead frame 26 on the output side
As mentioned above, the normally-on transistors 1'5. Resistance 19. The first and second photodiode arrays 23 and 24 are formed into one chip. A light emitting diode 27, which is an input element of the solid state relay, is supported by a lead frame 28 on the input side and is disposed so as to face the substrate 5. On the output side lead frame 26, a MOS transistor 25 which is a switching element is formed on another substrate, and its gate V. and source (2) are connected to the substrate 5 and the output side lead frame 2G by wire bonding. After this, as shown by the dashed line in the figure, a circuit part (circuit shown in FIG. 2) consisting of a substrate 5° MOS transistor 25 and a light emitting diode 27 is added.
are sealed with resin, and the connection portions 26a of the output side and input side lead frames 26, 28 are connected to each other. 28a..., a solid state relay made into a monolithic IC is completed.As mentioned above, the solid state relay manufactured in this manner uses a phototransfer as a discharging circuit for the switching MOS transistor 25. Diode array 23, 24, resistor 1
9. This uses a normally ion transistor 15. In this circuit, a current is passed through the light emitting diode 27 to cause it to emit light, and the photodiode arrays 23 and 24 receive this light and convert it into a current. The normally-on transistor 15 is always on, but when light is
When the diode arrays 23 and 24 are irradiated, a potential difference occurs between their gates and sources, so they turn off, and in that state, the switching MOS transistor 2
5 electricity storage begins. In other words, if such a circuit is used for discharging, the circuit will be in an open state when light is irradiated and will be in a short-circuited state when light is interrupted, so that the switching speed can be increased (the turn-on time can be shortened). Also,
It is also possible to prevent the MOS transistor 25 from being neither on nor off when the light irradiation is insufficient. As described above, in the method for manufacturing a semiconductor device of the present invention, a single crystal silicon layer can be easily formed only in a predetermined portion on the same substrate by epitaxial crystal growth without consideration of selectivity. It becomes possible to manufacture a semiconductor device used in a solid-state relay in which elements that require layers and elements that do not coexist can be manufactured with fewer steps. Moreover, in this invention, I)
By using an I-substrate, it becomes possible to completely insulate each element formed on the same chip, so that it is also possible to generate a high voltage for driving the gate of a MoS transistor. [Effects of the Invention] The method for manufacturing a semiconductor device of the present invention is configured as described above, and by epitaxial crystal growth without consideration of selectivity, it is possible to achieve, for example, a high resistance that cannot be achieved with a diffused resistor that can be formed by a normal IC process. It is possible to simultaneously form a single-crystal silicon layer that provides the necessary resistance and a single-crystal silicon layer that serves as the operating layer of a transistor, making it easy to separate areas on the same chip with and without a single-crystal silicon layer. Since the semiconductor devices can be manufactured separately in a small number of steps, it becomes possible to easily manufacture a semiconductor device consisting of a plurality of different elements in a small number of steps. 4. Brief description of the drawings FIG. 1 is a structural explanatory diagram showing the main parts of an example of a semiconductor device formed according to the present invention, FIG. 2 is a circuit diagram showing an example of a solid state relay circuit, and FIG. Diagram (a)
- (d) are explanatory diagrams showing an example of the manufacturing method of the DI board used in the present invention, Fig. 3 (e) - (hl and Fig. 4
Figures (al to g) are explanatory diagrams showing one embodiment of the present invention, Figure 5 is a graph showing the relationship between the diffusion temperature and the amount of warpage of the substrate in this invention, and Figure 6 is a graph showing the relationship between the diffusion temperature and the amount of warpage of the substrate in this invention. 5 is a plan view showing a mounted state of a semiconductor device to be mounted. 5... Substrate 6... Masking 7... Single crystal silicon layer 8... Polysilicon layer 15... Normally-on transistor 19 ...Resistance 23.2
4...Photo diode array

Claims (3)

[Claims] (1) A first photodiode is inserted between the gate and source of the switching element, a normally-on transistor is provided in parallel with this first photodiode, and a second photodiode is inserted between the gate and source of the switching element. A semiconductor device is provided with a photodiode and a discharge resistor in parallel, and serves as a light receiving section of a solid-state relay, wherein each of the elements is formed on a DI substrate, and at least the normally-on A semiconductor device characterized in that a transistor and a discharge resistor are shielded from light. (2) The semiconductor device according to claim 1, wherein the entire isolation island on the DI substrate, on which the normally-on transistor and the discharge resistor are provided, is shielded from light. (3) The semiconductor device according to claim 1 or 2, wherein light shielding is performed by an Al vapor deposited film.