CA1040320A - Depletion isolated semiconductor on insulator structures - Google Patents

Depletion isolated semiconductor on insulator structures

Info

Publication number
CA1040320A
CA1040320A CA243,354A CA243354A CA1040320A CA 1040320 A CA1040320 A CA 1040320A CA 243354 A CA243354 A CA 243354A CA 1040320 A CA1040320 A CA 1040320A
Authority
CA
Canada
Prior art keywords
layer
semiconductor
circuit components
semiconductor material
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA243,354A
Other languages
French (fr)
Inventor
Alfred C. Ipri
John C. Sarace
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Application granted granted Critical
Publication of CA1040320A publication Critical patent/CA1040320A/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)

Abstract

ABSTRACT
An integrated circuit device comprises a layer of semiconductor material on an insulating substrate. At least two spaced-art circuit components, such as field-effect transistors, are formed in the layer of semiconductor material. The circuit components are electrically isolated from each other by a method of (1) forming a layer of insulating material over the layer of semiconductor material and between the circuit components, (2) forming a layer of electrically conductive material over the layer of insulating material, and (3) providing bias means between the layer of conductive material and the layer of semiconductor material so as to deplete completely a region in the layer of semiconductor material opposite to the layer of conductive material and between the circuit components.

Description

K(A 67,'~0~

104U3Zo II)is invcntion rclatcs to a semiconductor device and a mcthod Or elcctrically isolating circuit components thereon. More ~rticularly, thc invention relates to an integrated circuit dcvice and a method of electrically isolating activc components formed in the integrated circuit.
In the manufacture of certain integrated circuits, such as those utilizing epitaxially deposited silicon on a suhstrate of sapphire, for example, electrical isolation between circuit components of the integrated circuit has been accomplished by forming islands of the silicon layer, whereby the islands are separated by air. Further electrical IS isolation of the silicon islands has heen obtained by covering the islands and the space therebetween with a layer of dielectric material. While such electrical isolation of circuit components in an integrated circuit is satisfactory for some semiconductor devices, isolated islands of semiconductor material present certain problems associated with the edge effects of these islands. For example, the threshold voltage of a field-effect transistor (FET~ formed in a semiconductor island can be unstable. Also, the breakdown voltage of such a field-effect transistor is usually lower than when formed in an integrated circuit whose surface is substantially planar. Furthermore, integrated circuits that comprise a plurality of separate islands of semiconductor material on an insulating substrate present serious problems for obtaining good metallization over the edges of the islands without any discontinuities
-2-~' ~. , .
. ~ , , . . . ~ . .

~ 67,908 lV4~3Zo 1 or unwanted excessive resistance in the metallization.
Field plates,or shields, have been used insemiconductor devices comprising bulk silicon, but the effect of the field plates in these devices is primarily to act as channel stoppers. It is not easy to get substantially complete electrical isolation between spaced-apart circuit components in devices formed in bulk silicon because it is not possible to completely deplete the region beneath the field plate in such devices.
In accordance with the present invention, a novel semiconductor device and method of isolating circuit components thereon are provided wherein the structure is planar so that there are no islands to provide step heights whicl1 present metal coverage problems. Also, by not utilizing the island-isolation techniques of the prior art, problems relating to the threshold instability and voltage breakdown of the semiconductor device are markedly reduced or substantially eliminated.
The novel semiconductor device comprises a layer of semiconductor material on an insulating substrate. At least two circuit components, each separated from the other are formed in the layer of semiconductor material. A layer of electrically insulating material is over the layer of semiconductor material, and a layer of electrically conductive 2S material, which functions as a field plate, or shield, is over the layer of insulating material. In accordance with the novel method of the present invention, means are provided to bias the layer of conductive material with respect to the layer of semiconductor material to form a depleted region in the
3 layer of semiconductor material opposite to the layer of ,. -, ~ . , , ., ~ . . , .. . . . . .. . .

~^- RCA 67908 1~4~ ZV
1 conductive material and between the circuit components.
In one embodiment of the novel semiconductor device, the circuit components comprise field-effect transistors, having source and drain regions formed in a layer of single crystal silicon. The layer of silicon is epitaxially deposited on a substrate of sapphire, and the circuit components are adapted to be isolated from each other by a depletion region that extends through the complete thickness of the layer of semiconductor material between the circuit components. The depletion region is obtained by bias means, preferably by electrically connecting a field plate to the layer of semiconductor material and utilizing the voltage provided by the work function between the field Z plate and the layer of semiconductor material.
In the drawings:
FIGURE l is a fragmentary cross-sectional view of an embodiment of the novel semiconductor device taken along ~ the plane l-l of FIGURE 2;
j FIGURE 2 is a fragmentary plan view of the novel semiconductor device shown in FIGURE l;
FIGURES 3-7, 9, lO and 12, are fragmentary cross-sectional views of the novel semiconductor device in difference stages of its construction; and FIGURES 8 and ll are fragmentary plan views of the 2S novel semiconductor devices in different stages of its construction.
Referring now particularly to FIGURES l and 2 of the drawing, there is shown one embodiment of the novel ,. . . . . . .
".,, I~(A 67908 lV4(~320 I semiconductor device 10 of the present invention. The semi-conductor device lO comprises at least two circuit components 12 and 14, illustrated herein as field-effect transistors (FET ' S) . The semiconductor device 10 comprises an insulating substrate 16, such as sapphire (A1203), spinel, or titanium dioxide, (TiO2), for example. A layer 18 of semiconductor material such as N- type silicon, germanium, or gallium arsenide, for example, is epitaxially deposited on the su~strate 16. Source channel, and drain regions of the FETs 12 and 14 are formed in the semiconductor layer 18, as will hereinafter be explained.
A layer 20 of electrically insulating material, such as silicon dioxide, silicon nitride, or aluminum oxide, ~or example, is over the semiconductor layer 18. An electrically conductive layer 22, such as of doped polycrystalline silicon, often called polysilicon, is over the electrically insulating layer 20, except where the circuit components 12 and 14 are formed. An electrically insulating layer 24, such as of silicon dioxide, for example, is over the conductive layer 22 and around electrical contacts of the circuit components 12 and 14, as best shown in FIGURE 1 for the circuit component 14. A (phosphorus) doped poly-silicon layer 26 is over the insulating layer 24, except in the region of the component 12, and a (boron) doped layer 28 of polysilicon is over the doped polysilicon layer 26 and over the portions of the component 12, as will hereinafter be explained.
The circuit component 14, as shown in FIGURES 1 and 2, is a deep depletion type FET having an N+ source .,., , ,. ~. ~ . .- . ..... .
.. ::. - - :. ..... . . :- .
-.. .. : . . .. . , , , . , , -- RCA 67,908 15~4()3ZO
l region 30, an N- channel region 32, and an N+ drain region 34. A gate electrode 36 is separated from the channel region 32 by a portion of the insulating layer 20, and electrical contacts 38 and 40 make contact with the source and drain regions 30 and 34, respectively. An electrical contact to the gate electrode 36 is not shown.
The circuit component 12 is a P-channel FET
comprising a source region 42, a channel region 44, and a drain region 46. A gate electrode 48 is separated from the channel region 44 by a portion of the insulating layer 20, as shown in FIGURE 1. A metalized contact 50 is connected to the gate electrode 48. Metal contacts 52 and 54 are electrically connected to the source and drain regions 42 and 46, respectively.
lS Since the source, channel, ant drain regions 30, 32, ant 34, respectively, of the circuit component 14 are formed in the same semiconductor layer 18 as the source, channel, and drain regions 42, 44 and 46 of the circuit component 12, it is most desirable to separate, that is, to electrically isolate the circuit component 12 from circuit component 14. In accordance with the present invention, a region 60 of the semiconductor layer 18, between the circuit components 12 and 14 of the device 10, is depleted by biasing the conductive layer 22 with respect to the semi-conductor layer 18. This may be accomplished under appropriate conditions by connecting the conductive layer 22 to the semiconductor layer 18, as by connectingthe metalized contacts 56 and 38 to a common connection, such as ground.
The bias means in the novel device 10 is preferably -~ . .. . . . . . .

RCA 679~8 ~ 4~ 3 ZO l a voltage provided by the work function difference resulting from the different materials of the (field plate) conductive layer 22 and the semiconductor layer 18.
Other bias means, however, such as a battery of suita b~e voltage, may be connected between the conductive layer 22 and the semiconductor layer 18 to completely deplete the region 60 of the semiconductor layer 18 between the circuit components 12 and 14.
Due to the work function difference between the (doped polysilicon) conductive layer 22 and the (single crystal silicon) semiconductor layer 18, an electric field exists at the surface of the semiconductor layer 18.
~lectrons which were initially present in the regions 60 of the semiconductor layer 18, opposite the conductive layer 22, are affected by the electric field and are swept out, leaving the region 60 depleted of electrons. The depth of the depleted region 60 depends upon the thickness of the semlconductor layer 18 and its doping concentration.
Where the semiconductor layer 18 is relatively thin , silicon, that is, less than 1 micron in thickness, the concentration of carriers in the N- type silicon layer 18 is between 1 and 2 X1015/cm3, and the conductive layer 22 is (boron) doped polysilicon, the region 60 can be completely depleted by connecting the layers 22 and 18 to each other, by a common connection, such as ground, whereby the circuit components 12 and 14 are substantially electrically isolated from each other.
The novel semiconductor device 10 can be made as follows: Referring now to FIGURE 3, there is shown the insulating substrate 16 which may be a wafer of sapphire, spinel, or titanium dioxide, for example, having a .. , ........... . , , . , - , :. ~ , . . . .
-'.: ~ ' ,: ~ , , ~,, R(~A 67,908 1~03Z0 1 thickness of about between 250~m and 500 ~m. A layer of semiconductor material, such as N- type silicon, having a carrier concentration of between 1- 2xI015/cm3 and a thickness of between about 0.5 ~m and 0.7 ~m is epitaxially deposited on the surface of the insulating substrate 16. The semiconductor layer 18 may be doped with either arsenic or phosphorus, for example.
The layer 20 of electrically insulating material is preferably a layer of silicon dioxide which can be grown thermally on the semiconductor layer 18, as by oxidizing the semiconductor layer 18 in steam at a temperature of about 900C for between 30 and 60 minutes. The insulating layer 20, shown in FIGURE 4, should have a thickness of between about 500A and l,OOOA.
Next, a layer 22a of polysilicon is deposited upon the insulating layer 20, as shown in FIGURE 5. The polysilicon layer 22a can be deposited upon the insulating layer 20 by any suitable method, as by the decomposition of silane, SiH4, at a temperature of about 700C in a chemical vapor deposition system. The thickness of the polysilicon layer 22a is between about 0.1 ~m and 0.5 ~m. Means are provided to dope the polysilicon layer 22a, shown in FIGURE 7, to make it conductive. To this end, a layer 23 of P+(boron) doped glass, as shown in FIGURE 6, is deposited over the polysilicon layer 22a. The layer 23 of P+ ~boron) doped glass can be deposited by reacting silane (SiH4) and oxygen in the presence of diborane at a temperature of between 320 and 450C in achemical vapor deposition process, well-known in the art. The thickness of the layer 23 may be in the neighborhood of about 3,OOOA and should have a R~ 67,908 ~ 32 concentration of about 102/cm3.
Ihe boron glass layer 23, shown in FIGURE 6, is defined with a photoresist, not shown, to form the field plate 22, in the pattern shown in FIGURE 7 The defined boron glass layer 23 is then etched as with a buffered HF
solution; and the remaining defined boron glass layer 23 is heated for abo-lt 10 minutes in helium at a temperature of about 1,050C to diffuse the boron into the field plate 22.
The boron glass 23 is then stripped from the field plate 22, using an HF acid solutio~. The portion of the polysilicon layer 22 that is not used for the field plate is then removed, as with a solvent which does not substantially attack boron doped silicon, such as a solution of KOH, water, and N-propanol at a temperature of about 70C.
The structure shown in FIGURE 7 is now treated to form the gates 36 and 48, of the circuit components 14 and 12, respectively, and to provide means for forming the source and drain regions of these circuit components. To this end, the layer 24 of silicon dioxide, having a thickness of between 500A and 1000A, is formed over the structure shown in FIGURE 7 as by heating in steam at 900C for about 30-60 minutes, shown in FIGURE 9. A polysilicon layer (not shown) is deposited over the layer 24 and a boron doped 2S glass layer (not shown) is deposited over the last-mentioned polysilicon layer in the manner previously described. The boron doped layer is then covered with a photoresist which, in turn, is defined to form the gates 36 and 48 by photolithographic means well known in the art. The boron glass is now etched, leaving boron glass portions over the polycrystalline layer which will be the gates 36 and 48.
g ... . .. . . . .. .
- . . .
.

lV4~Z~) The structure is now heated to diffuse boron into the polysilicon layer to form the gates 36 and 48. The remaining boron glass and portions of the polysilicon layer, other than the gates 36 and 48 of the circuit components 5 14 and 12, respectively, are now etched away. Portions of the insulating layer 20 are next etched away to expose portions of the surface of the semiconductor layer 18 for diffusing impurities therein to form the source and drain regions of the circuit components 12 and 14, as shown in FIoURE 10.
- The source and drain regions 30 and 34 of the component 14 (FIGURE 1) are now formed by depositing a layer 26 (FIGURE 12) of phosphorus doped polycrystalline silicon ov0r exposed portions of the surface of the semicon-lS ductor layer 18, the phosphorus doped layer 26 is deposited in a chemical vapor deposition system from a mixture of silane and PH3 at a temperature of between 320 and 450C to a thickness of about l,OOOA. The concentration of phosphorus in the doped polycrystalline silicon layer 26 is about 1019/cm3. The phosphorus doped layer 26 is defined with photoresist over the source and drain regions 30 and 34. The layer 28 of boron doped polycrystalline silicon is now deposited over the structure shown in FIGURE 12 for the purpose of forming the source and drain regions 42 and 46 of the com-ponent 12, as shown in FIGURE 2. The boron doped layer 28 and the phosphorus doped layer 26 are then heated to a temperature of about 1050C for about 15 minutes in helium to diffuse the boron and phosphorus into the semiconductor layer 18, simultaneously whereby to form the source and drain regions 42 and 46 of the device 12 and the source and drain regions :: : . " : - ~ ": , .
, . . .. , , ~

-RCA 67,908 104~t20 ~.
30 and 34 of the device 14.
Contact regions to the sources and drains of the ~
circuit components 12 and 14 and also to the field plate 22 ~;
are formed by photolithographic means, using a photoresist and a buffered HF for etching, in a manner well-known in the art. Metal contacts 38 and 40 for source and drain regions of the circuit component 14 and metal contacts 52 and 54 for the source and drain regions 42 and 46 of the circuit ~
component 12, as well as a metal contact 56 for the field ~ `
plate 22 are formed by thc vacuum evaporation of a metal, such as aluminum, in a manner well-knwon in the art.
While the novel semiconductor device 10 has been doscribed with components 12 and 14 formed in the somiconductor layer 18 of N- type somiconductor material, it is within the contemplation of the present invention to lnclute semicontuctor tevices with components formed in P
~ , .
type somiconductor material as where the conductive layer 22 can~be phosphorus doped polysilicon or a metal. If the ; 20 contuctive~layer 22 is~ a metal, then the bias applied between the~contuctive layer~22 and the semiconductor layer 18 may be other than zero, that is, either a positive or a negative ? ' . ~
potential in order to effect the completely depleted region 0~within the semicontuctor layer 18.
2S~ ;

~ ~ 30 "~
.. ..
, .,

Claims (2)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. A semiconductor device (10) comprising: an insulating substrate (16), a layer of semiconductor material (18) on said insulating substrate (16), two circuit components (12 and 14), each separated from the other, formed in said layer of semiconductor material (18), characterized by a layer of. electrically insulating material (20) over said layer of semiconductor material (18) and between said circuit components, (12,14) a layer of electrically conductive material (22) over said layer of insulating material, and means (40 and 56) to bias said layer of conductive material (22) with respect to said layer of semiconductor material (18) to form a depletion region (60) in said layer of semiconductor material (18) opposite to said layer of conductive material (22) and be-tween said circuit components (12, 14).
2. A semiconductor device (10) as described in Claim 1, wherein; said insulating substrate (16) comprises a material chosen from the group consisting of sapphire, spinel, and titanium dioxide, said layer of semiconductor material (18) is one consisting of silicon, germanium, and gallim arsenide, said layer of insulating material (20) is one chosen from the group consisting of silicon dioxide, silicon nitride, and aluminum oxide, said layer of electrically con-ductive material (22) is a material chosen from the group consisting of a metal and doped polysilicon, and said means to bias said layer of conductive material (22) with respect to said layer of semiconductor material (18) comprises means (40 and 56) to completely deplete the semiconductor material between said circuit components.
CA243,354A 1975-01-13 1976-01-12 Depletion isolated semiconductor on insulator structures Expired CA1040320A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US54044375A 1975-01-13 1975-01-13

Publications (1)

Publication Number Publication Date
CA1040320A true CA1040320A (en) 1978-10-10

Family

ID=24155496

Family Applications (1)

Application Number Title Priority Date Filing Date
CA243,354A Expired CA1040320A (en) 1975-01-13 1976-01-12 Depletion isolated semiconductor on insulator structures

Country Status (11)

Country Link
JP (1) JPS5346701B2 (en)
BE (1) BE837382A (en)
CA (1) CA1040320A (en)
CH (1) CH598695A5 (en)
DE (1) DE2600221B2 (en)
FR (1) FR2297496A1 (en)
GB (1) GB1509949A (en)
IN (1) IN144889B (en)
IT (1) IT1049016B (en)
NL (1) NL7600259A (en)
SE (1) SE408508B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4448632A (en) * 1981-05-25 1984-05-15 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor devices
US7282409B2 (en) * 2004-06-23 2007-10-16 Micron Technology, Inc. Isolation structure for a memory cell using Al2O3 dielectric
JP2011119397A (en) * 2009-12-02 2011-06-16 Canon Inc Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
CH598695A5 (en) 1978-05-12
JPS5346701B2 (en) 1978-12-15
FR2297496A1 (en) 1976-08-06
JPS5195785A (en) 1976-08-21
SE408508B (en) 1979-06-11
IN144889B (en) 1978-07-22
GB1509949A (en) 1978-05-10
BE837382A (en) 1976-05-03
IT1049016B (en) 1981-01-20
SE7600122L (en) 1976-07-14
DE2600221A1 (en) 1976-07-15
DE2600221B2 (en) 1978-09-07
NL7600259A (en) 1976-07-15

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