JPS62252962A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent erroneous operation cuased by the input of radiation such as alpha rays into a memory chip, by forming a P<+> type region, which has a concentration higher than that of a P<-> type substrate by an order of magnitude or more, directly beneath an N<+> region, which is connected to a bit line. CONSTITUTION:P<+> type impurities are selectively injected and diffused in a P<-> type semiconductor substrate 1. A P<+> region 9 for preventing inversion and parasitic phenomena is formed. At the same time, an element isolating and insulating film 8 is formed. Then, an N<+> region 6, a P<+> region 12, gate electrodes 2 and 3 and N<+> regions 5 and 7 are formed. Then, an interlayer insulating film 14 is laminated, and a contact hole 15 is formed by etching. Then, with the contact hole 15 as a mask, silica glass, which inludes P-type impurity ions such as boron and can be rotated and applied, is rotated and applied. Thereafter, a P<+> region 13 is formed by heat treatment. After interconnection is performed, a low-permittivity material is formed on the entire surface.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device that uses the presence or absence of electric charge as stored information.

[Conventional technology]

As an example of a conventional semiconductor device of this type, the structure of a dynamic MOSRAM memory cell 256 is shown in FIG. That is, in FIG. 2, 1 is a semiconductor substrate with P-type conductivity, 2 and 3 are gate electrodes of the first and second layers, 4 is a gate insulating film, 6 is a charge storage region, and 7 is a semiconductor substrate with P-type conductivity. N'' region 8 as a bit line is an inter-element isolation insulating film, 9 is inversion, P'' region 10 and 11 are depletion layers for parasitic prevention, 14 is an interlayer insulating film, 15 is a contact hole,
16 is a word line, and 17 is a capacitor power supply.

In such a device, when the potential of the word line increases and the potential of the second layer gate electrode 3 as a transfer gate connected to this word line becomes higher than the threshold voltage, the voltage immediately below this gate electrode 3 increases. A channel of the N° inversion layer is formed, and conduction occurs between both N° regions 6 and 7.

Therefore, the information stored in the memory cell is now "0".

In other words, when electrons are accumulated in the N'' region 6, conduction occurs between the N'' region 6 and the N'' region 7, which serves as a bit line, so that this N'' region, which was previously held at an intermediate potential, When the potential of the `` region 7 decreases, and conversely, the stored information of the memory cell is ``1'', that is, when no electrons are stored in the N+ region 6, this conduction causes the potential of the N'' region 7, which was at an intermediate potential, to decrease. The potential will rise.

This change in the potential of the bit line is sensed by a sense amplifier (not shown), amplified and taken out, and the same stored information is refreshed and written into the memory cell again within the same cycle.

[Problem that the invention seeks to solve]

Conventional memory cells are constructed in this way, and because the charge storage region and bit line are formed of an N degree page area or an N degree inversion layer, radiation such as alpha rays is not allowed to enter the memory chip. Of the electron-hole pairs generated upon incidence, electrons are collected in these charge storage regions and bit lines, inverting the original stored information. For this reason, there is a drawback that malfunctions (hereinafter referred to as soft errors) occur.

In addition, in order to eliminate the above-mentioned drawbacks, as shown in FIG. 3, a P-type region 12 is formed around the N'' region 6 as a charge storage region to increase the cell capacity, and the cell capacitance is increased. Some devices have been designed to prevent soft errors by increasing the critical charge amount in order to prevent malfunctions even if electrons collected in this charge storage region are used as bit lines.
Region 7 is not protected against absorption of electrons, and additionally providing a P-wall region around this N1 region 7 results in opposing P-wall regions within a narrow spacing of at most 2-3 μm. This results in a parasitic PNP transistor operation, making it difficult to operate the pass transistor stably.

This invention was made to eliminate the above-mentioned drawbacks of the conventional technology, and it is possible to eliminate rough 1 errors caused by radiation such as alpha rays with a simple structure without impairing transistor characteristics even in a miniaturized structure. An object of the present invention is to obtain a semiconductor memory device as described above.

[Means for solving problems]

The semiconductor memory device according to the present invention includes a semiconductor memory device containing a P-type impurity such as poron directly below the N''?7I region which is connected to the bit line wiring through the contact hole in the second N-conductivity type region. A first P'' conductivity type high concentration region having a concentration higher than that of the P-type semiconductor substrate by one order of magnitude or more is formed by spin-coating coatable silica glass and heat-treating the coatable silica glass.

[Effect]

In this invention, a P'' region with a higher concentration than the P- type substrate is formed directly under the N'' region connected to the bit line.
The capacitance of the N'' region serving as a bit line increases, and it is possible to prevent electrons from diffusing from the P- type substrate to the N'' region serving as a bit line, thereby eliminating the occurrence of soft errors.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor memory device according to an embodiment of the present invention. In the figure, the same reference numerals as those in FIGS. 2 and 3 indicate the same or corresponding parts, and 13 indicates N as a bit line.
Immediately below the ``region 7'' is a P'' region, which is implanted and diffused so as not to spread laterally beyond this region, and has a concentration that is at least one order of magnitude higher than that of the P-type semiconductor substrate 1. Here the P- concentration is 10'
2~'6/cn1. P'' concentration is 1014 to 18/-.

Next, a method of forming this embodiment device will be explained. First, P'' impurities were selectively implanted and diffused into the P- type semiconductor substrate 1 to form P'' regions 9 for inversion and parasitic prevention, and at the same time, element isolation insulating films 8 were formed respectively. 6. N″ area 6. P″ region 12. Gate electrodes 2, 3°N″ region 5.7 is formed. Thereafter, an interlayer insulating film 14 is deposited and a contact hole 15 is opened by etching.

Next, using this contact hole as a mask, spin-coatable silica glass containing P-type impurity ions such as boron is spin-coated, and a P'' head region 13 is formed by subsequent heat treatment.

Region 13 is the contact hole portion N + f, l
It is formed in a self-aligned manner using contact holes so as not to spread laterally beyond the castle 11. After wiring, a protective film (not shown) made of a low dielectric constant material (for example, PSG) is formed over the entire surface.

Next, the effects will be explained.

The above-mentioned soft error is caused by the fact that among the electron-hole pairs generated when radiation such as alpha rays enters the chip, electrons are collected in the charge storage region or the N゛゛ region 5, 6.7, which serves as the bit line. caused by being caused. In other words, before the α rays that enter the chip lose energy and stop, they generate many electron-hole pairs along their range, and the depletion layer 10.11
The electron-hole pairs generated within the depletion layer are immediately separated by the electric field inside the depletion layer, and the electrons are collected in the N'' region 5, 6.7, and the genuine tag flows down through the substrate 1.
．． Since the electron-hole pairs generated inside the substrate 1 recombine, they do not contribute to the increase or decrease of electrons at all, and the depletion layers 10, 11 are formed by diffusion of the electron-hole pairs generated inside the substrate 1. Only the electrons that have reached N.

These will be collected in areas 6, 7 and cause soft errors, while others will be recombined within the substrate 1.

Therefore, in this embodiment, P-
By forming the p+bi region 13 with a higher concentration than that of the type substrate 1, firstly, the width of the depletion layer 11 formed at the interface between the N'' region 7 and the P'' region 13 becomes smaller, and the capacitance of the N'' region 7 decreases. becomes large, and secondly, the N+bp region 7 becomes the P" region 13.
Because the electrons diffused from the P-type substrate 1 are recombined within the P'' region 13 and do not reach the region 7, thirdly, the P-type substrate 1 and the P'' region Since a potential barrier against electrons is formed at the interface of P-
Of the electrons diffused from the substrate 1, those with low energy are not allowed to pass through. And by the first point, area 7
The difference in the number of electrons corresponding to "0" and "1" read out in the second and third
This makes it possible to prevent electrons from diffusing into the N'' region 7, thereby eliminating the occurrence of soft errors.

In the above embodiment, the P+g region was formed directly under the N1 layer in the bit line region, but the present invention also applies to the N'' region of the sense amplifier and the portion where the contact hole is formed in the N'' region of the peripheral circuit. Applicable to

Furthermore, although the above embodiment describes a dynamic type semiconductor device, the present invention is equally applicable to a static type semiconductor device, as well as when an N channel is a P channel, and when a bipolar device is used instead of a MOS device. can also be applied.

〔Effect of the invention〕

As described above, according to the semiconductor memory device of the present invention, the concentration of P is at least one order of magnitude higher than that of the P- type substrate directly under the N-type region connected to the bit line.

Since the mold area is formed, malfunctions caused by radiation such as α rays entering the memory chip can be prevented.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the structure of a semiconductor memory device according to an embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views showing the structure of semiconductor memory devices according to various conventional examples. l...P-type semiconductor substrate, 2, 3... first layer, second
Gate electrode of layer, 6, 7...N'' region 8... Inter-element isolation insulating film, 10.11... Depletion layer, 13... P-
region.

Claims (3)

[Claims] (1) On a first P^- conductivity type semiconductor substrate, second N^+ conductivity type regions as a charge storage region and a bit line, and gate electrodes in the first layer and second layer. forming a second N^+ conductivity type region as a bit line on the semiconductor substrate; forming a contact hole on this region for connecting this region with the bit line; The second N^+ as a bit line in the second N^+ conductivity type region is formed by spin-coating silica glass containing a P-type impurity such as boron, which can be spin-coated, and then heat-treating the second N^+ conductivity type region. Under the conductivity type region, a first P whose temperature is one order of magnitude or more higher than the temperature of the substrate.
A semiconductor memory device characterized by forming a high concentration region of ^+ conductivity type. (2) The above semiconductor substrate has a P^- concentration of 10^1^3
^~^1/cm^3, and the above high concentration region is that P^
2. The semiconductor memory device according to claim 1, wherein the + concentration is 10^1^4^ to^1^8/cm^3. (3) The semiconductor memory device according to claim 1 or 2, wherein the gate electrode has a passivation film made of a material with a low dielectric constant above the gate electrode.