JPS62179144A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent a semiconductor memory device from erroneous operation to be generated according to incidence into a memory chip of a radial rays such as alpha-rays, etc. by a method wherein a P<+> type region having concentration higher by one figure or more than a P<-> type substrate is formed directly under an N<+> type region to be connected to a bit line. CONSTITUTION:By forming a P<+> type region 13 having concentration higher than that of a P<-> type substrate 1 directly under an N<+> type region 7, width of a depletion layer 11 to be formed at the interference between the N<+> type region 7 and the P<+> type region 13 is narrowed, and thereby capacity of the N<+> type region 7 is enlarged. Because the N<+> type region 7 is formed right above the P<+> type region 113, electrons scattered from the P<-> type subtrate 1 recombine in the P<+> type region 13, and never reach the region 7. Moreover because a potential barrier is formed against electrons at the interface between the P<-> type substrate 1 and the P<+> type region 13, out of electrons scattered from the P<-> type substrate 1, electrons having small energy are not allowed to pass the barrier. Accordingly generation of a soft error can be checked.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device that uses the presence or absence of electric charge as stored information.

[Conventional technology]

As an example of a conventional semiconductor device of this type, the structure of a memory cell of a dynamic MO3RAM is shown in FIG. That is, in FIG. 2, 1 is a semiconductor substrate having P-type conductivity, 2 and 3 are gate electrodes of the first N and second layers, 4 is a gate insulating film, 6 is a gi charge S product region, and 7 is a semiconductor substrate having P-type conductivity. 8 is an N'' region as a bit line, 8 is an isolation insulating film between elements, 9 is an inversion and P1 region for preventing parasitic effects, 10.
11 is a depletion layer, 14 is an interlayer insulating film, 15 is a contact hole, 16 is a word line, and 17 is a capacitor power supply.

In such a device, when the potential of the word line increases and the potential of the second layer gate electrode 3 as a transfer gate connected to this word line becomes higher than the threshold voltage, the voltage immediately below this gate electrode 3 increases. A channel of the N0 inversion layer is formed, and conduction occurs between the two N'' openings 6.7.

Therefore, the information stored in the memory cell is now “O”.

In other words, when electrons are accumulated in the N'' region 6, conduction occurs between the N'' region 6 and the N'' region 7, which serves as a bit line, so that this N'' region, which was previously held at an intermediate potential, When the potential of the ``region 7'' decreases and, conversely, the stored information of the memory cell is ``1'', that is, no electrons are stored in the N'' region 6, this conduction causes the N'' region, which was at an intermediate potential, to drop. The potential of 7 will rise. This change in the potential of the bit line is sensed by a sense amplifier (not shown), amplified and taken out, and the same stored information is refreshed and written into the memory cell again within the same cycle.

[Problem that the invention seeks to solve]

Conventional memory cells are configured in this way, and since the charge storage region and bit line are formed of an N'' region or an N0 inversion layer, radiation such as alpha rays may enter the memory chip. Among the generated electron-hole pairs, electrons are collected in these charge storage regions and bit lines, inverting the original stored information.This has the disadvantage of causing malfunctions (hereinafter referred to as soft errors). was there.

In addition, in order to eliminate the above-mentioned drawbacks, as shown in FIG. 3, a P-type region 12 is formed around the N'' region 6 as a charge storage region to increase the cell capacity, and the cell capacitance is increased. Some devices have been designed to prevent soft errors by increasing the critical charge amount in order to prevent malfunctions even if electrons collected in this charge storage region are used as bit lines.
Region 7 is not protected against absorption of electrons, and additionally providing a P wall region around this N'' region 7 results in opposing P wall regions within a narrow spacing of at most 2-3 μm. This results in parasitic PNP transistor operation, making it difficult to operate the pass transistor stably.

This invention was made to eliminate the above-mentioned drawbacks of the conventional technology, and eliminates soft errors caused by radiation such as alpha rays with a simple structure without affecting transistor characteristics even in a miniaturized structure. The object of the present invention is to obtain a semiconductor memory device that can perform the following steps.

[Means for solving problems]

The semiconductor memory device according to the present invention has a concentration that is at least one order of magnitude higher than that of the P- type semiconductor substrate immediately below the N'' region connected to the bit line wiring through the contact hole in the second N'' conductivity type region. A first P conductivity type high concentration region is formed.

[Effect]

In this invention, since the P'' region with a higher concentration than the P- type substrate is formed directly under the N''' fighting region connected to the bit line, the capacitance of the N'' region as a bit line is large (and It is possible to prevent electrons from diffusing from the P-type substrate to the N'' region serving as a bit line, thereby eliminating the occurrence of soft errors.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor memory device according to an embodiment of the present invention. In the figure, the same reference numerals as those in FIGS. 2 and 3 indicate the same or corresponding parts, and 13 indicates N as a bit line.
Immediately below the ``region 7'' is a P'' region which is implanted and diffused so as not to spread laterally beyond this region and has a concentration higher than that of the P-type semiconductor substrate 1 by at least one order of magnitude. P- here? M degree is 10
13~'6/cd, P' concentration is 10'4~Ill/cd.
It is crA.

Next, a method of forming this embodiment device will be explained. First, a P'' impurity is selectively implanted and diffused into the P- type semiconductor substrate 1 to form a P'' region 9 for inversion and parasitic prevention, and at the same time, an element isolation insulating film 8 is formed respectively. , N'' region 6. by normal forming procedure. P″ region 12. Gate electrode 2.3°N″ region 5.7 is formed. Thereafter, an interlayer insulating film 14 is deposited and a contact hole 15 is opened by etching.

Next, using this contact hole as a mask, P-type impurity ions such as boron are implanted at an appropriate acceleration voltage, and a p-1M region 13 is formed by subsequent heat treatment. At this time, the P'' region 13 is formed in a self-aligned manner using the contact hole so that it does not spread laterally beyond the N'' region 11 in the contact hole portion. And after wiring,
A protective film made of PSG, a low dielectric material, on the entire surface (not shown)
form.

Next, the effects will be explained.

The above-mentioned soft error occurs when the electrons are collected in the charge storage region or the N' regions 5, 6.7, which serve as bit lines, among the electron/genuine tag pair generated when radiation such as alpha rays enters the chip. caused by In other words, before the α rays that enter the chip lose energy and stop, they generate a large number of electron-hole pairs along their range, and the depletion jglo,
The electron-hole pairs generated in 11 are immediately separated by the electric field inside the depletion layer, the electrons are collected in the N'' region 5.6.7, and the holes flow down through the substrate 1. Since the electron/hole pairs generated inside the region 6.7 recombine, they do not contribute to the increase or decrease of electrons at all, and due to the diffusion of the electron/hole pairs generated inside the substrate 1, a depletion layer is created. 10.1
Only the electrons that reach 1 will be collected in the N' region 6.7 and cause a soft error, while the others will be recombined within the substrate 1.

Therefore, in this embodiment, P-
By forming the P'' region 13 with a higher concentration than the type substrate 1, firstly, the width of the depletion fill formed at the interface between the N1 region 7 and the P'' region 13 becomes smaller, and the capacitance of the N'' region 7 increases. secondly, N3 region 7 becomes P″ region 1゛3
Because the electrons diffused from the P-type substrate 1 are recombined within the P'' region 13 and do not reach the region 7, thirdly, the P-type substrate 1 and the P'' Since a potential barrier against electrons is formed at the interface of the space region 3, P-
Among the electrons diffused from the substrate 1, those with low energy are not allowed to pass through, and the first point creates a region 7.
The difference in the number of electrons corresponding to 0'' and ``1'' read out becomes large, and it is possible to provide a margin for electrons generated by the incidence of alpha rays, etc., and due to the second and third points, N ``It is possible to prevent electrons from diffusing into the region 7, thereby eliminating the occurrence of soft errors.

In the above embodiment, the P'' region was formed directly under the N layer of the bit line region, but the present invention
The same applies to the EAP region and the N'' region of the peripheral circuit where contact holes are to be formed.

Furthermore, although the above embodiment describes a dynamic type semiconductor device, the present invention is equally applicable to a static type semiconductor device, as well as when an N channel is a P channel, and when a bipolar device is used instead of a MOS device. can also be applied.

〔Effect of the invention〕

As described above, according to the semiconductor memory device of the present invention, a P'-type region with a concentration higher than that of the P-type substrate by one order of magnitude or more is formed directly under the N°-type region connected to the bit line. This has the effect of preventing malfunctions caused by radiation such as α rays entering the memory chip.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the structure of a semiconductor memory device according to an embodiment of the present invention, and FIGS. 2 and 3 are sectional views showing the structure of each conventional semiconductor memory device. ■... P- type semiconductor substrate, 2.3... 1st N, 2nd
gate electrode of layer, 6.7...N'' region 8... element isolation insulating film, 10.11... depletion layer, 13...P''
region

Claims (4)

[Claims] (1) On a first P^- conductivity type semiconductor substrate, second N^+ conductivity type regions as a charge storage region and a bit line, and first and second layer gate electrodes are provided. In the semiconductor memory device in which the second N^+ conductive region is provided under the second N^+ conductive type region serving as a bit line, and has a concentration one or more orders of magnitude higher than the concentration of the substrate. A semiconductor memory device comprising a first P^+ conductivity type high concentration region. (2) The first P^+ conductivity type high concentration region is formed by forming a second N^+ conductivity type region as a bit line on the semiconductor substrate, and then forming a bit line on this region. A patent claim characterized in that it is formed by forming a contact hole for making a connection with the contact hole, then using this contact hole as a mask, ions of P-type impurity such as boron are implanted, and heat treatment is performed. The semiconductor memory device according to item 1. (3) The above semiconductor substrate has a P^- concentration of 10^1^3
^~^1^6/cm^2, and the high concentration region has a P^+ concentration of 10^1^4^~^1^■/cm^2. The semiconductor memory device according to item 1 or 2. (4) The above gate electrode has PSG of low dielectric material above it.
4. A semiconductor memory device according to claim 1, further comprising a passivation film made of: