JPH03257863A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize good flatness of a surface of a memory cell section by forming a first conductivity type gate electrode of a transistor and a second conductivity type cell plate which constitutes an electrode of a capacitor of the same polycrystalline silicon film integrally. CONSTITUTION:After a resist pattern 11 of a specified configuration whose section corresponding to word lines WL3 to WL6 is opened, p-type impurities are ion-implanted into a polycrystalline Si film 10. Then, after the resist pattern 11 is removed, electrical activation and diffusion of ion-implanted impurities are carried out. Then, a trap in the polycrystalline Si film 10 is non-activated by adding hydrogen. Thereby, an n<+>-type source region 6 and an n<->-type semiconductor region 7 are formed in a p-well 2. Word lines WL5, WL6 which consist of a p<+>-type polycrystalline Si film and a cell plate CP2 which consists of the n<+>-type polycrystalline Si film 10 are formed integrally. Similary, work lines WL3, WL4 which consist of p<+>-type polycrystalline Si film and cell plate CP2 which consists of the n<+>-type polycrystalline Si film 10 are formed integrally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and is particularly suitable for application to a semiconductor memory device having a 1-transistor l-capacitor type memory cell.

[Summary of the Invention] The present invention provides a semiconductor memory device having a memory cell including one transistor and one capacitor.
A gate electrode of a first conductivity type of a transistor and a cell plate of a second conductivity type constituting an electrode of a capacitor are integrally formed of the same polycrystalline silicon film. This makes it possible to improve the flatness of the surface of the memory cell portion and to simplify the manufacturing process of the semiconductor memory device.

[Prior art] In recent highly integrated MOS dynamic RAMs,
A one-transistor, one-capacitor type memory cell is used (for example, Nikkei Electronics, June 1985).
3rd issue, pp. 209-231). Conventionally, MOS using this one-transistor capacitor type memory cell
As a dynamic RAM, the one shown in FIG. 5 is known, in which the cell plate is formed of a first layer of polycrystalline silicon (St) film, and the word line is formed of a second layer of polycrystalline St film. There is. That is, in FIG.
Reference numeral 101 is, for example, a P-type Si substrate, 102 is a field insulating film, 103 is a gate insulating film, CP' is a cell plate formed of the first layer of polycrystalline 54III, and WL.
' is a word line formed by the second layer of polycrystalline Si film, 104 is word line I%1iWL' and cell play 1-CP.
' shows an insulating film for insulation. Here, the word line WL
A part of ' is overlaid on cell play 1-CP'. Further, reference numeral 105 indicates, for example, an n" type source region. An access transistor is formed by the word 1iWL' and this source region 105. In this case, the word line WL' and the cell plate CP' are adjacent to each other. Since the gate insulating film 1 is formed as a gate insulating film 1, there is no need to form a drain region of the access transistor.
A capacitor is formed by the cell plate CP' and the P-type Si substrate 101, which face each other with 03 in between. Although not shown, the source region 105 is connected to a bit line made of aluminum (AI). In addition, the power supply voltage ■ is applied to the cell plate cP'. , is applied.

[Problem to be solved by the invention]

The conventional MOS dynamic RAM shown in FIG. 5 described above has a word line WL' formed by a second layer of polycrystalline Si film on a cell plate CP' formed by a first layer of polycrystalline Si film. Since a portion of the memory cell portion overlaps, a large step exists in this overlapped portion, resulting in poor surface flatness of the memory cell portion.

In addition, the cell plate CP'' is formed of a first layer of polycrystalline Si film, and the word line WL' is formed of a second layer of polycrystalline Si film.
Since it is formed from a film, the manufacturing process is also complicated.

Therefore, an object of the present invention is to provide a semiconductor memory device that can improve the surface flatness of a memory cell portion.

Another object of the present invention is to provide a semiconductor memory device whose manufacturing process can be simplified.

[Means to solve the problem]

To achieve the above object, the present invention provides a semiconductor memory device having a memory cell consisting of one transistor and one capacitor, in which a gate electrode of a first conductivity type (for example, WLS) of a transistor and a gate electrode of a first conductivity type of a capacitor are connected to each other. Second conductivity type cell plate (e.g. CP3) forming the electrode
are integrally formed of the same polycrystalline silicon film (10).

[Effect]

According to the semiconductor memory device of the present invention configured as described above, the gate electrode of the transistor (for example, WLs)
and the cell plate that constitutes the electrode of the capacitor (e.g.
CPs ) is the same polycrystalline silicon 1! (10), the surfaces of these gate electrodes (e.g., WLs) and cell plates (e.g., CP) are flat, thus improving the surface flatness of the memory cell portion. be able to. Further, since the gate electrode (for example, WLs) and the cell plate (for example, CP) can be formed using the same polycrystalline silicon film (10), the manufacturing process can be simplified accordingly.

Note that a pn junction is formed by the gate electrode of the first conductivity type of the transistor (for example, WLs) and the cell plate of the second conductivity type of the capacitor (for example, CP), and this pn junction allows these gate electrodes (for example, ,WLS
) and cell plates (eg, CPs).

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This embodiment demonstrates the present invention in a MOS dynamic R
This is an example applied to AM. In addition, in all the drawings of the embodiment, the same parts are given the same reference numerals.

FIG. 3 shows a MOS dynamic R according to an embodiment of the present invention.
FIG. 2 is a plan view showing an AM memory cell array. In FIG. 3, WL, ~W L s are word lines, BL, -BL
, are bit lines, 01 to C3 are bit lines BL, ~BL
Contact holes for x contacts are shown. In the memory cell array of the MOS dynamic RAM according to this embodiment, the pattern of the portion surrounded by the dotted chain line in FIG. 3 is regularly arranged. Therefore, in the following:
The portion surrounded by the dotted chain line in FIG. 3 will be explained.

An enlarged sectional view and a plan view of this portion are shown in FIGS. 1 and 2, respectively. Note that FIG. 1 is an enlarged sectional view taken along line 1-1 in FIG. 3.

As shown in FIGS. 1 and 2, the MO according to this embodiment
In S dynamic RAM, for example, p-type or n
A p-well 2 is formed in a semiconductor substrate 1 such as a type of Si substrate. This p-well 2 may be formed over the entire memory cell array, or may be formed in each portion surrounded by a dotted chain line in FIG. The code 3 is, for example, Si
1. n shows a field insulating film such as a film, and this field insulating film 3 provides isolation between elements. Although not shown, a p-type channel stop region, for example, is formed under the field insulating film 3. On the surface of the active region surrounded by this field insulating film 3, a gate insulating film 4 such as a Si0g film is provided.
is formed.

In this embodiment, word lines WLs, WL&, and cell lines CP are integrally formed of the same polycrystalline St film. Here, the word lines WL, , WL are formed of, for example, a p-type polycrystalline SN film, and the cell line (CP) is formed of, for example, an n''-type polycrystalline Si film. Line wt, s, WL
, and cell plate CP.

On the surface of the word line WL, there is a pn junction between the word line WL and the cell plate cps, and a pn junction between the word line WL and the cell plate cps,
For example, an insulating film 5 such as a SiOg film is formed to prevent junction leakage of the pn junction between the two.

Reference numeral 6 indicates, for example, an n3 type source region, and the word line WLs and this source region 6 form an n-channel M
O3) transistor is formed and this n-channel MO5)
An access transistor is formed by a transistor. In this case, for example, an n-type semiconductor region 7 is formed in the channel region below the word line WLS. Therefore, this access transistor normally
It is an on type, that is, a depletion type. This depletion type access transistor, cell plates CP facing each other with a gate insulating film 4 in between, and a capacitor formed by the p well 2 form an l transistor 1 capacitor type memory cell. . Note that the above-mentioned n-type semiconductor regions 7 are formed symmetrically on both sides of the source region 6.

Reference numeral 8 indicates a glabellar insulating film such as a phosphosilicate glass (PSG) film. The bit line B L z is in contact with the source region 6 through the contact hole C1 formed in the glabella insulating film 8 and the gate insulating film 4.

In the MOS dynamic RAM according to this embodiment, for example, a power supply voltage Vcc (eg, 5V) is applied to the cell plate (eg, CPs). Furthermore, when a memory cell is selected, for example, Ov is applied to the word line (for example, WL), and when it is not selected, for example, -Vcc""
A voltage of 5V is applied. Here, add 15■ to the word line.
When is applied, the depletion type access transistor is turned off. In this case, writing data to the memory cell or reading data from the memory cell can be performed by turning on/off a depletion type access transistor.

Note that, as mentioned above, since VCC is applied to the cell plate (for example, CP,) and O to -5■ is applied to the word line (for example, WL,), The pn junction formed by the word line wAWL made of a crystalline Si film and the cell plate CP made of an n9 type polycrystalline St film is always reverse biased, so these word lines WLs and cell plate CPS are electrically connected. are separated.

Next, the MOS according to this embodiment configured as described above
A method for manufacturing a dynamic RAM will be explained. Note that this description will be made regarding the cross section shown in FIG.

As shown in FIG. 4A, first a p-well 2 is formed in a semiconductor substrate 1, and then a field insulating film 3 is formed by selectively thermally oxidizing the surface of this p-well 2, thereby providing isolation between elements. Next, a gate insulating film 4 is formed on the surface of the active region surrounded by the field insulators 1!3 by, for example, thermal oxidation.

Next, a resist pattern 9 having a predetermined shape with openings corresponding to the n3 type source region 6 and n- type semiconductor region 7 described above is formed by lithography. For example, an n-type impurity such as phosphorus (P) or arsenic (As) is ion-implanted into the p-well 2 (the n-type impurity ion-implanted into the p-well 2 is indicated by .

Next, after removing the resist pattern 9, as shown in FIG. 4B, the first layer of polycrystalline Si is deposited on the entire surface by CVD
N! 10 is formed, and this polycrystalline 54 film IO is patterned by etching into a predetermined shape.

Next, as shown in FIG. 4C, an n-type impurity such as P or As is ion-implanted into the p-well 2 using the patterned polycrystalline Si film 10 as a mask.

Next, as shown in the fourth diagram, the word lines WLs~
After forming a resist pattern 11 of a predetermined shape with openings corresponding to WL by lithography, using this resist pattern 11 as a mask, an n-type impurity such as boron (B) is ion-implanted into polycrystalline Si#10. (The n-type impurity ion-implanted into the polycrystalline Si film 10 is indicated by a circle).

Next, after removing the resist pattern 11, the ion-implanted impurities are electrically activated and diffused by performing annealing at a high temperature in a nitrogen atmosphere, for example.

Then, annealing is performed at a relatively low temperature in a hydrogen atmosphere (
Hydrogen annealing) is performed to inactivate the traps in the polycrystalline 54 film 10 by hydrogen addition. With this, the fourth
As shown in the figure, an n' type source region 6 and an n- type semiconductor region 7 are formed in the p well 2. Further, word lines WL, , WL made of a p-type polycrystalline Si film, and a cell plate CP made of an n-type polycrystalline St film 10 are provided.
s is integrally formed. Similarly, the word line WL! is made of a p-type polycrystalline Si film! , W.L.

and a cell layer consisting of an n9 type polycrystalline St film 10)C
P is also integrally formed.

Next, as shown in FIG. 1, the word line WL.

An insulating film 7 such as a 5ift film is formed on the surface of the WLb and cell layer CP by thermal oxidation. An insulating film 7 is similarly formed on the surfaces of the word lines wLs, WL4 and the cell plate CPt. Next, after forming a glabellar insulating film 8 such as a PSG film on the entire surface by CVD, this interlayer insulating film is Predetermined portions of the film 8 and gate insulating film 4 are removed by etching to form a contact hole C4. Thereafter, the interlayer insulating film 8 is reflowed as necessary to improve the shape of the contact hole CJ. Next, the entire surface is coated with, for example, aluminum (AI) by, for example, sputtering.
) film is formed, and this AI film is patterned into a predetermined shape by etching to form a bit line BL. As a result, the desired MOS dynamic RAM using a negative layer of polycrystalline St film and one layer of AI wiring is completed.

As described above, according to this embodiment, the word 'IA' forming the gate electrode of the access transistor of the memory cell is
Since W L s and the capacitor cell plate CP 3 are integrally formed of the same polycrystalline Si film,
These words &91 W L S and cell plate C
The surface of P becomes flat, so that the surface flatness of the memory cell portion can be improved.

In addition, the word line W L
Since the word line WLs and cell plate CP can be formed, the MOS
The manufacturing process of the dynamic RAM can be simplified. Furthermore, the MOS dynamic RAM according to this embodiment
The structure itself is simpler than the conventional MOS dynamic RAM.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, the layout of the memory cell array shown in FIG. 3 is merely an example, and it goes without saying that a different layout can be used.

In addition, when the distance between adjacent word lines across the contact hole for bit line contact is small and it is difficult to make contact with the bit line, for example, as shown by the dashed line in FIG. 2, the bit line BLz By increasing the distance between the word lines WL, , WL in the periphery of the contact hole C1, it is possible to make contact with the bit lines more easily.

〔Effect of the invention〕

As described above, according to the present invention, the gate electrode of the first conductivity type of the transistor and the cell plate of the second conductivity type constituting the electrode of the capacitor are integrally formed of the same polycrystalline silicon film. Therefore, the surface flatness of the memory cell portion can be improved, and the manufacturing process of the semiconductor memory device can be simplified.

[Brief explanation of drawings]

FIG. 1 shows a MOS dynamic R according to an embodiment of the present invention.
2 is a cross-sectional view showing the main parts of an AM, FIG. 2 is a plan view showing the main parts of a MOS dynamic RAM according to an embodiment of the present invention, and FIG. 3 is a MOS dynamic RA according to an embodiment of the present invention.
FIGS. 4A to 4E are plan views showing a memory cell array of M, and FIGS. 4A to 4E are MOS dynamic RAM according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a conventional MOS dynamic RAM. Explanation of main symbols in the drawings 1: Semiconductor substrate, 2: P well, 3: Field insulating film, 4: Gate insulating film, 6: Source region, 7:
Semiconductor region, 8: Interlayer insulating film,: Polycrystalline St film, WL, -WL,: Word line, BL, -BL3: Bit line, 1 - C3: Contact hole.

Claims (1)

[Claims] In a semiconductor memory device having a memory cell consisting of one transistor and one capacitor, a gate electrode of a first conductivity type of the transistor and a gate electrode of a second conductivity type constituting an electrode of the capacitor are provided. A semiconductor memory device characterized in that a cell plate and a cell plate are integrally formed of the same polycrystalline silicon film.