JPS62252955A - Package - Google Patents
PackageInfo
- Publication number
- JPS62252955A JPS62252955A JP19761586A JP19761586A JPS62252955A JP S62252955 A JPS62252955 A JP S62252955A JP 19761586 A JP19761586 A JP 19761586A JP 19761586 A JP19761586 A JP 19761586A JP S62252955 A JPS62252955 A JP S62252955A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- silicon
- silicone
- leads
- package according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 44
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 239000010703 silicon Substances 0.000 claims abstract description 43
- 239000007788 liquid Substances 0.000 claims abstract description 7
- 229920001296 polysiloxane Polymers 0.000 claims description 26
- 229920001187 thermosetting polymer Polymers 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 abstract description 6
- 239000004020 conductor Substances 0.000 abstract description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000001816 cooling Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229920002050 silicone resin Polymers 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- KGWWEXORQXHJJQ-UHFFFAOYSA-N [Fe].[Co].[Ni] Chemical compound [Fe].[Co].[Ni] KGWWEXORQXHJJQ-UHFFFAOYSA-N 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 238000005470 impregnation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電子部品が実装され設計変更および修理が容易
なパッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package in which electronic components are mounted and whose design can be easily changed and repaired.
従来、この種のパッケージでは、基板上に７エイスアツ
プの状態で集積回路（ＩＣ）チップを搭載し、このチッ
プと基板とはリードによシミ気的に接続されている。さ
らに１チツプおよびリードを覆うよう基板上にシリコン
樹脂がコーティングされる。このコーティングは、基板
上の配線やリード等を湿気から保膿するために行なう。Conventionally, in this type of package, an integrated circuit (IC) chip is mounted on a substrate in a 7-eighth-up state, and the chip and the substrate are electrically connected by leads. Furthermore, silicone resin is coated on the substrate so as to cover one chip and the leads. This coating is performed to protect the wiring, leads, etc. on the board from moisture.
従来パッケージの一例が、Ｂｒａｄ ０１ｄｅｒ ａｎ
ｄ Ｒｉｃｈａｒｄ Ａ 、 。An example of a conventional package is Brad 01der an
d Richard A.
＠Ｎｏｎ−ｎｅｒｍａｔｉｃ ｐａｃｋａｇｉｎｇ ｔ
ｅｃｈｎｉｑｕｅｓ ｆｏｒ ｈｉｂｒｉｄｓ”。@Non-nermatic packaging
technology for hybrids”.
Ｅｌｅｃｔｒｏｎｉｃ Ｐａｃｋａｇｉｎｇ ａｎｄ
Ｐｒｏｄｕｃｔｉｏｎ 、 Ｊｕｎｅ 、 １９７９゜
Ｐ１３７〜１３９ に開示されている。Electronic Packaging and
Production, June, 1979, pp. 137-139.
このような従来のパッケージでは、チップの交換時に、
リードとチップの下面と基板の上面とで囲まれた空間の
シリコーン樹脂の除去が困雛である。また、シリコーン
樹脂を除去するためにパッケージを有機容剤に浸せきさ
せると、シリコーン樹脂が膨張してリードが切れたり、
基板から剥れたりする可能性がある。With these traditional packages, when replacing the chip,
It is difficult to remove the silicone resin in the space surrounded by the leads, the bottom surface of the chip, and the top surface of the substrate. Also, if the package is immersed in an organic solution to remove the silicone resin, the silicone resin will expand and the leads may break.
It may peel off from the board.
本発明の目的は上述の欠点を除去したパッケージを提供
することにある。The object of the invention is to provide a package which eliminates the above-mentioned disadvantages.
本発明のパッケージは、基板と、前記基板上に形成され
た複数のパッドと、前記パッドと接続される複噂のリー
ドを有し前記基板上に実装された少なくとも１つの電子
部品と、前記リードと前記電子部品の下面と前記基板の
上面とで囲まれた空間に充填された液状の第１のシリコ
ンと、前記基板上および第１のシリコン上を覆う硬化し
た第２のシリコンとから構成される。The package of the present invention includes a substrate, a plurality of pads formed on the substrate, multiple leads connected to the pads, at least one electronic component mounted on the substrate, and the leads. and a liquid first silicon filled in a space surrounded by a lower surface of the electronic component and an upper surface of the substrate, and a hardened second silicon that covers the substrate and the first silicon. Ru.
第１図を参照すると、本発明の一実施例は、複数の導体
配線１を含む基板３と、基板３の下面に設けられた複数
の入出力ビン２と、基板３の上面に設けられた複数のパ
ッド８と、基板３の上面の周囲に接着剤（例えば、チッ
化ホウ素入りエポキシ接着剤）によ如取り付けられた鉄
−ニッケルーコバルト合金等からなる枠材１０と、基板
３の上面と対向するよう枠材１０に接着剤により取り付
けられたチッ化アルミ等からなるキャップ１３と、基板
３の上面に接着剤により固定されシリコンゴム等からな
る複数のスベーテ９と、スペーｆ９上に接着剤により固
定された複数の集積回路（ＩＣ）チップ４と、基板３の
上面とキャップ１３の下面と枠材１０の側面とで囲まれ
る空間に後述する方法で充填された第１のシリコン１１
および第２のシリコン１２とから構成される。キャップ
１３の上面には、空冷用ヒートシンクまたは水冷用冷却
板を取り付けてもよい。キャップ１３の下面とＩＣチッ
プ４の上面との間には、熱伝導性のよいコンパウンドを
挿入してもよい。ＩＣチップ４で発生した熱は直接また
はコンパウンドを介してキャップ１３に伝達され、さら
に、ヒートシンクまたは冷却板を介して外部に発散され
る。枠材１０を電気的絶静材料で形成した場合には、接
着剤として導電性失着剤を使用できる。Referring to FIG. 1, one embodiment of the present invention includes a board 3 including a plurality of conductor wirings 1, a plurality of input/output bins 2 provided on the bottom surface of the board 3, and a plurality of input/output bins 2 provided on the top surface of the board 3. A frame member 10 made of an iron-nickel-cobalt alloy or the like is attached around the upper surface of the substrate 3 with a plurality of pads 8 and an adhesive (for example, an epoxy adhesive containing boron nitride), and the upper surface of the substrate 3. A cap 13 made of aluminum nitride or the like is attached to the frame material 10 with an adhesive so as to face it, a plurality of substrates 9 made of silicone rubber or the like are fixed to the upper surface of the substrate 3 with an adhesive, and are glued on the space f9. A first silicon 11 is filled in a space surrounded by a plurality of integrated circuit (IC) chips 4 fixed with a chemical agent, the upper surface of the substrate 3, the lower surface of the cap 13, and the side surface of the frame member 10 by a method described later.
and second silicon 12. An air-cooling heat sink or a water-cooling cooling plate may be attached to the upper surface of the cap 13. A compound with good thermal conductivity may be inserted between the lower surface of the cap 13 and the upper surface of the IC chip 4. Heat generated in the IC chip 4 is transmitted to the cap 13 directly or via a compound, and is further dissipated to the outside via a heat sink or a cooling plate. When the frame member 10 is made of an electrically static material, a conductive detoxifying agent can be used as the adhesive.
チップ４の下面の周囲には、複数のリード５一端が微小
な間隔で取り付けられている。これらのチップ４から放
射状に伸びるリード５の他端はそれぞれパッド８にボン
ディング等により接続されている。この結果、ピン２と
チップ４内の回路とは、導体配７ｙｉ！１、パッド８お
よびリード５を介して電気的に接続される。One ends of a plurality of leads 5 are attached around the lower surface of the chip 4 at minute intervals. The other ends of leads 5 extending radially from these chips 4 are respectively connected to pads 8 by bonding or the like. As a result, pin 2 and the circuit in chip 4 are connected to conductor layout 7yi! 1, electrically connected via pad 8 and lead 5.
次にシリコンの充填法について説明する。Next, a silicon filling method will be explained.
まず、チップ４の基板３への実装後、スポイトまたは注
射器等を用いて粘性の高い液状の第１のシリコン１１を
チップ４の下面、リード５、スペーサ９の側面および基
板３の上面で囲まれる空間に充填する。この第１のシリ
コン１１としては、例えば、信越シリコン社１のシリコ
ーン含浸剤ＫＪＦ−８１２を・吏用できる。次に基板３
上に液状の第２のシリコン１２を流し込む。この第２の
シリコン１２としては、例えばＴｏｒａｙ Ｓｉｌｉｃ
ｏｎｅＣｏｍｐａｎｙ Ｌｔｄ、製の熱硬化形（７）
ＳＨＩ ８５１ｊ’ ルを使用できる。第１のシリコン
１１の粘性は第２のシリコン１２のそれに比べて高いた
め、第１のシリコン１１はチップ４の下面、リード５、
スペーサ９の側面および基板３の上面で囲まれる空間に
留まり、第２のシリコン１２内に混入しない。このあと
、パッケージ全体を約１２５℃の空気雰囲気中に１時間
〜２時Ｉ′ｉ！１程度推持し、概２のシリコン１２をゲ
ル状に硬化させる。このとき、第１のシリコン１１は硬
化しない。これらのシリコン１１および１２は基板３の
上面に形成された配線等を湿気等から保護する。First, after the chip 4 is mounted on the substrate 3, a highly viscous liquid first silicon 11 is surrounded by the lower surface of the chip 4, the leads 5, the side surfaces of the spacers 9, and the upper surface of the substrate 3 using a dropper or syringe. Fill the space. As the first silicon 11, for example, silicone impregnation agent KJF-812 manufactured by Shin-Etsu Silicon Co., Ltd. 1 can be used. Next, board 3
A liquid second silicon 12 is poured on top. This second silicon 12 is, for example, Toray Silic.
oneCompany Ltd, thermosetting type (7)
SHI 851j' can be used. Since the viscosity of the first silicon 11 is higher than that of the second silicon 12, the first silicon 11 is attached to the bottom surface of the chip 4, the leads 5,
It remains in the space surrounded by the side surface of the spacer 9 and the top surface of the substrate 3 and does not mix into the second silicon 12. After this, the entire package is placed in an air atmosphere at approximately 125°C for 1 to 2 hours. The silicone 12 of about 2 times is hardened into a gel state by holding it for about 1 minute. At this time, the first silicon 11 is not cured. These silicones 11 and 12 protect wiring and the like formed on the upper surface of the substrate 3 from moisture and the like.
なお、本実施例では第１のシリコンとして粘性の高いも
のを使用したが、粘性の低いものを使用してもよい。こ
の場合には、第１のシリコンを基板３上に流し込んたあ
と、基板３をひっくり返す。In this embodiment, a silicon with high viscosity is used as the first silicon, but a silicon with low viscosity may be used. In this case, after pouring the first silicon onto the substrate 3, the substrate 3 is turned over.
この結果、第１のシリコンの大部分は捨てられるが、チ
ップ４の下面、リード５、スペーサ９の側面および基板
３の上面で囲まれる空間には表面張力により第１ρシリ
コン１１が残る。このあと、第２のシリコンを流し込み
第２のシリコンのみを硬化させる。As a result, most of the first silicon is discarded, but the first ρ silicon 11 remains in the space surrounded by the lower surface of the chip 4, the leads 5, the side surfaces of the spacers 9, and the upper surface of the substrate 3 due to surface tension. After that, the second silicone is poured and only the second silicone is hardened.
さらに、第１および第２のシリコンとして同一の紫外線
硬化形のシリコンを使用してもよい。この場合には、基
板３上に紫外線硬化形のシリコンを流し込み、上方側か
ら紫外線を照射することにより、チップ４およびリード
５の影になる部分のシリコン１１が未硬化ないしは半硬
化状態となり、他の部分のシリコン１２はゲル状に硬化
する。このような紫外線硬化形のシリコンとしては例え
ば、東芝シリコーン社製のＴＵＶ６０００を使用できる
。Furthermore, the same ultraviolet curable silicone may be used as the first and second silicones. In this case, by pouring ultraviolet curable silicon onto the substrate 3 and irradiating it with ultraviolet rays from above, the silicon 11 in the shadow of the chip 4 and the leads 5 becomes uncured or semi-cured, and the other parts The silicon 12 in the portion hardens into a gel state. As such ultraviolet curable silicone, for example, TUV6000 manufactured by Toshiba Silicone Co., Ltd. can be used.
第３図を参照すると、本発明の第２の実施例は、第１の
実施例と同様に、基板３上にチップ４と枠材１０とが実
装される。次に、第１のシリコン２１が流し込まれたあ
と第２のシリコン２２が流し込まれる。この第１および
第２のシリコン２１および２２としては、それぞれ上述
のＫＪＦ−８１２および５Ｈ１８５１を使用できる。こ
のあと、このパッケージ全体を第１の実施例と同様の約
１２５℃の空気雰囲気中に約１〜２時間維持すると、第
２のシリコン２２のみがゲル状に硬化する。最後にキャ
ップ１３が枠材１０に取り付けけられてパッケージが完
成する。Referring to FIG. 3, in the second embodiment of the present invention, a chip 4 and a frame member 10 are mounted on a substrate 3, similar to the first embodiment. Next, after the first silicon 21 is poured, the second silicon 22 is poured. The above-mentioned KJF-812 and 5H1851 can be used as the first and second silicones 21 and 22, respectively. Thereafter, when the entire package is maintained in an air atmosphere at about 125° C. for about 1 to 2 hours, similar to the first embodiment, only the second silicon 22 hardens into a gel state. Finally, the cap 13 is attached to the frame material 10 to complete the package.
第２の実施例において、第２のシリコンは熱硬化形のも
のを使用したが、上述のＴＵＶ６０００のような紫外線
硬化形のシリコンを使用してもよい。In the second embodiment, a thermosetting silicone is used as the second silicon, but an ultraviolet curing silicone such as the above-mentioned TUV6000 may also be used.
この場合には、当然、紫外線を照射することによシ第２
のシリコンを硬化させる。In this case, of course, the second
harden the silicone.
このようにして組み立てられた本発明のパッケージの第
１および第２のシリコンをチップ交換等のために設計変
更時や修理時に除去する場合に、第１のシリコンは、第
２のシリコンをはがしたあと、有機溶剤により簡単に洗
い流すことができる。When the first and second silicones of the package of the present invention assembled in this way are removed at the time of design change or repair for chip replacement, etc., the first silicone is removed by peeling off the second silicone. After that, it can be easily washed away with an organic solvent.
したがって、第１および第２の実施例では、シリコン除
去時にリード５の切断やパッド８からのはがれが発生し
ない。Therefore, in the first and second embodiments, the leads 5 are not cut or peeled off from the pads 8 during silicon removal.
以上、本発明には、基板上に実装したＩＣチップ等の電
子部品を、設計変更時や修理時に損傷を与えることなく
容易に取り外せるという効果がある。As described above, the present invention has the advantage that electronic components such as IC chips mounted on a board can be easily removed without causing damage during design changes or repairs.
第１図および第２図はそれぞｎ本発明の第１の実施例の
断図図および平面図ならびに第３図は本発明の第２の実
施例の断面図である。
これらの図において、１・・・・・・導体配線、２・・
・・・・入出力ビン、３・・・・・・基板、４・・・・
・・ＩＣチップ、５・・・・・・リード、８・・・・・
・パッド、９・・・・・・スペーサ、１０・・・・・・
ｎ材、１１．２１・・・・・・第１のシリコン、１２．
２２・・・・・・第２のシリコン、１３・・・・・・キ
ャップ。 −１代理人 弁理士 内 原 ２′
白 ｔ
＼−一′ノ
牛 １ 図
第 ２ 図
第３ 図1 and 2 are a sectional view and a plan view, respectively, of a first embodiment of the invention, and FIG. 3 is a sectional view of a second embodiment of the invention. In these figures, 1... conductor wiring, 2...
...Input/output bin, 3... Board, 4...
...IC chip, 5...Lead, 8...
・Pad, 9... Spacer, 10...
n material, 11.21...first silicon, 12.
22...Second silicon, 13...Cap. -1 Agent Patent Attorney Uchihara 2' Shirot \-1' No Ushi 1 Figure 2 Figure 3
Claims (1)
に実装された少なくとも１つの電子部品と、 前記リードと前記電子部品と前記基板とで囲まれた空間
に充填された液状の第１のシリコンと、 前記基板上および第１のシリコン上を覆う硬化した第２
のシリコンとから構成したことを特徴とするパッケージ
。 ２ 前記基板上の周囲に設けた枠状部材と、前記基板上
を覆うよう前記枠状部材に取り付けたキャップとを含む
ことを特徴とする特許請求の範囲第１項記載のパッケー
ジ。 ３ 前記第２のシリコンが熱硬化形のシリコンであるこ
とを特徴とする特許請求の範囲第１項記載のパッケージ
。 ４ 前記第２のシリコンが紫外線硬化形のシリコンであ
ることを特徴とする特許請求の範囲第１項記載のパッケ
ージ。 ５ 前記第１のシリコンが紫外線硬化形のシリコンであ
ることを特徴とする特許請求の範囲第４項記載のパッケ
ージ。 ６ 基板と、 前記基板上に形成された複数のパッドと、 前記パッドと接続される複数のリードを有し前記基板上
に実装された少なくとも１つの電子部品と、 前記基板上の周囲に取り付けられた枠状部材と、 前記基板と前記枠状部材とで囲まれる空間内に少なくと
も前記複数のリードが浸積されるまで充填された液状の
第１のシリコンと、 前記第１のシリコン上に形成された硬化した第２のシリ
コンとから構成したことを特徴とするパッケージ。 ７ 前記第２のシリコンは熱硬化形のシリコンであるこ
とを特徴とする特許請求の範囲第６項記載のパッケージ
。 ８ 前記第２のシリコンは紫外線硬化形のシリコンであ
ることを特徴とする特許請求の範囲第６項記載のパッケ
ージ。[Scope of Claims] 1. A substrate, a plurality of pads formed on the substrate, at least one electronic component mounted on the substrate and having a plurality of leads connected to the pads, and the lead. a liquid first silicon filled in a space surrounded by the electronic component and the substrate; and a hardened second silicon that covers the substrate and the first silicon.
A package characterized by being composed of silicon. 2. The package according to claim 1, comprising: a frame-shaped member provided around the substrate; and a cap attached to the frame-shaped member so as to cover the substrate. 3. The package according to claim 1, wherein the second silicone is thermosetting silicone. 4. The package according to claim 1, wherein the second silicone is an ultraviolet curable silicone. 5. The package according to claim 4, wherein the first silicone is an ultraviolet curable silicone. 6 a substrate, a plurality of pads formed on the substrate, at least one electronic component having a plurality of leads connected to the pads and mounted on the substrate, and an electronic component mounted around the substrate; a frame-like member formed on the first silicon; a liquid first silicon filled into a space surrounded by the substrate and the frame-like member until at least the plurality of leads are immersed therein; and a hardened second silicon. 7. The package according to claim 6, wherein the second silicone is thermosetting silicone. 8. The package according to claim 6, wherein the second silicone is an ultraviolet curable silicone.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60-197007 | 1985-09-05 | ||
| JP19700785 | 1985-09-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62252955A true JPS62252955A (en) | 1987-11-04 |
| JPH0787231B2 JPH0787231B2 (en) | 1995-09-20 |
Family
ID=16367238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61197615A Expired - Fee Related JPH0787231B2 (en) | 1985-09-05 | 1986-08-22 | Package manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0787231B2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5762613A (en) * | 1980-10-01 | 1982-04-15 | Murata Mfg Co Ltd | Electronic parts and their production |
| JPS585350U (en) * | 1981-06-30 | 1983-01-13 | 日本電気ホームエレクトロニクス株式会社 | Resin-encapsulated semiconductor device |
| JPS60116151A (en) * | 1983-11-28 | 1985-06-22 | Matsushita Electric Works Ltd | Sealing method of electronic parts |
-
1986
- 1986-08-22 JP JP61197615A patent/JPH0787231B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5762613A (en) * | 1980-10-01 | 1982-04-15 | Murata Mfg Co Ltd | Electronic parts and their production |
| JPS585350U (en) * | 1981-06-30 | 1983-01-13 | 日本電気ホームエレクトロニクス株式会社 | Resin-encapsulated semiconductor device |
| JPS60116151A (en) * | 1983-11-28 | 1985-06-22 | Matsushita Electric Works Ltd | Sealing method of electronic parts |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0787231B2 (en) | 1995-09-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4709301A (en) | Package | |
| JP2815324B2 (en) | Chip carrier having a single encapsulant and method of forming | |
| JP4757398B2 (en) | Manufacturing method of semiconductor device | |
| JPH0846098A (en) | Equipment and method for forming direct heat conduction path | |
| TWI414027B (en) | Chip-sized package and fabrication method thereof | |
| JPH1167799A (en) | Manufacture of electronic component | |
| JP2002368028A (en) | Semiconductor package and method of manufacturing the same | |
| JP7096766B2 (en) | Manufacturing method of semiconductor device | |
| KR100823699B1 (en) | Flip chip assembly and method of manufacturing the same | |
| JP2004128286A (en) | Chip-like electronic component and manufacturing method thereof, pseudo wafer used for the manufacturing and manufacturing method thereof, and mounting structure | |
| JP2617402B2 (en) | Semiconductor device, electronic circuit device, and manufacturing method thereof | |
| KR100878408B1 (en) | Method of packaging wafer level device package | |
| JPS62252955A (en) | Package | |
| CN115172179A (en) | Chip packaging structure and preparation method | |
| CN101295655A (en) | Panel/wafer molding apparatus and method of the same | |
| KR100714186B1 (en) | Tape carrier package of thermal emission type and manufacturing method thereof | |
| JPH10135254A (en) | Semiconductor device and manufacturing method thereof | |
| JP2005322869A (en) | Manufacturing tool and chip arrangement method of wafer level package, | |
| JP3468386B2 (en) | Method for manufacturing semiconductor device | |
| JPS6244851B2 (en) | ||
| JPS606558B2 (en) | Resin packaging method for electronic components | |
| JPS62133741A (en) | Package | |
| KR100431501B1 (en) | High-power package structure for reducing thickness and manufacturing cost thereof and method for fabricating the same | |
| KR100308394B1 (en) | Semiconductor Package and Manufacturing Method_ | |
| JPS62133742A (en) | Package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |