JPS62249081A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS62249081A JPS62249081A JP61092626A JP9262686A JPS62249081A JP S62249081 A JPS62249081 A JP S62249081A JP 61092626 A JP61092626 A JP 61092626A JP 9262686 A JP9262686 A JP 9262686A JP S62249081 A JPS62249081 A JP S62249081A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- stage
- delay time
- delay
- difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 238000000034 method Methods 0.000 abstract description 12
- 230000010355 oscillation Effects 0.000 abstract description 4
- YDLQKLWVKKFPII-UHFFFAOYSA-N timiperone Chemical compound C1=CC(F)=CC=C1C(=O)CCCN1CCC(N2C(NC3=CC=CC=C32)=S)CC1 YDLQKLWVKKFPII-UHFFFAOYSA-N 0.000 abstract 1
- 229950000809 timiperone Drugs 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
- Pulse Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は遅延時間の評価ができる半導体’Ｊ槓回路に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor 'J' circuit that can evaluate delay time.
し従来の技術〕
従来、回路周辺部の遅延や測定器の測定端子間の時間ズ
レ（スキニー）を除いて、試験ゲートの遅延時間を求め
る方法として、二種類の方法が用いられてきた。第１の
方法は、段数の異なる試願ゲートの列を２つ用いてこれ
ら２つのバスの遅延時間を測定することによって試験ゲ
ートの段数の差分のゲート遅延時間を見積るスルーパス
方法であり、第２の方法は、試験ゲートでリング発掘器
を構成し、その遅延時間ｆｔ発振周期として測定するも
のである。BACKGROUND ART Conventionally, two types of methods have been used to determine the delay time of a test gate, excluding the delay in the circuit periphery and the time difference (skinny) between measurement terminals of a measuring device. The first method is a through-pass method in which the gate delay time of the difference in the number of test gate stages is estimated by measuring the delay time of these two buses using two rows of test gates with different numbers of stages. In this method, a ring excavator is configured with a test gate, and its delay time ft is measured as the oscillation period.
上述の二つの方法は、次のような欠点がある。 The above two methods have the following drawbacks.
１ず第１の方法では、試験ゲートの高速化に伴って、短
い時間間隔を測定するための高精度の測定器を必要とし
、又外部に信号源上必要とする。1. In the first method, as the speed of the test gate increases, a high-precision measuring instrument for measuring short time intervals is required, and an external signal source is also required.
また第２の方法では、各試験ゲートが、所定の振幅より
小さなままで発振（−で、見かけ上試験ゲートの遅延時
間が小さくなる場合の確認が困難である。In addition, in the second method, each test gate oscillates with an amplitude smaller than a predetermined value (-), and it is difficult to confirm that the delay time of the test gate appears to be small.
本発明の目的は、これらの欠点を解決し、精度よく遅延
時間を測定できるようにした半導体集積回路を提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to solve these drawbacks and provide a semiconductor integrated circuit that can measure delay time with high accuracy.
し問題点を解決するための手段〕
本発明の半導体集積回路の構成は、入力端子とそれぞれ
接続されそれぞれ遅延時間の異なる複数の遅延部と、こ
れら複数の遅延部の出力を切替えて１個の出力端子と接
続する出力切替回路とを有の出力端と前記入力端子との
接続を切替えて前記直列ゲートの初段に接続する入力切
替回路とをそれぞれ含み、前記各切替回路を切替えて前
記ゲートの遅廷時間金測定できるようにしたことを特徴
とする。[Means for Solving the Problems] The structure of the semiconductor integrated circuit of the present invention includes a plurality of delay sections each connected to an input terminal and each having a different delay time, and a single delay section by switching the outputs of these plurality of delay sections. and an input switching circuit that switches the connection between the output terminal and the input terminal to connect to the first stage of the series gate, and switches each switching circuit to connect the gate to the first stage of the series gate. A feature of this system is that it is possible to measure late court time and fees.
し実施例〕 次に、本発明について図面を参照して説明する。Example] Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.
本実施例は、入力端子４と接続される１１段遅延部１の
出力と２１段遅延部２の出力の一万を選択し出力端子５
へ出力する出力スイッチ３とから構成される。また、１
１段遅延部１は、入力スイッチ１０と、１１段の試験ゲ
ート１１〜２１の列とからなり、入力スイッチ１０は、
入力端子４あるいｒよ最終段の試験ゲート２１の出力の
一万全選択し、初段の試験ゲート１１と接続し、２１段
遅延部２は、入力スイッチ３０と、２１段の遅延ゲート
３１〜５１の列とからなり、段数を除いては１１段遅延
部１と同じである。これら試験ゲート１１〜２１．３１
〜５１は全て同じゲート遅延時間ＴＤの反転ゲートから
構成される。In this embodiment, the output of the 11-stage delay unit 1 and the output of the 21-stage delay unit 2 connected to the input terminal 4 are selected, and the output terminal 5
It is composed of an output switch 3 for outputting to the output terminal. Also, 1
The one-stage delay section 1 consists of an input switch 10 and a column of 11 stages of test gates 11 to 21.
The input terminal 4 or r selects all the outputs of the final stage test gate 21 and connects them to the first stage test gate 11. It consists of 51 columns and is the same as the 11-stage delay unit 1 except for the number of stages. These test gates 11-21.31
.about.51 are all composed of inverting gates having the same gate delay time TD.
次に、この回路の動作について説明する。この回路によ
るゲート遅延時間ＴＤの測定には２つの方法がある。Next, the operation of this circuit will be explained. There are two methods for measuring the gate delay time TD using this circuit.
＠１の方法はスルーパスによるもので。この時入力スイ
ッチ１０，３０ｕ入力端子４からの入力を選択している
。この状態で入力端子４と出力端子５０間の遅延時間を
、出力スイ・ソチ３を切換えて、１１段遅延部１と２１
段遅延部２についてそれぞれ測定し、その遅延時間の差
をゲート段数の差（１０）で割ることにより、１段の試
験ゲート当りの遅延時間ＴＤを求めることができる。The method @1 uses a through path. At this time, the input from the input switch 10, 30u input terminal 4 is selected. In this state, the delay time between the input terminal 4 and the output terminal 50 is changed between the output switch 3 and the 11-stage delay section 1 and 21.
By measuring each of the stage delay sections 2 and dividing the difference in delay time by the difference in the number of gate stages (10), the delay time TD per test gate in one stage can be obtained.
第２の方法は１１ング発振器によるもので、この時入力
スィッチ１０，３０１！各々最終段の試験ゲート３１．
’５１に選択している。この状態では１１段遅延部ｌと
２１段遅延部２は各々１１段、２１段の１１ング発撮器
として動作し、これら２つのリング発振器の発振周期を
、出力スイッチ３を切換えて測定し、その発振周期の差
を、ゲート段数の差の２倍で割ることにより、１段当り
の試験ゲートの遅延時間を求めることができる。The second method is by an 11-ring oscillator, when the input switch 10,301! Each final stage test gate 31.
Selected in '51. In this state, the 11-stage delay unit l and the 21-stage delay unit 2 operate as 11-stage and 21-stage 11-ring oscillators, respectively, and the oscillation periods of these two ring oscillators are measured by switching the output switch 3. By dividing the difference in the oscillation period by twice the difference in the number of gate stages, the delay time of the test gate per stage can be obtained.
以上説明したように、本発明は、試験ゲートの列ｆ ス
ルー ＊ ハスとリング発振器の二つの方法で用いるこ
とにより、リング発振器の小撮幅動作を確認でき、周期
測定による遅延時間を精度よく測定できるという効果が
ある。As explained above, the present invention can confirm the small width operation of the ring oscillator by using the row of test gates in two ways: the row f through * lotus and the ring oscillator, and accurately measure the delay time by period measurement. There is an effect that it can be done.
第１図は本発明の一実施例のブロック図である。
ｌ・・・・・・１１段遅延部、２・・・・・・２１段遅
延部、３・・・・・・串カスイッチ、４・・・・・・入
力端子、５・・・・・・出力端子、１０．３０・・・・
・・入力スイッチ、１１−・２１゜３１〜５１・・・・
・・試験ゲート。
代理人 弁理士 円 原 皆
６．７′FIG. 1 is a block diagram of one embodiment of the present invention. l... 11-stage delay section, 2... 21-stage delay section, 3... skewer switch, 4... input terminal, 5...・・Output terminal, 10.30・・・・
・・Input switch, 11-・21゜31~51・・・・
...Test gate. Agent Patent Attorney Yen Hara Min 6.7'
Claims (1)
複数の遅延部と、これら複数の遅延部の出力を切替えて
１個の出力端子と接続する出力切替回路とを有し、前記
各遅延部が、それぞれ段数の異る複数のゲートを直列接
続した直列ゲート回路と、この直列ゲート回路の出力端
と前記入力端子との接続を切替えて前記直列ゲートの初
段に接続する入力切替回路とをそれぞれ含み、前記各切
替回路を切替えて前記ゲートの遅延時間を測定できるよ
うにしたことを特徴とする半導体集積回路。It has a plurality of delay sections each connected to an input terminal and having different delay times, and an output switching circuit that switches the outputs of the plurality of delay sections and connects them to one output terminal, and each of the delay sections has a Each includes a series gate circuit in which a plurality of gates having different numbers of stages are connected in series, and an input switching circuit that switches the connection between the output terminal of the series gate circuit and the input terminal and connects it to the first stage of the series gate, and A semiconductor integrated circuit characterized in that the delay time of the gate can be measured by switching each switching circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61092626A JPS62249081A (en) | 1986-04-21 | 1986-04-21 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61092626A JPS62249081A (en) | 1986-04-21 | 1986-04-21 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62249081A true JPS62249081A (en) | 1987-10-30 |
Family
ID=14059652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61092626A Pending JPS62249081A (en) | 1986-04-21 | 1986-04-21 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62249081A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02284080A (en) * | 1988-09-02 | 1990-11-21 | Internatl Business Mach Corp <Ibm> | Integrated circuit chip and method for detecting operating speed of the same |
| JP2001266593A (en) * | 2000-03-23 | 2001-09-28 | Oki Micro Design Co Ltd | Semiconductor integrated circuit |
-
1986
- 1986-04-21 JP JP61092626A patent/JPS62249081A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02284080A (en) * | 1988-09-02 | 1990-11-21 | Internatl Business Mach Corp <Ibm> | Integrated circuit chip and method for detecting operating speed of the same |
| JP2001266593A (en) * | 2000-03-23 | 2001-09-28 | Oki Micro Design Co Ltd | Semiconductor integrated circuit |
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