JP2001266593A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IC incorporating a circuit for measuring an accurate operation time. SOLUTION: A test mode (level 'H') is specified by a mode signal MOD, analog switches (SW) 18, 19 are turned off, a SW20 is turned on, semiconductor circuits of memory cell array 14 and the like are separated, and an input node 11 and an output node 17 are connected. Therefore, a delay time of a measuring system excluding semiconductor circuits is measured. Next, the mode signal MOD is switched to a normal mode (level 'L'), the SW18, 19 are turned on, the SW20 is turned off, an operation time of a memory macro-cell 10A to which a delay time of the measuring system is added is measured. An accurate access time of the memory macro-cell 10A can be calculated by subtracting a measured result at the time of a test mode from a measured result at the time of a normal mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit (hereinafter, referred to as "IC"), and more particularly to an IC having a circuit for accurately measuring an operation time.

[0002]

2. Description of the Related Art FIG. 2 is a diagram showing a conventional memory macro cell and its test configuration. This memory macro cell 10
Has an input node 11 to which an input signal S2 such as an address signal is applied, and a decoder driver 13 is connected to the input node 11 via an address buffer 12. The decoder driver 13 decodes an address signal and drives a memory cell at a specified address.
The word line of the memory cell array 14 is connected to the decoder driver 13.

[0003] The memory cell array 14 is provided with a plurality of word lines and bit lines intersecting each other, and a memory cell is arranged at each intersection. The storage contents of the memory cells driven by the word lines of the memory cell array 14 are as follows:
The data is output to the bit line. A sense amplifier 15 that amplifies the output voltage and generates a data signal of a predetermined level is connected to the bit line. The output side of the sense amplifier 15 is connected to an output node 17 via a data buffer 16.

On the other hand, a system for measuring the access time of the memory macro cell 10 includes a measuring device 1 as a main body and an input pad 2 and an output pad 3 as connection portions for measurement. The measuring device 1 has a function of outputting a test signal S1 such as an address signal to the memory macrocell 10, a measurement signal S4 such as a data signal output from the memory macrocell 10, and a measurement signal S4 from the output of the test signal S1. It has a function to measure the time until the input of the.

The input pad 2 protects the memory macro cell 10 from overvoltage and the like, converts the test signal S 1 output from the measuring device 1 into an input signal S 2 of a level suitable for the memory macro cell 10, and converts the input signal to an input node 11. To give to. The output pad 3 protects the memory macrocell 10 from overvoltage and the like, and converts an output signal S3 output from the memory macrocell 10 into a measurement signal S4 of a level suitable for the measuring device 1.

In the test configuration shown in FIG. 2, the access time TA of the memory macro cell 10 is measured, for example, as follows. First, since it is necessary to observe the waveform, a specific test signal S that assumes the measuring device 1 from another test device is used.
1 and the test signal S1 passes through the input pad 2 and
The time delay until output as the input signal S2 is calculated by waveform observation. Similarly, the output signal S3 is output pad 3
, A time delay until output as the measurement signal S4 is calculated by waveform observation. Thus, the signals S1 to S1
The delay time T1 of S2 and S3 to S4 is measured.

Next, the memory macro cell 1
A test signal S1 for designating a specific address of 0 is output.
The operation time T2 until input as 4 is measured. From the operation time T2 measured in this way, the delay time T1
Is subtracted to calculate the access time TA.

[0008]

However, the test of the conventional memory macro cell 10 has the following problems. That is, in the measurement of the operation time T2 performed in the test configuration of the memory macro cell 10, since the measurement environment of the delay time T1 is completely different, it is not easy to faithfully reproduce the temperature, resistance, capacitance, and the like. Therefore, the delay time T1 included in the operation time T2 cannot be accurately obtained, and the access time TA
Was difficult to calculate correctly.

Further, for example, the output condition of the input pad 2 for connecting the memory macrocell 10 and the output pad 3
Are different from each other, the input pad 2 and the output pad 3 cannot be directly connected to measure the delay time T1. An object of the present invention is to solve the problem of the prior art and to provide an IC having a circuit for accurately measuring an operation time by eliminating a delay time of a measurement system.

[0010]

According to a first aspect of the present invention, an input node to which an input signal is applied and a semiconductor circuit which performs a predetermined operation based on the input signal are provided. And an output node that outputs an output signal of the semiconductor circuit.
Second and third switch means are provided.

When the normal mode is designated by a mode signal designating the normal mode or the test mode, the first switch means connects between the input node and the input side of the semiconductor circuit, and performs a test by the mode signal. When a mode is designated, the connection between the input node and the input side of the semiconductor circuit is disconnected. The second switch means connects or disconnects between the output side of the semiconductor circuit and the output node according to the mode signal in the same manner as the first switch means. The third switch means connects or disconnects the input node and the output node in reverse to the first switch means according to the mode signal.

According to the first aspect, since the IC is configured as described above, the following operation is performed. When the test mode is designated by the mode signal, the semiconductor circuit is separated from the input node and the output node by the first and second switch means, and the input node and the output node are connected by the third switch means. You. This allows I
The delay time of the measurement system excluding the semiconductor circuit in C can be measured.

On the other hand, when the normal mode is designated by the mode signal, the third switch is turned off, and the semiconductor circuit is connected between the input node and the output node by the first and second switch. Thereby, the operation time of the IC to which the delay time of the measurement system is added can be measured.
Therefore, the accurate operation time of the IC can be calculated by subtracting the measurement result in the test mode from the measurement result in the normal mode.

According to a second aspect of the present invention, there is provided an IC similar to the first aspect, wherein the first and second switch means similar to the first aspect are different from each other when a test mode is designated by a mode signal. Short-circuit means for short-circuiting between the input node and the output node through a short-circuit path selected by a selection signal among the above short-circuit paths.

According to the second invention, the following operation is performed. When the test mode is specified by the mode signal, the first
The semiconductor circuit is separated from the input node and the output node by the second switch means. Further, the input node and the output node are short-circuited by the short-circuit means through the path selected by the selection signal. Thus, the delay times of the plurality of short-circuit paths can be measured, and the delay time of the measurement system when the number of the short-circuit paths is 0 can be calculated from the measurement results.

On the other hand, when the normal mode is designated by the mode signal, the short circuit is cut off, and the semiconductor circuit is connected between the input node and the output node by the first and second switch means. Thereby, the operation time of the IC to which the delay time of the measurement system is added can be measured. Therefore, the accurate operation time of the IC can be calculated by subtracting the delay time calculated from the test mode result from the measurement result in the normal mode.

A third aspect of the present invention is the first or second aspect of the present invention.
The semiconductor circuit in C is constituted by a memory macro cell which supplies an address signal as an input signal and outputs data stored in an area designated by the address signal as an output signal.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a diagram showing a memory macro cell and a test configuration thereof according to a first embodiment of the present invention. Elements common to those shown in FIG. Common symbols are assigned. This memory macro cell 10A
Like FIG. 2, it has an input node 11 to which an input signal S2 such as an address signal is applied. The input node 11
The address of a semiconductor circuit (for example, an address buffer 12, a decoder driver 13, a memory cell array 14, a sense amplifier 15, and a data buffer 15) via first switch means (for example, an analog switch, hereinafter, referred to as "SW") 18 It is connected to the input side of the buffer 12. A decoder driver 13 is connected to the output side of the address buffer 12. Decoder driver 1
Numeral 3 is for decoding the address signal and driving the memory cell at the designated address. The word line of the memory cell array 14 is connected to the decoder driver 13.

The memory cell array 14 is provided with a plurality of word lines and bit lines crossing each other, and a memory cell for storing data is arranged at each of these crossing points.
The stored contents of the memory cells driven by the word lines of the memory cell array 14 are output to bit lines. The bit line is connected to a sense amplifier 15 that amplifies the voltage output to the bit line and generates a data signal of a predetermined level. The output side of the sense amplifier 15
It is connected to the input side of the data buffer 16.

The output side of the data buffer 16 is connected to the output node 1 via second switch means (for example, SW) 19.
7 is connected. Further, a third switch means (for example, SW) 2 is provided between the input node 11 and the output node 17.
0. SW18-2
0 is turned on / off by a mode signal MOD applied to the signal node 21. That is,
When a test mode (for example, level “H”) is designated by the mode signal MOD, the SWs 18 and 19 are set to an on state, and the SW 20 is set to an off state.
In addition, the normal mode (for example,
When the level “L” is designated, the switches 18 and 19 are set to the off state and the switch 20 is set to the on state.

On the other hand, the system for measuring the access time of the memory macro cell 10A comprises a measuring device 1 as a main body and an input pad 2 and an output pad 3 for connection to a circuit to be measured, as in FIG. I have. The measuring device 1 generates a test signal S1 such as an address signal for the memory macrocell 10.
And a function of inputting a measurement signal S4 such as a data signal output from the memory macro cell 10 and measuring the time from the output of the test signal S1 to the input of the measurement signal S4.

The input pad 2 is connected to the memory macro cell 10A
Is protected from overvoltage or the like, and the test signal S1 output from the measuring device 1 is converted into an input signal S2 of a level suitable for the memory macro cell 10A, and the input node 11 is
To give to. The output pad 3 protects the memory macro cell 10A from overvoltage and the like, and outputs the output signal S3 output from the memory macro cell 10A.
This is for converting into a measurement signal S4 of a level suitable for the measurement device 1.

In the test configuration as shown in FIG. 1, the access time TA of the memory macro cell 10A is measured as follows. First, the test mode is designated by setting the mode signal MOD to be applied to the signal node 21 to "H". As a result, the SWs 18 and 19 are turned off, and the semiconductor circuits such as the memory cell array 14 are disconnected from the input node 11 and the output node 17. Further, the SW 20 is turned on, and the connection between the input node 11 and the output node 17 is connected. In this state, the specific test signal S1
And a delay time TD until the test signal S1 passes through the input pad 2 and the output pad 3 and returns to the measuring device 1 as the measurement signal S4 is measured.

Next, the mode signal MOD is set to "L",
Specify normal mode. As a result, the SWs 18 and 19 are turned on, and the semiconductor circuits such as the memory cell array 14 are connected to the input node 11 and the output node 17. Further, the SW 20 is turned off, and the connection between the input node 11 and the output node 17 is disconnected. In this state, a test signal S1 for designating a specific address of the memory macro cell 10A is output from the measuring device 1, and the data of the memory macro cell 10A is used as a measuring signal S4.
The operation time TR until the input is input to the device is measured. The access time TA is calculated by subtracting the delay time TD from the operation time TR thus measured.

As described above, the memory macro cell 10A of the first embodiment has the SWs 18 to 20 for internally connecting the input node 11 and the output node 17 based on the designation of the mode signal MOD. are doing. Thereby, there is an advantage that the delay time TD of the measurement system can be accurately measured, and the accurate access time TA of the memory macro cell 10A itself can be calculated.

(Second Embodiment) FIG. 3 shows a second embodiment of the present invention.
FIG. 2 is a diagram showing a memory macro cell and a test configuration thereof according to the first embodiment, and components common to those in FIG. 1 are denoted by common reference numerals. The memory macro cell 10B includes short-circuit means (for example, switching units 22a and 22b, and a short circuit) that can short-circuit between the input node 11 and the output node 17 of the memory macro cell 10A in FIG. Wirings 23a, 23b, 23c) are provided.

That is, the switching section 22 is connected to the output side of the SW 20.
a is connected. The switching unit 22a connects the output side of the SW 20 to one of the short-circuit wires 23a, 23b, and 23c.
One to connect. The lengths of the short-circuit wires 23b and 23c are respectively twice and three times the length of the short-circuit wires 23a, and the other ends of these short-circuit wires 23a to 23c are connected to the output node 17 via the switching unit 22b. Have been.
The switching units 22a and 22b are commonly controlled by a selection signal SEL applied to the signal node 24.
Other configurations are the same as those in FIG.

In the test configuration shown in FIG. 3, the access time TA of the memory macro cell 10B is measured as follows. First, the test mode is designated by setting the mode signal MOD to be applied to the signal node 21 to "H". As a result, the SWs 18 and 19 are turned off, and the semiconductor circuits such as the memory cell array 14 are disconnected from the input node 11 and the output node 17. Further, the SW 20 is turned on. Further, the switching units 22a and 22b are switched to the short-circuit line 23a by the selection signal SEL supplied to the signal node 24. Thereby, the input node 11 and the output node 17
Are connected via a short-circuit wire 23a. In this state, a specific test signal S1 is output from the measuring apparatus 1, and the test signal S1 passes through the input pad 2, the short-circuit wiring 23a, and the output pad 3, and is output as the measuring signal S4.
The delay time TDa before returning to is measured.

Similarly, the short-circuit wires 23b and 23c are sequentially selected by the selection signal SEL, and these short-circuit wires 23b and 23c are selected.
The delay times TDb and TDc passing through b and 23c are measured. The delay times TDa to TDc correspond to the short-circuit wires 23a to 23
c, the length of the short-circuit wire is set to 0 based on these delay times TDa to TDc.
In this case, the delay time TD0 is calculated.

Next, the mode signal MOD is set to "L",
Specify normal mode. As a result, the SWs 18 and 19 are turned on, and the semiconductor circuits such as the memory cell array 14 are connected to the input node 11 and the output node 17. Further, the SW 20 is turned off, and the connection between the input node 11 and the output node 17 is disconnected. In this state, a test signal S1 for designating a specific address of the memory macro cell 10B is output from the measuring device 1, and the data of the memory macro cell 10B is used as a measuring signal S4.
The operation time TR until the input is input to the device is measured. The access time TA is calculated by subtracting the delay time TD0 from the operation time TR thus measured.

As described above, in the memory macro cell 10B of the second embodiment, the SWs 18 to 20 for internally connecting the input node 11 and the output node 17 are provided based on the designation of the mode signal MOD. Have. Further, based on the selection signal SEL, the switching units 22a, 22b, which can select three short-circuit wires 23a to 23c having different lengths.
22b. Thereby, the memory macro cell 1
The delay time TD0 of only the measurement system can be accurately calculated without being affected by the length of the short-circuit line in 0B, and the access time TA of the memory macro cell 10B itself can be calculated more accurately. There is an advantage.

The present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (a) and (b). (A) As an IC to be measured, a memory macro cell 10
Although A and 10B have been described as examples, the present invention can be similarly applied to an IC such as a complicated logic circuit. (B) The memory macro cell 10B of FIG. 3 is provided with the short-circuit wires 23a, 23b, and 23c having a length of 1: 2: 3, but the number of short-circuit wires may be plural. Also, the length ratio need not be an integer ratio, but may be any known value.

[0033]

As described above in detail, according to the first and third aspects of the present invention, the first to third modes for directly connecting the input node and the output node by separating the semiconductor circuit in the test mode.
Third switch means is provided. Thereby, the delay time of the measurement system can be measured. Therefore, by subtracting the measurement result in the test mode from the measurement result in the normal mode, an accurate operation time of the IC such as the memory macro cell can be calculated.

According to the second and third aspects, the first and second switch means for disconnecting the semiconductor circuit in the test mode, and the short-circuit means for short-circuiting between the input node and the output node through a plurality of different short-circuit paths. It has. This allows I
The delay time of only the measurement system can be measured without being affected by the length of the short circuit path in C. Therefore, by subtracting the measurement result in the test mode from the measurement result in the normal mode, the operation time of the IC can be calculated more accurately.

[Brief description of the drawings]

FIG. 1 is a diagram showing a memory macro cell and a test configuration thereof according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a conventional memory macro cell and its test configuration.

FIG. 3 is a diagram showing a memory macro cell and a test configuration thereof according to a second embodiment of the present invention.

[Explanation of symbols]

 10A, 10B Memory macro cell 11 Input node 12-16 Semiconductor circuit 17 Output node 18-20 SW (analog switch) 21, 24 Signal node 22a, 22b Switching unit 23a-23c Short circuit wiring

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/822 F-term (Reference) 2G032 AA07 AD06 AK12 AK14 4M106 AB07 AC08 CA09 CA57 DJ11 DJ21 5F038 CD09 DF05 DF17 DT02 DT16 EZ20 5L106 DD08 DD11 DD32 GG05 9A001 BB03 BB05 JJ49 KK54 LL05

Claims (3)

[Claims] An input node to which an input signal is applied; a semiconductor circuit performing a predetermined operation based on the input signal;
An output node for outputting an output signal of the semiconductor circuit, wherein when a normal mode is designated by a mode signal designating a normal mode or a test mode, the input node and the input side of the semiconductor circuit are connected to each other. First switch means for disconnecting between the input node and the input side of the semiconductor circuit when a test mode is designated by the mode signal; and an output side of the semiconductor circuit according to the mode signal. A second switch for connecting or disconnecting between the output node in the same manner as the first switch, and a first switch for connecting between the input node and the output node according to the mode signal. And a third switch for connecting or disconnecting the semiconductor integrated circuit. 2. An input node to which an input signal is applied, a semiconductor circuit performing a predetermined operation based on the input signal,
An output node for outputting an output signal of the semiconductor circuit, wherein when a normal mode is designated by a mode signal designating a normal mode or a test mode, the input node and the input side of the semiconductor circuit are connected to each other. First switch means for disconnecting between the input node and the input side of the semiconductor circuit when a test mode is designated by the mode signal; and an output side of the semiconductor circuit according to the mode signal. Second switch means for connecting or disconnecting the output node in the same manner as the first switch means, and selecting from among two or more different short-circuit paths when a test mode is designated by the mode signal Short-circuit means for short-circuiting between the input node and the output node through a short-circuit path selected by a signal; And a semiconductor integrated circuit. 3. The semiconductor circuit according to claim 1, wherein the semiconductor circuit is constituted by a memory macro cell which supplies an address signal as the input signal and outputs data stored in an area designated by the address signal as the output signal. 3. The semiconductor integrated circuit according to claim 1, wherein: