JPS6224774A - Image scanner device - Google Patents

Image scanner device

Info

Publication number
JPS6224774A
JPS6224774A JP60164538A JP16453885A JPS6224774A JP S6224774 A JPS6224774 A JP S6224774A JP 60164538 A JP60164538 A JP 60164538A JP 16453885 A JP16453885 A JP 16453885A JP S6224774 A JPS6224774 A JP S6224774A
Authority
JP
Japan
Prior art keywords
output
variable resistor
scanner device
density
image sensor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60164538A
Other languages
Japanese (ja)
Inventor
Masahito Tanimura
正仁 谷村
Yoshitaka Furui
義隆 古井
Makoto Murata
誠 村田
Kiyoshi Kimura
潔 木村
Hiroshi Sakai
境 博
Takeshi Yamamoto
剛 山本
Tomoshige Ishimura
石村 朝茂
Yuji Shimazaki
島崎 雄二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panafacom Ltd
Original Assignee
Panafacom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panafacom Ltd filed Critical Panafacom Ltd
Priority to JP60164538A priority Critical patent/JPS6224774A/en
Publication of JPS6224774A publication Critical patent/JPS6224774A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make an image scanner device handling the presence/absence of white/black levels only without expression of an intermediate density express a pseudo multi-value with an inexpensive means by adopting the constitution that a noise signal is applied to an analog signal output from an optical read section and the result is compared with a threshold voltage. CONSTITUTION:An analog signal representing the density of a graphic received by a comparator 5 is the sum between a voltage division of an output of a white noise generator 7 by a variable resistor 8 and an output of a CCD image sensor 3 by an adder 9 and the sum changes irregularly timewise with respect to the substantial output of the CCD image sensor 3. In comparing the output with a threshold voltage decided by a variable resistor 6, since the probability of the output with logical '1' of the comparator 5 is increased as the output of the adder 9 increases, that is, the output of the CCD image sensor 3 increases, the frequency of output being logical '1' is increased according to the density of the inputted graphic and the intermediate tone is expressed in a pseudo way. In this case, the variable resistor 6 adjusts the density and the variable resistor 8 adjusts the contrast.

Description

【発明の詳細な説明】 〔概要〕 光学読取部からのアナログ信号出力にノイズ信号を加え
た上で、闇値電圧と比較する構成のイメージスキャナ装
置が示されている。
DETAILED DESCRIPTION OF THE INVENTION [Summary] An image scanner device is shown in which a noise signal is added to an analog signal output from an optical reading section and then compared with a dark value voltage.

〔産業上の利用分野〕[Industrial application field]

本発明は、イメージスキャナ装置に関する。 The present invention relates to an image scanner device.

〔従来の技術〕[Conventional technology]

従来、イメージスキャナ装置で写真などの多値図形を入
力する場合、図形をアナログ信号にて読み取り、これを
A/Dコンバータでデジタル信号に変換し、これを計算
機に読み込んでいた。
Conventionally, when inputting a multivalued figure such as a photograph using an image scanner device, the figure was read as an analog signal, converted to a digital signal by an A/D converter, and then read into a computer.

第2図は、従来のイメージスキャナ装置の構成例を示す
図である。
FIG. 2 is a diagram showing an example of the configuration of a conventional image scanner device.

第2図において、1はイメージスキャナ装置の制御を司
る制御部、2はタイミング発生器、3はCCDイメージ
センサ、4はイメージデータ信号とホスト計算機との同
期を取るための同期信号先主 声器、5はイメージデータ信号を出力するコンパレータ
、6は基準電圧を分圧する可変抵抗器である。
In FIG. 2, 1 is a control unit that controls the image scanner device, 2 is a timing generator, 3 is a CCD image sensor, and 4 is a synchronization signal destination main voice unit for synchronizing the image data signal with the host computer. , 5 is a comparator that outputs an image data signal, and 6 is a variable resistor that divides the reference voltage.

第2図の動作について説明する。1の制御部がホスト計
算機から読取指令を受けると、1の制御部は2のタイミ
ング発生器にタイミング発生を、3のCCDイメージセ
ンサに読取開始を、4の同期信号発生器にホスト計算機
に対する同期信号の発生を指示する。これにより2のタ
イミング発生器が発生するタイミングに従い、3のCC
Dイメージセンサは読取動作を、4の同期信号発生器は
同期信号を発生する。3のCCDイメージセンサの出力
は5のコンパレータにより6の可変抵抗器で定まる闇値
電圧と比較され、闇値電圧より大きい場合は“1″を、
小さい場合は“0”を出力する。
The operation shown in FIG. 2 will be explained. When the control unit 1 receives a reading command from the host computer, the control unit 1 instructs the timing generator 2 to generate timing, the CCD image sensor 3 to start reading, and the synchronization signal generator 4 to synchronize with the host computer. Instructs the generation of a signal. As a result, according to the timing generated by the timing generator 2, the CC of 3
The image sensor D generates a reading operation, and the synchronization signal generator No. 4 generates a synchronization signal. The output of the CCD image sensor 3 is compared with the dark value voltage determined by the variable resistor 6 by the comparator 5, and if it is higher than the dark value voltage, it is set as "1".
If it is smaller, "0" is output.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のようにして読み込んだ図形データはメモリの使用
量を減らすために、またプリンタなどの出力装置が2値
出力以外不可能であるために、多くの場合多値から2値
の変換を行ないデータをメモリに蓄積していた。この処
理において、図形データは2値に変換する前は、一旦多
値の図形データが読み込まれるため一時的に多くのメモ
リを必要とし、そのために大容量のメモリが必要となる
という問題があった。
In order to reduce the amount of memory used, and because output devices such as printers are only capable of outputting binary values, the graphic data read in the above manner is often converted from multivalued data to binary data. was stored in memory. In this process, before the graphic data is converted into binary data, the multi-valued graphic data is read in, which temporarily requires a large amount of memory, which creates a problem in that a large amount of memory is required. .

〔問題点を解決するための手段〕[Means for solving problems]

銅1図は、本発明によるイメージスキャナ装置の原理構
成図であり、図中、20は光学読取部、21はノイズ発
生部、22は加算部、23は闇値電圧発生部、24はコ
ンパレータである。
Figure 1 shows the principle configuration of an image scanner device according to the present invention. In the figure, 20 is an optical reading section, 21 is a noise generation section, 22 is an addition section, 23 is a dark value voltage generation section, and 24 is a comparator. be.

闇値電圧と比較される光学読取部20からのアナログ信
号出力は、ノイズ発生部21からのノイズが加算される
ため、時間の経過とともに不規則に増減される。コンパ
レータ24は、加算部22を経由して不規則化されたア
ナログ信号出力と閾値電圧発生部23からの闇値とを比
較することになる。
The analog signal output from the optical reading section 20 that is compared with the dark value voltage is irregularly increased or decreased over time because noise from the noise generating section 21 is added thereto. The comparator 24 compares the analog signal output irregularized via the adder 22 and the dark value from the threshold voltage generator 23 .

ここで、コンパレータ24の出力が“1”となる確率は
、光学読取部20の出力の大きさに従い、大きくなるた
め、2値のイメージスキャナ装置を擬似的な多値を取り
扱い可能な装置とすることができる。
Here, since the probability that the output of the comparator 24 becomes "1" increases according to the magnitude of the output of the optical reading section 20, the binary image scanner device is used as a device that can handle pseudo-multivalued data. be able to.

〔作用〕[Effect]

上記したように、コンパレータ24の出力が“1”とな
る確率は、加算部22の出力が大きくなる、すなわち光
学読取部20の出力の大きさに従い大きくなるため、入
力した図形の濃度に従い出力は“1”となる頻度が増え
、擬似的に中間調が表現できる。
As mentioned above, the probability that the output of the comparator 24 becomes "1" increases as the output of the adding section 22 increases, that is, as the output of the optical reading section 20 increases, so the output increases according to the density of the input figure. The frequency of "1" increases, and pseudo-halftones can be expressed.

本発明によれば、 イメージスキャナ装置は図形データを蓄えるバッファメ
モリや、高価な高速のA/Dコンバータを一切必要とす
ることなく多値の図形を2値に変換でき、さらにホスト
計算機のメモリの量、処理の量、ホスト計算機に対する
データ転送の量を大幅に削減することが可能となる。さ
らに、濃度に関しての重み付けも簡単に行え、CODの
特性や人間の好み、プリンタやディスプレイの特性など
の補正が容易となる。また、数種類の重みをユーザもし
くは計算機からの指示で容易に切り換えることもでき、
目的に合った重み付けが可能となる。
According to the present invention, an image scanner device can convert a multivalued figure into a binary figure without any need for a buffer memory for storing figure data or an expensive high-speed A/D converter, and furthermore, it is possible to convert a multilevel figure into a binary figure without requiring any buffer memory for storing figure data or an expensive high-speed A/D converter. It becomes possible to significantly reduce the amount of processing, the amount of data transferred to the host computer. Furthermore, weighting with respect to density can be easily performed, making it easy to correct COD characteristics, human preference, printer and display characteristics, etc. In addition, several types of weights can be easily switched by instructions from the user or the computer.
It becomes possible to assign weights that suit the purpose.

〔実施例〕〔Example〕

第3図は、本発明の第1の実施例の構成図である。第3
図において、上記した第2図と同一番号のものは同一の
もの、7はFMの復調回路によるホワイトノイズジェネ
レータ、8はホワイトノイズジェネレータの出力を分圧
する可変抵抗器、9は加算器である。5のコンパレータ
が受は取る図形の濃度を示すアナログ信号は、7のホワ
イトノイズジェネレータの出力を8の可変抵抗器で分圧
したものと、3のCCDイメージセンサの出力とを9の
加算器により加算した和となり、これは3のCCDイメ
ージセンサ本来の出力に対して、時間に関して不規則に
増減する。しかし、この出力を6の可変抵抗器で定まる
闇値電圧と比較する場合、5のコンパレータの出力が“
1”となる確率ば9の加算器の出力が大きくなる、すな
わち3のCCDイメージセンサの出力が大きさに従い大
きくなるため、入力した図形の濃度に従い出力は“1”
となる頻度が増え、擬似的に中間調が表現できる。なお
この例では、6の可変抵抗器により濃度の調節が、8の
可変抵抗器によりコントラストの調節が行える。
FIG. 3 is a block diagram of the first embodiment of the present invention. Third
In the figure, the same numbers as those in FIG. 2 described above are the same, 7 is a white noise generator using an FM demodulation circuit, 8 is a variable resistor that divides the output of the white noise generator, and 9 is an adder. The analog signal indicating the density of the figure received by the comparator 5 is obtained by dividing the output of the white noise generator 7 with the variable resistor 8 and the output of the CCD image sensor 3 using the adder 9. This is the sum of the sums, which increases or decreases irregularly over time with respect to the original output of the CCD image sensor 3. However, when comparing this output with the dark value voltage determined by variable resistor 6, the output of comparator 5 is “
If the output of the adder 9 increases, the output of the CCD image sensor 3 increases as the size increases, so the output becomes ``1'' according to the density of the input figure.
The frequency of this increases, and it is possible to express halftones in a pseudo manner. In this example, the density can be adjusted using the 6 variable resistors, and the contrast can be adjusted using the 8 variable resistors.

第4図は、本発明の第2の実施例の構成図である。第4
図において、上記した第2図、第3図と同一番号のもの
は同一のもの、10はカウンタ、11はROM、12は
D/Aコンバータ、13はランチである。
FIG. 4 is a block diagram of a second embodiment of the present invention. Fourth
In the figure, the same numbers as in FIGS. 2 and 3 above are the same, 10 is a counter, 11 is a ROM, 12 is a D/A converter, and 13 is a launch.

この場合、1の制御部がホスト計算機がら読取動作指令
を受け、これによりまず4の同期信号発生器が9のカウ
ンタに初期値をセットし、読取動作を開始する。10の
カウンタは2のタイミング発生器の出力に従いカウント
を行い、その出力を11のROMのアドレスに出力する
。そして11のROMはそのアドレスに対応するデータ
を読み出L、12のD/Aコンバータに出力する。この
出力は3のCCDイメージセンサの出力と9の加算器に
より加算され、3のCCDイメージセンサ本来の出力に
対して、時間に関して増減を繰り返す。この場合も第3
図のときと同様、この出力を5のコンパレータのもう一
方の入力の基準電圧と比較する場合、5のコンパレータ
の出力が“1″となる確率は9の加算器の出力が大きく
なる、すなわち3のCCDイメージセンサの出力の大き
さに従い大きくなるため、入力した図形の濃度に従い出
力は“1”となる頻度が増え、擬似的に中間調が表現で
きる。4の同期信号発生器は10のカウンタに3のCC
Dイメージセンサの一回の水平走査が終わるごとに前回
の水平走査時にセットした値とは異なる値をセットし、
これは一定周期で以て元の値を取るように成っており、
11のROMのデータに従い水平垂直方向に、すなわち
2次元方向に、規則的なデータを持つようになっている
。また11のROMには、乱数データや2次元的に大小
を繰り返すデータ、大きな値開にもしくは小さな値開に
偏りがあるデータ等が書き込まれており、これはホスト
計算機より任意の値がセントできる13のラッチの出力
により選択されるため、ホスト計算機より簡単に濃淡に
関しての重みが変更できる。
In this case, the control unit 1 receives a read operation command from the host computer, and as a result, the synchronization signal generator 4 first sets an initial value in the counter 9 and starts the read operation. The counter 10 counts according to the output of the timing generator 2, and outputs the output to the address of the ROM 11. Then, the ROM 11 reads out the data corresponding to the address and outputs it to the D/A converter 12. This output is added to the output of the CCD image sensor No. 3 by an adder No. 9, and increases and decreases over time with respect to the original output of the CCD image sensor No. 3. In this case as well, the third
As in the case of the figure, when this output is compared with the reference voltage of the other input of the comparator 5, the probability that the output of the comparator 5 becomes "1" is that the output of the adder 9 becomes larger, that is, 3 Since the output of the CCD image sensor increases in accordance with the magnitude of the output, the output becomes "1" more frequently in accordance with the density of the input figure, and a pseudo halftone can be expressed. 4 sync signal generators 10 counters and 3 CCs
Each time one horizontal scan of the D image sensor is completed, a value different from the value set during the previous horizontal scan is set,
This is designed to take the original value at regular intervals,
It has regular data in the horizontal and vertical directions, that is, in the two-dimensional direction, according to the data in the ROM No. 11. In addition, random number data, data that repeats large and small values in two dimensions, data that is biased toward large values or small values are written in the ROM of 11, and any value can be sent from the host computer. Since the selection is made based on the output of the latch No. 13, the weights regarding shading can be easily changed by the host computer.

〔発明の効果〕 本発明によれば、中間濃度の表現のできない、白黒の有
無のみ取り扱うイメージスキャナ装置を、安価な手段に
より、擬似的な多値を表現可能な装置にすることができ
、その実用上の効果は大きいものがある。
[Effects of the Invention] According to the present invention, an image scanner device that cannot express intermediate densities and handles only the presence or absence of black and white can be made into a device that can express pseudo multi-values by inexpensive means. The practical effects are significant.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理構成図、 第2図は従来のイメージスキャナ装置の構成例を示す図
、 第3図は本発明の第1の実施例の構成図、第4図は本発
明の第2の実施例の構成図である。 図中、1は制御部、2はタイミング発生器、3はCCD
イメージセンサ、4は同期信号発生器、5はコンパレー
タ、6は可変抵抗器、7はホワイトノイズジェネレータ
、8は可変抵抗器、9は加算器、10はカウンタ、11
はROM、12はD/Aコンバータ、13はラッチであ
る。 本発明が東理都′図 第1侶 4よ木のΔX−ジλキャナ裟’X 、?献JJ’ll第
2コ 本1発明の第1の賀旌イ列/)填さζ7第3Σ
FIG. 1 is a diagram showing the principle configuration of the present invention. FIG. 2 is a diagram showing an example of the configuration of a conventional image scanner device. FIG. 3 is a diagram showing the configuration of the first embodiment of the present invention. FIG. 2 is a configuration diagram of a second embodiment. In the figure, 1 is a control unit, 2 is a timing generator, and 3 is a CCD.
Image sensor, 4 is a synchronizing signal generator, 5 is a comparator, 6 is a variable resistor, 7 is a white noise generator, 8 is a variable resistor, 9 is an adder, 10 is a counter, 11
is a ROM, 12 is a D/A converter, and 13 is a latch. Is the present invention the ΔX-diλ cana'X of the tree in the first part of Torito's figure 4? Presentation JJ'll 2nd Copy Book 1 Invention's 1st Kageki I/) Filled ζ7 3rd Σ

Claims (4)

【特許請求の範囲】[Claims] (1)図形を読み取りその濃淡に従ったアナログ信号を
出力する光学読取手段(20)と、 ノイズ発生手段(21)と、 上記光学読取手段(20)の出力と、上記ノイズ発生手
段(21)の出力を加算する加算手段(22)と、 閾値電圧発生手段(23)と、 上記加算手段(22)の出力を上記閾値電圧発生手段(
23)の出力と比較し、“1”、“0”の信号に変換し
て出力するコンパレータ(24)を具備することを特徴
とするイメージスキャナ装置。
(1) Optical reading means (20) that reads a figure and outputs an analog signal according to its shading; Noise generating means (21); Output of the optical reading means (20); and Noise generating means (21) an adding means (22) for adding the outputs of the above-mentioned adding means (22); a threshold voltage generating means (23) for adding the outputs of the above-mentioned adding means (22);
An image scanner device characterized by comprising a comparator (24) that compares the output of 23) and converts the signal into a "1" or "0" signal and outputs the signal.
(2)上記ノイズ発生手段(21)は、ホワイトノイズ
発生器(7)であることを特徴とする特許請求の範囲第
(1)項記載のイメージスキャナ装置。
(2) The image scanner device according to claim (1), wherein the noise generating means (21) is a white noise generator (7).
(3)上記ノイズ発生手段(21)はカウンタ(10)
と、該カウンタ(10)の出力をアドレスとして入力す
るメモリ(11)と、該メモリ(11)の出力を入力と
するD/Aコンバータ(12)を含んで構成されること
を特徴とする特許請求の範囲第(1)項記載のイメージ
スキャナ装置。
(3) The noise generating means (21) is a counter (10)
, a memory (11) that inputs the output of the counter (10) as an address, and a D/A converter (12) that inputs the output of the memory (11). An image scanner device according to claim (1).
(4)上記メモリ(11)は、上記カウンタ(10)の
出力信号より多いアドレス信号線を有するとともに、上
記ノイズ発生手段(21)は、該アドレス信号線の一部
を任意の値に固定するアドレス固定手段(13)を具備
することを特徴とする特許請求の範囲第(3)項記載の
イメージスキャナ装置。
(4) The memory (11) has more address signal lines than the output signals of the counter (10), and the noise generating means (21) fixes a part of the address signal lines to an arbitrary value. An image scanner device according to claim 3, characterized in that it comprises address fixing means (13).
JP60164538A 1985-07-25 1985-07-25 Image scanner device Pending JPS6224774A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60164538A JPS6224774A (en) 1985-07-25 1985-07-25 Image scanner device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60164538A JPS6224774A (en) 1985-07-25 1985-07-25 Image scanner device

Publications (1)

Publication Number Publication Date
JPS6224774A true JPS6224774A (en) 1987-02-02

Family

ID=15795060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60164538A Pending JPS6224774A (en) 1985-07-25 1985-07-25 Image scanner device

Country Status (1)

Country Link
JP (1) JPS6224774A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04373258A (en) * 1991-06-21 1992-12-25 Shinko Electric Co Ltd Binarizing circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052166A (en) * 1983-09-01 1985-03-25 Matsushita Electric Ind Co Ltd Binary-coding display method of picture signal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052166A (en) * 1983-09-01 1985-03-25 Matsushita Electric Ind Co Ltd Binary-coding display method of picture signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04373258A (en) * 1991-06-21 1992-12-25 Shinko Electric Co Ltd Binarizing circuit

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