JPH08317213A - Image processor - Google Patents

Abstract

PURPOSE: To provide an image processor which can change the gradation property in the same hardware constitution. CONSTITUTION: This image processor is provided with a halftone processing part 5 which applies the halftone processing to the digital image data having the number of bits accordant with the gradation number by an error propagation method, a binarization part 6 which binarizes the pixel data undergone the halftone processing based on the threshold data having the number of bits accordant with the gradation number, a RAM 7a which stores the error data and the threshold data used at the parts 5 and 6 respectively, and a gradation property control part 8 which controls the number of bits of both pixel and error data processed at the part 5 and the threshold data given to the part 6 in order to attain the variable control of the gradation property.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for carrying out halftone (halftone) processing using an error diffusion method in a facsimile machine or the like.

[0002]

2. Description of the Related Art As a conventional image processing apparatus of this type, for example, in Japanese Patent Laid-Open No. 4-150573, a correction density level of a pixel to be read is considered in consideration of an error of a plurality of pixels located around the pixel to be read. (Error diffusion method), and in the image processing apparatus that determines the black and white of the pixel to be read based on this corrected density level, the error value of the heavy weight assigned to the error of each surrounding pixel is negative. In this case, there is disclosed a device provided with a switching means for changing the weight or stopping the addition of the error itself.

[0003]

However, such a conventional image processing apparatus has only one kind of gradation, and if it is desired to have another gradation, different hardware is used. However, it was not possible to use the same device to provide a wide range of gradation and differentiate it from other devices.

Further, in the prior art, gradation is realized by constructing hardware corresponding thereto, and weighting of an error matrix and improvement of thresholds are carried out in order to enhance halftone processing capability in the same circuit. However, since the quality of the image is almost determined by the gradation, there is a limit to the improvement of the image quality in the low gradation.

Further, in the prior art, the storage area of the correction data (error data) on the memory is constant. For example, the effective read width is B4 size, and the correction data is stored in the memory area not used when reading A4 size. I didn't save the file, but I couldn't use the memory effectively.

Therefore, the present invention has been made in order to solve such a problem, and an object of the present invention is to provide an image processing apparatus capable of changing gradation with the same hardware configuration.

It is another object of the present invention to provide an image processing apparatus which can bring out high gradation with a hardware configuration that is smaller than the hardware corresponding to the gradation.

Further, it is another object of the present invention to provide an image processing apparatus capable of performing image processing of higher gradation with the current configuration by effectively utilizing an empty memory generated when reading a document having a size smaller than the effective reading width. It is a thing.

[0009]

According to a first aspect of the present invention, there is provided a halftone processing section for performing halftone processing on digital image data having a bit number corresponding to the number of gradations by using an error diffusion method. A binarization unit that binarizes the halftone-processed pixel data using threshold data of the number of bits corresponding to the number of gradations, and error data used by the halftone processing unit and the binarization unit. By controlling the memory unit that stores the threshold data to be used, the pixel data and error data processed by the halftone processing unit, and the number of bits of the threshold data provided to the binarization unit, the gradation can be varied. And a gradation control unit for controlling.

According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the gradation control unit deletes the lower bits of the pixel data, the error data, and the threshold data, so that the gradation is reduced. The number is changed.

According to a third aspect of the present invention, in the image processing apparatus according to the first aspect, there is provided a processing clock speed changing unit for changing a processing clock for performing image processing to a high gradation processing clock having a frequency that is a multiple of the normal frequency. , The gradation control unit,
At the time of the high gradation processing clock, the pixel data and the error data are each divided into a plurality of parts, and each of them is processed by one clock of the high gradation processing clock, thereby performing high gradation halftone processing. .

According to a fourth aspect of the present invention, in the image processing apparatus according to the first aspect, in the case of image data obtained by reading a document smaller than an effective reading width, the gradation control section is The halftone processing with high gradation is performed by increasing the number of bits of the error data and the threshold data by utilizing the empty area generated in the memory section.

[0013]

According to the first aspect of the invention, the gradation property can be variably controlled by controlling the number of bits of the pixel data, the error data and the threshold value data by the gradation property control unit. It is possible to change the setting of the number of gradations with the hardware configuration of, and it is possible to give a wide range of gradation with the same device.

According to the second aspect of the present invention, the gradation number can be lowered by deleting the lower bits of the pixel data, the error data and the threshold data by the gradation control section. When handling an image that does not require tones, the speed can be increased by reducing the number of bits.

According to the third aspect of the present invention, the processing clock is changed to, for example, a high gradation processing clock that is twice as high as a normal clock.
Accordingly, the pixel data and the error data are divided into upper bits and lower bits, and each of them is processed by one clock of the high gradation processing clock, so that the number of bits of the register and the arithmetic circuit remains low gradation, and High gradation halftone processing can be performed without reducing the processing speed.

According to the structure described in claim 4, for example, when a document having an effective reading width of B4 size and A4 size is read, the empty memory area generated in the image processing memory is effectively used to perform halftone processing. By increasing the memory area of, you can increase the number of bits such as error data,
Gradation can be improved.

[0017]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of an image processing apparatus according to an embodiment of the present invention. In the figure,
1 is an A / D converter, which is a contact sensor or CCD (Ch
Converts analog image data read by a scanner (not shown) such as argeCoupled Device) into 8-bit digital image data. A shading / peak level correction unit 2 performs shading correction and peak level correction on the digital image data from the A / D converter 1. Reference numeral 3 denotes a γ correction unit that performs γ correction only during halftone processing on digital image data that has been subjected to shading correction and peak level correction. 4 is MTF (Modulati
on Transfer Function: Modulation transfer function) Correction unit, 3 ×
By configuring the matrix of No. 3, MTF correction in the line drawing mode is performed. A halftone processing unit 5 performs halftone processing using the error diffusion method, and its gradation is controlled by a gradation control unit 8 described later. Reference numeral 6 denotes a binarizing unit, which compares the digital image data that has been subjected to the MTF correction or halftone processing with the threshold data to determine whether it is black or white, and sends the result to the line buffer memory.

Reference numeral 7 denotes a RAM interface (I / I) for reading or writing shading correction data, MTF data, error data, threshold value data and the like with respect to the RAM 7a.
In the section F), a DMA request is generated and a chip select signal of the RAM 7a is generated to read / write data. A gradation control unit 8 changes the gradation of the error diffusion method by controlling error data, threshold values, γ correction characteristics, and the like. Reference numeral 9 is a processing clock shifting unit, which is the shading / peak level correcting unit 2, the γ correcting unit 3, and the MT.
By switching between two types of clocks having different speeds supplied to the F correction unit 4, the halftone processing unit 5, and the binarization unit 6, etc., the processing clock in the normal time and the processing clock in the high gradation (the above The speed is controlled at twice the processing clock frequency. As a result, in each of the units 2 to 6, normally, one pixel is processed with one processing clock, and when the gradation is high, one pixel is processed with two processing clocks.

Next, the operation will be described with reference to FIGS. First, the analog image data read by the scanner is converted into digital image data by the A / D converter 1. 17 when the scanner scans A4 size
28 pieces, 2048 pieces of image data in the case of B4 size are A
When the A / D converter 1 has an 8-bit resolution, 8-bit digital image data is output, and when the A / D converter 1 has a 10-bit resolution, 10-bit digital image data is output. Here, it is assumed that 8-bit digital image data is output with 8-bit resolution.

The image data converted into a digital signal is subjected to shading correction and peak level correction in the shading / peak level correction unit 2. In the shading correction, the way in which the light from the LED hits, the distance to the CCD, and the like change due to the difference in the scan position. Specifically, by reading white reference data such as a white pressure plate that presses the original against the contact glass,
The white reference data is obtained at each reading position to calculate a correction coefficient, and the correction coefficient is used to perform the correction. The correction coefficient is R
Through the AM interface unit 7, the shading correction data storage memory area (see FIG. 2) of the RAM 7a is written or read. Also, the peak level correction is 1
The line read data is normalized, and the correction is performed by detecting the peak value and dividing each pixel data with it.

Up to this point, the processing is the same in the line drawing mode and the halftone mode, but the processing changes from the next γ correction section 3. The γ correction unit 3 converts from 7 bits to 6 bits in 64 gradations by simply deleting the lower 1 bit in the line drawing mode. However, in the halftone mode, conversion from 7 bits to 6 bits is performed in 64 gradations by using a predetermined arithmetic expression. By performing this correction, reflection linear conversion as shown by a in FIG. 3 is performed in the line drawing mode, and density linear conversion as shown by b in the same figure is performed in the halftone mode. Here, when changing the gradation, the gradation control unit 8
When more control signals are sent and it is desired to reduce to 32 gradations, the data converted from 7 bits to 6 bits is further erased by the lower 1 bit to be converted to 5 bits. When it is desired to reduce to 16 gradations, the lower 1 bit is further erased and converted to 4 bits.

The image data on which the γ correction has been performed is based on the mode setting, and in the line drawing mode, the MTF correction unit 4 performs MTF correction.
Correction is performed (determination 101 in the flowchart of FIG. 7 →
Process 102). MTF (Modulation Transfer Functio)
n: Modulation transfer function) correction is to correct the blur of an image generated by converting and transmitting a signal, by correcting the front, back, left, and right images of a desired image. The correction is shown in Figure 4.
As shown in (a), a 3 × 3 matrix is formed, the central pixel E is tripled to 5 times, and pixels adjacent to the central pixel are subtracted to obtain image data of the central pixel.
However, this correction is basically not performed during the halftone processing (correction is applied in the case of an edge pixel which is a boundary between the line drawing portion and the photograph portion).

In the line drawing mode, after the MTF correction is performed, the binarization unit 6 compares the image data with a threshold value to make a final judgment of white / black to obtain eight binarized data. DMA transfer is performed to the line buffer memory in units.

In the halftone mode, after the setting of each function such as the number of halftone gradations, halftone processing is performed by the halftone processing unit 5 using the error diffusion method based on the set number of gradations. It is performed (decision 101 → process 103 → decision 104). The error diffusion method is a method for compensating the difference between the result of outputting a certain pixel and the threshold value with surrounding pixels. As illustrated in FIG. 4B, five registers for the previous line and the current line are used. The error diffusion calculation is performed by forming a matrix with a total of eight registers for use.

For example, if the pixel of interest in FIG. 4B is h, the pixel closest to h is weighted 4 times, the next closest weight is doubled, and the farthest pixel is weighted 1 time. The data is ((a + e) + 2 * (b + d + f) + 4 *
(C + g)) / 16. The error diffusion process is performed by adding the pixel data of h to this. 64
At the time of gradation, a to g used for this error data are 7 bits including polarity (6 bits without polarity), and pixel data is also 6 bits (decision 104 → process 105). 32
When the gradation is reduced, a control signal is output from the gradation control unit 8 and the error data a to g are converted into 6 bits (decision 104 → process 106). Regarding the movement of the data of the error diffusion matrix, the previous line data a to e are first read from the RAM 7a via the RAM interface unit 7 into the register of e. When the processing for the next pixel is started, the data in the register e is transferred to the register d, and the next data comes from the RAM 7a into the register e. In this way, the operation of inputting from the RAM 7a to e, and transferring d → c →→ b → a is repeated. At this time, when changing the gradation to 32 gradations, the e register is fixed to 6 bits, and when changing the gradation to 16 gradations, it is fixed to 5 bits.

When h data is calculated, the current line data is transferred to the g register at the time of processing the next pixel, and transferred as h → g → f as in the previous line. At this time, h data is written in the RAM 7a through the RAM interface section 7 for processing the next line. When transferring from the h register to the g register, the g register is fixed to 5 bits at 32 gradations and fixed to 4 bits at 16 gradations. The pixel data is also fixed to 5 bits for 32 gradations and 4 bits for 16 gradations. The halftone-processed image data is binarized by the binarization unit 6. At this time, the threshold data is also 6 bits for 64 gradations, 5 bits for 32 gradations,
At the time of 16 gradations, it is binarized by fixing it to 4 bits. The bit change is performed by erasing one bit of the LSB (least significant bit). For example, when setting 32 gradations, 7-bit data at 64 gradations is 0111000.
If it is (+56), erase the LSB 1 bit and set 01.
1100 (+28). When it is 1111000 (-8), it is set to 111100 (-4).

By doing so, it is possible to change the setting of the number of gradations with the same hardware configuration, it is possible to have a wide range of gradations with the same device, and it is necessary to have too high gradations. When dealing with images that do not
Higher speed can be achieved by reducing the number of bits.

Further, when an A4 original is read with an effective reading width of B4 size and the memory map shown in FIG. 2 is set, addresses 0000h to 063Fh, 0 are set.
A4 for 800h-0E3Fh and 1000h-163Fh
Used in size, 0640h to 07FFh, 0E
40h to 0FFFh and 163Fh to 17FFh are not used at A4. Therefore, the gradation is improved by opening this unused area for storing error data.
Specifically, the error diffusion matrix register is provided with 8 bits and only 7 bits are used when reading B4 size. Then, when the A4 size is read, it is used with 8 bits full, and the address of the unused area is addressed by the gradation control unit 8, so that the halftone processing of 128 gradations, which was normally 64 gradations, becomes possible. . Further, since it can be used for MTF data and the like in addition to error data, it is possible to improve each correction capability.

However, if the user wants to use the above-mentioned free memory but does not want to increase the number of bits of the register, the processing clock shifting unit 9 shifts the processing clock so that the bits of the arithmetic circuit such as the register and the full adder are changed. Even if the number is not increased, the free memory can be used to improve the gradation. By attaching an external RAM and increasing the memory, the gradation can be improved without increasing the number of bits of the register or the like by changing the processing clock even when reading the B4 size.

FIG. 5 is a block diagram of an arithmetic circuit provided in the shading / peak level correction unit 2, the γ correction unit 3, the MTF correction unit 4, the halftone processing unit 5, and the like. The data output multiplexer 10 and the full adder 11 are shown in FIG. , The first register 12, the second register 13, and the polarity selection unit 14
Consists of. By controlling the multiplexer 10 and the polarity selecting section 14 in a predetermined procedure by using the arithmetic circuit having the same configuration, a predetermined arithmetic operation is performed according to each correcting section. The arithmetic processing of each part will be described with reference to FIG.
Full adder 1 for each pixel data in the matrix
Output to 1. The full adder 11 adds the output data of the data output multiplexer 10 and the output data of the second register 13 input via the polarity selection unit 14.
The addition result of the full adder 11 is held in the first register 12. The polarity selection unit 14 selects the polarity depending on whether the output data of the second register 13 is added or subtracted, and is output as it is at the time of addition, and the data is inverted and incremented by +1 at the time of subtraction, that is, the complement is output. .

In the normal state, as shown in FIG. 6 (a), one pixel is processed by one processing clock, and at the time of 64 gradations, the error data register is 7 bits and the adder is It is 8 bits. However, when 128 gradations are set, first, the lower 4 bits of data of one pixel are transferred from the RAM 7a, then the upper 4 bits thereof are transferred, and then the lower 4 bits and upper 4 bits of the next pixel are repeated. Transferred. Then, as shown in FIG. 6B, the processing clock is doubled to process one pixel in two clocks, so that the lower bit is calculated in the first clock and the result is the first. It is held in the register 12. Next, when calculating the upper 4 bits, the first register 12
The lower operation result of (1) is transferred to the second register 13, and the upper operation result is held in the first register 12. Next, the lower 4-bit data of the next pixel is input to the full adder 11 and added to the lower operation result of the second register 13. At this time, if there is a carry from the lower order, the carry flag is held in the register, and 1 is added at the time of the next higher bit operation. By doing so, when the memory area is increased in the low gradation circuit, high gradation halftone processing can be performed without decreasing the processing speed while maintaining the number of bits of the register or the arithmetic circuit (determination). 104 → Process 10
7-> decision 108-> process 109 or process 110).

The image processing apparatus can be applied to various image processing apparatuses for digitally processing an image, such as a digital copying machine, in addition to the facsimile apparatus.

[0034]

As described above, according to the first aspect of the present invention, the halftone processing unit for performing the halftone processing on the digital image data having the number of bits corresponding to the number of gradations by using the error diffusion method. And the halftone-processed pixel data is set to 2 using the threshold value data of the number of bits according to the number of gradations.
A binarization unit for binarization, a memory unit for storing error data used in the halftone processing unit and threshold data used in the binarization unit, pixel data processed by the halftone processing unit, and error data And a gradation control unit that variably controls gradation by controlling the number of bits of the threshold data provided to the binarization unit. Therefore, the gradation control unit controls pixel data and error data. By controlling the number of bits of the threshold data and the gradation property, the gradation property can be variably controlled, so that the setting of the gradation number can be changed with the same hardware configuration. Therefore, there is an effect that the same device can have a wide range of gradation and can be differentiated from other devices.

According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the gradation control section includes:
Since the number of gradations is changed by deleting the lower bits of the pixel data, the error data, and the threshold data, the same effect as that of claim 1 can be obtained, and the gradation data is controlled by the gradation control unit. By deleting the lower bits of the error data and the threshold data, the number of gradations can be reduced. Therefore, for example, when handling an image that does not require high gradation, there is an effect that the speed can be increased by reducing the number of bits.

According to a third aspect of the present invention, in the image processing apparatus according to the first aspect, there is provided a processing clock speed changing unit for changing the processing clock for performing image processing to a high gradation processing clock having a frequency which is a multiple of the normal frequency. The gradation control unit divides the pixel data and the error data into a plurality of parts at the time of the high gradation processing clock, and processes each of them with one clock of the high gradation processing clock to obtain a high gradation half. Since the tone processing is performed, the same effect as that of the first aspect can be obtained, and the processing clock is changed to, for example, a high gradation processing clock that is twice as high as the normal one, and accordingly, the pixel data and the error data are respectively placed in the higher order The number of bits in the register and arithmetic circuit is low because it is divided into bits and low-order bits, and each is processed with one clock of the high gradation processing clock. It remains, and without reducing the processing speed, there is an effect that it is possible to perform a high grayscale halftone processing.

According to a fourth aspect of the present invention, in the image processing apparatus according to the first aspect, in the case of image data obtained by reading a document smaller than the effective reading width, the gradation control section is Since the high-gradation halftone processing is performed by increasing the number of bits of the error data and the threshold data by using the empty area generated in the memory unit, the same effect as that of claim 1 can be obtained. For example, when reading an A4 size original with an effective read width of B4 size, the empty memory area generated in the image processing memory is effectively used and the memory area for halftone processing is increased, so that error data, etc. The number of bits can be increased. Therefore, there is an effect that the gradation can be improved without increasing the memory for image processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a memory map of the above embodiment.

FIG. 3 is an explanatory view of anti-linear conversion in the line drawing mode and density linear conversion in the halftone mode in the above embodiment.

FIG. 4 is a diagram showing an MTF correction matrix and an error diffusion matrix of the above embodiment.

FIG. 5 is a block diagram showing an arithmetic circuit provided in each part of the above embodiment.

FIG. 6 is a diagram showing a processing timing according to the processing clock change of the embodiment.

FIG. 7 is a flowchart showing the operation of the above embodiment.

[Explanation of symbols]

 1 A / D converter 2 Shading / peak level correction unit 3 γ correction unit 4 MTF correction unit 5 Halftone processing unit 6 Binarization unit 7 RAM interface (I / F) unit 7a RAM 8 Gradation control unit 9 Processing clock Transmission section 10 Data output multiplexer 11 Full adder 12 First register 13 Second register 14 Polarity selection section

Claims (4)

[Claims] 1. A halftone processing unit for performing halftone processing on digital image data having a number of bits corresponding to the number of gradations by using an error diffusion method, and gradation of pixel data subjected to the halftone processing. A binarization unit that binarizes using threshold data having a bit number corresponding to the number; a memory unit that stores error data used in the halftone processing unit and threshold data used in the binarization unit; And a gradation control unit for variably controlling gradation by controlling the number of bits of pixel data processed by the halftone processing unit, error data, and threshold data given to the binarization unit. An image processing device characterized by: 2. The image processing apparatus according to claim 1, wherein the gradation control unit changes the number of gradations by deleting lower bits of pixel data, error data, and threshold data. Image processing device. 3. The image processing apparatus according to claim 1, further comprising a processing clock shifting unit that changes a processing clock for performing image processing to a high gradation processing clock having a frequency that is a multiple of a normal frequency, and the gradation control unit. In the high gradation processing clock, the pixel data and the error data are each divided into a plurality of parts, and each of them is processed by one clock of the high gradation processing clock, thereby performing high gradation halftone processing. Image processing device. 4. The image processing apparatus according to claim 1, wherein in the case of image data obtained by reading a document smaller than an effective reading width, the gradation control unit uses an empty area generated in the memory unit. By increasing the number of bits of the error data and the threshold data, high-gradation halftone processing is performed.