JPH0662224A - Image processor - Google Patents

Abstract

PURPOSE:To accelerate binarizing processing and to improve picture quality by performing binarization by deciding threshold value data corresponding to the density data of the prescribed addresses of an objective pixel in a preceding line and a pixel preceding the same line with this address as a reference at the time of binarizing the objective pixel. CONSTITUTION:This image processor is composed of a thinning processing part 100, peripheral pixel read processing part 200, binarizing processing part 300, output processing part 400 and image memory part 500. The processing part 100 is composed of an input image part 1 to supply pixel density data, pixel density data write circuit 2 to write the density data in an image memory, pixel counter 3, output resolution setting means 4, pixel element thinning circuit 5 and address counter 6. The processing part 200 is composed of a peripheral pixel address calculation circuit 9 and a read circuit 10 to read image data and density data from a pixel density storage memory 7, and the processing part 400 is provided with an output control circuit 14, and output result address calculation circuit 15 to calculate an output result address, or the like. The memory part 500 is provided with a binarized result storage memory 8 in addition to the memory 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus which binarizes an input image signal and outputs it as image data having different resolutions as needed.

[0002]

2. Description of the Related Art In an image processing apparatus such as an image scanner, a copy machine, a facsimile, etc., which performs binarization processing on an input image signal, in order to prevent thin line loss and reproduce halftone of a halftone dot photograph. In addition, when binarizing the signal of the target pixel to be image-processed, a method called floating binarization processing that determines the threshold value of the target pixel by using the density information of pixels around the target pixel is effective. Target. Further, when performing image processing on a halftone picture, a method of thinning out in a non-lattice form is effective in order to remove moire caused by the periodicity of the halftone picture and the periodicity of the input sample.

Now, let us say that the density of the target pixel is D, and the densities of the three surrounding pixels of this target pixel are A, B and C, respectively. In this case, in order to perform the floating binarization process, the floating threshold T shown in (Equation 1) is determined by calculation. The determined threshold value T is compared with the density D of the target pixel to obtain T
If> D, the binarization result R becomes R = 1 and a black pixel is obtained. If T ≦ D, the binarization result R becomes R = 0 and a white pixel is obtained.

[0004]

## EQU1 ## FIG. 6 is a diagram showing a threshold value T for the average density (S / 3) of surrounding pixels, where T0 is a fixed binary threshold value and Tf is a floating binary threshold value. Is shown. By performing the floating binarization process, the threshold value for the target pixel changes depending on the surrounding pixel density, so that the halftone in a halftone dot photo document can be faithfully reproduced, and even if the background has a color tone, the character Can be reproduced clearly, and thin lines can be prevented from missing.

If the threshold value is determined using the density data of pixels on the same line as the target pixel, thin lines in the horizontal direction are likely to be missing. Therefore, an image density memory for at least one line is provided. The threshold value is determined by using the density data of pixels on a plurality of different lines.

FIGS. 7 to 9 are views showing non-lattice thinning-out processing for converting the resolution of input image data into a low resolution and outputting it. FIG. 7 shows 400 DPI (dot
The pattern at the time of converting the input image data with the resolution of per inchi) into 100 DPI is shown. In FIG. 7, a small area surrounded by a thin line represents each pixel, that is, an input pixel area, and an area surrounded by a thick line represents an output pixel area. Furthermore, the pixel area of the circle mark is
As a result of the non-lattice thinning-out process, the selected pixel, that is, the output pixel is shown. The output pixel area is composed of 16 pixels of 4 × 4, but the relative positions of all the selected pixels are different, and they are non-lattice.

FIGS. 8 and 9 are diagrams showing patterns for converting resolution from 400 DPI to 200 DPI and 300 DPI, respectively. In this way, by thinning out in a non-lattice pattern, it is possible to remove moire caused by the periodicity of the halftone dot original and the periodicity of the input sample.
Further, since the selected pixels are arranged in all columns and all rows in the main scanning direction and the sub scanning direction, thin line loss due to thinning is unlikely to occur. When the non-lattice thinning processing is used, one output line is generated from a plurality of input lines of image data. In FIG. 10, four pixels p1 to p4 have different input lines, but output lines are on the same line. Therefore, it is necessary to provide a memory with a maximum of one line to store the image density data or the binarization result. That is, the pixels p1 and p2 are stored,
The pixels p3 and p4 output in real time. Pixel p4
Is output, the pixels p1 and p2 are output.

[0008]

However, the conventional image processing apparatus has the following problems.

FIG. 11 shows a first conventional example. In this example, the arrangement relationship between the target pixel D and the surrounding pixels A, B, and C is as shown in FIG. In this case, as shown in FIG. 11B, since the floating binarization processing is performed using the density data of the surrounding pixels A, B, and C after the non-grid thinning processing, there are the following problems. It was

(1) Since the pixel C exists on the line next to the line on which the target pixel D exists, the floating binarization process of the target pixel D cannot be performed in real time.

(2) Since the addresses of the peripheral pixels A and C in the main scanning direction are batting (identified), a memory for storing pixel density information of at least 2 to 4 lines is required, and the address management of the memory is required. Becomes complicated and becomes a factor of cost increase.

In the second conventional example shown in FIG. 12, the arrangement relationship between the target pixel D and the surrounding pixels A, B and C is shown in FIG.
It is as shown in (a). Therefore, since the floating binarization process is performed according to the procedure shown in FIG. 12B, the problem that the addresses of the surrounding pixels are batting can be solved, but since the pixel C exists in the line next to the target pixel D, two lines still exist. Therefore, there is a problem that a memory for four lines is required, and real-time floating binarization processing cannot be performed.

FIG. 13 shows a third conventional example, in which the target pixel D
Since the positional relationship between the pixels and surrounding pixels A, B, and C is as shown in FIG. 13A, real-time floating binarization processing can be performed, and the first and second problems can be solved. However, there is a new problem in that the positions of the surrounding pixels are too far away from the target pixel D and proper floating binarization processing cannot be performed.

A configuration in which the floating binarization process is performed by using pixels before thinning is also conceivable. In this case, a memory for the thinning process and its address, and a memory for the floating binarization process. And its address must be provided separately, which causes a problem of increasing memory and complicating address operation.

If hardware is used to compensate for the fact that the processing time is delayed because it cannot be processed in real time, a new problem arises that the hardware becomes expensive.

The present invention solves the above-mentioned various problems of the related art, and an appropriate floating binarization process is performed by using an image density memory of only one line without requiring complicated address management of the memory. It is an object of the present invention to provide an excellent image processing device that can perform the image processing in real time.

[0017]

In order to achieve the above object, the present invention provides thinning means for thinning pixels of input image data according to output resolution, and density data of pixels selected by the thinning processing. A first memory for storing and a second memory for storing binarized data of the selected pixel
And a reading means for determining one or a plurality of predetermined address groups of the first memory according to the address of the target pixel to be binarized, and reading the density data of the determined address group, Threshold value determining means for determining threshold value data from the generated density data, and binarization for performing binarization processing of the target pixel by comparing the density data of the target pixel with the threshold data. Processing means and binarized binarized data of the target pixel are stored in an address corresponding to an address of the target pixel of the second memory, and density data of the target pixel is stored in the first memory. Writing means for storing the target pixel in the memory at an address corresponding to the address of the target pixel, and data output means for reading the binarized data of the target pixel from the second memory and using this as output image data. And has a configuration was.

[0018]

According to the present invention, when the target pixel is binarized, the density of the pixel at the predetermined address of the pixel one line before and the pixel on the same line as the target pixel is based on the address of the target pixel. By determining the threshold data from the data and performing the binarization, the binarization process can be speeded up, the cost of the device itself can be reduced, and the image quality displayed by the output image data can be improved. .

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall functional configuration diagram of an embodiment of an image processing apparatus according to the present invention. The overall configuration shown in FIG. 1 includes a thinning processing unit 100, a surrounding pixel reading processing unit 200, a binarization processing unit 300, an output processing unit 400, and an image memory unit 5.
00 functional units.

In the thinning processing unit 100, 1 is 256
An input image unit that supplies pixel density data of gradation in pixel units, and 2 is a writing circuit as a writing unit that writes the pixel density data in an image memory. A pixel counter 3 counts input pixels, and outputs a count value for each input pixel. An output resolution setting unit 4 sets the resolution of the output pixel and sends the output resolution data. Reference numeral 5 is an input pixel thinning circuit that determines an address of a pixel to be thinned, that is, a thinning address, based on the count value from the pixel counter 3 and the output resolution data from the output resolution setting means 4, and 6 is from the pixel counter 3. Is an address counter that manages the address related to the pixel data of this device by the count value of
Pixel data to be stored in the image memory is designated according to the thinning-out address from the input pixel thinning-out circuit 5.

In the density image memory section 500, 7 is a pixel density storage memory as a first memory for storing the pixel density data from the pixel density data writing circuit 2,
Reference numeral 8 denotes a binarization result storage memory as a second memory for storing the binarization result of the pixel density data. Although the pixel density storage memory 7 and the binarization result storage memory 8 are separate memories, they can be configured by a single memory having a storage area of a plurality of bits for each address.

In the surrounding pixel reading processing unit 200, 9
Is a peripheral pixel address calculation circuit for calculating the addresses of the peripheral pixels of the target pixel to be binarized, and 10 is a pixel for reading the target pixel data and its peripheral pixel data from the pixel density storage memory 7 in accordance with the addresses of the peripheral pixels. This is a density data writing circuit.

In the binarization processing unit 300, 11 is a threshold value determining means for calculating a threshold value for binarization based on the target pixel data obtained from the pixel density data writing circuit 10 and the surrounding pixel data. Reference numeral 12 is a threshold value calculation circuit, 12 is a binarization processing circuit as a binarization processing means for performing binarization processing of the target pixel with the calculated threshold value, and 13 is binarized binarization. This is a binarization result data writing circuit for writing the result data to the binarization result storage memory 8.

In the output processing unit 400, 14 is an output control circuit for controlling the output of pixel data.
Reference numeral 5 is an output result address calculation circuit for calculating the address of the output pixel forming the image based on the command of the output control circuit 14, and 16 is a binarization result storage memory according to the calculated output pixel address. 8 is an output result data reading circuit as a reading means for reading from 8. Reference numeral 17 denotes an output image section as a data output unit configured by the output result data from the output result data reading circuit 16.

Next, the operation of the image processing with the configuration of FIG. 1 will be described with reference to FIGS.

FIG. 2 shows a procedure for performing the floating binarization process according to the present invention. For example, when the target pixel to be binarized is D, the address of the target pixel D is used as a reference.
The address of the pixel density storage memory 7 in which already input pixels are stored is determined. In the case of FIG. 2, the address on the line (main scanning direction) of the target pixel D is 1, so the addresses of the memory are determined to be 0, 1 and 2, and the data of the pixels D1, D2 and D3 of that address are determined. Is read out to determine threshold value data for binarizing the target pixel D.

FIG. 3 shows a configuration for storing data of one pixel in the pixel density storage memory 7. In this case, the input resolution of the input image data is 400D
Since it is PI and the density of the input pixel is 256 levels, it is captured as 8-bit density data.
Further, the least significant bit data of the 8-bit data is deleted, and the 7-bit data is stored in the memories b7 to b1 as density data. The least significant bit R of the memory stores the binarized data that has been binarized. Since the number of pixels of the image data in the main scanning direction, that is, the number of lines is 1600, the memory capacity is 1
It is 1600 bytes of 8 bits.

The output resolution of the output image data is 4
00, 300, 200, and 100 DPI, and can be switched according to a command from a device that outputs image data or according to an operation.

4 and 5 are flow charts showing the operation of the image processing apparatus of this embodiment. In these flow charts, H is an 11-bit horizontal pixel counter, which manages addresses of 1600 pixels from 1 to 1600. V is a 5-bit vertical pixel counter. Z is 1
It is a thinning flag of bits. When this flag is 1, pixel data is selected, and when it is 0, it is discarded without being selected. L is a 1-bit line type flag, and when this flag is 1, image data is output. A is an 11-bit address counter, and AD is a 1-bit address increment flag. When the flag AD is 1, the address counter A is incremented.

In FIG. 4, when the resolution of the image data to be output is set (step S1), V = 0, H = 0 and A = 0 are initialized (step S2). Next, a pixel processing subroutine is performed (step S3). After this image processing, it is determined whether the flag AD is 1 (step S4), if it is 1, the value of the address counter A is incremented by 1 (step S5), and if it is not 1, it is not incremented. The horizontal pixel counter H
The value of is incremented by 1 (step S6). Next, it is determined whether or not the value of the horizontal pixel counter H is 1600, that is, the last pixel of the line (step S7). If it is not the last pixel, the process proceeds to step S3 and the processes up to step S7 are executed. H in step S7
When the value of becomes 1600, H = 0, A = 0 and V
= V + 1 is set (step S8), and it is determined whether or not the pixel processing of all pixels is completed (step S9). If the pixel processing of all the pixels is not completed, the process proceeds to step S3 and the processes up to step S9 are executed. When the pixel processing of all the pixels is completed in step S9, the operation of this image processing is completed.

FIG. 5 is a flow chart showing the pixel processing subroutine (step S3) in the flow chart of FIG. In FIG. 5, a thinning flag Z, a line type flag L and an address increment flag AD
Is determined (step S30).

Regarding the determination of the thinning flag Z, the arithmetic expression differs depending on the output resolution. In the case of 100 × 100 DPI, Z is determined by (Equation 2), and 200 × 200D is determined.
For PI and 300 × 300 DPI, Z is determined by (Equation 3) and (Equation 4), respectively.

[0034]

[Equation 2]

[0035]

[Equation 3]

[0036]

## EQU00004 ## When the output resolution is 400.times.400 DPI, that is, when the input resolution and the output resolution are the same, thinning is not performed and Z = 1.

The line type flag L and the address increment flag AD have an output resolution of 100 × 100D.
PI, 200 x 200 DPI and 300 x 300 DPI
In some cases, it is determined by (Equation 5), (Equation 6) and (Equation 7), respectively.

[0038]

[Equation 5]

[0039]

[Equation 6]

[0040]

## EQU00007 ## When the output resolution is 400.times.400 DPI, L = 1 and AD = 1.

Next, it is determined whether Z = 1 (step S31). If Z = 1 is not satisfied, the target image data (D) after thinning is fetched (step S32). When the pixel data D in FIG. 2 is the target pixel and the address of the target pixel is A, the density data is transferred from the addresses A-1, A and A + 1 of the image memory to the surrounding pixels D1, D.
2, D3 are read (step S33), and the surrounding pixel total S is calculated by (Equation 8) (step S34).

[0042]

## EQU8 ## The threshold value T is calculated from the calculated surrounding pixels S based on (Equation 9), the density data D of the target pixel is compared with the threshold value T, and the floating binarization processing is performed (step S
35).

[0043]

[Equation 9] By the floating binarization process, the binarization result R and the density data of the target pixel are written to the address A of the image memory (step S36). That is, the density data of the address A and the binarization result are updated. Next, it is determined whether the bit logical product AD & L of AD and L is 1 (step S37), and if it is 1, the binarization result R is read from the image memory (step S38), and The quantized result is output (step S39).

After outputting the binarization result, and step S
If Z = 1 is not satisfied in step 31 and the bit logical product AD & L is not 1 in step S37,
To step S4 (return).

As described above, when the target pixel is binarized, regardless of the pixel position, the pixels of one line before and on the same line as the target pixel are determined based on the address of the line of the target pixel. The threshold value data is determined from the density data of the pixel at the address, and binarization is performed.

[0046]

As is apparent from the above-described embodiment, the present invention, when binarizing a target pixel, uses the address of the line of the target pixel as a reference, one line before and before the same line as the target pixel. The threshold value data is determined from the density data of the pixel of the predetermined address of the above pixel and binarization is performed, so that the image density memory of only one line can be stored without the need of complicated memory address management. By using it, it is possible to perform appropriate floating binarization processing in real time, and it is possible to obtain the effects of speeding up the binarization processing, lowering the cost of the device itself, and improving the image quality displayed by the output image data. To be

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a diagram showing a state of pixel processing in the present embodiment.

FIG. 3 is a diagram showing a configuration for storing image data in an image memory in this embodiment.

FIG. 4 is an operation flowchart of image processing in this embodiment.

5 is a flowchart of a subroutine of pixel processing in FIG.

FIG. 6 is a diagram showing a threshold value with respect to an average density of surrounding pixels in a conventional example.

FIG. 7: 400 DPI to 100 DPI in the conventional example
It is a figure which shows the mode of non-grid thinning in the case of converting the resolution into.

FIG. 8 is 400 DPI to 200 DPI in the conventional example.
It is a figure which shows the mode of non-grid thinning in the case of converting the resolution into.

FIG. 9 is 400 DPI to 300 DPI in the conventional example.
It is a figure which shows the mode of non-grid thinning in the case of converting the resolution into.

FIG. 10 is a diagram showing how one output line is generated from a plurality of input lines of image data when non-lattice thinning processing is used.

11A is a diagram of a first example showing a positional relationship between surrounding pixels A, B, and C and a target pixel D in a conventional image processing apparatus. FIG. FIG. 11B is a diagram showing a state of pixel processing in FIG.

FIG. 12A is a diagram of a second example showing a positional relationship between surrounding pixels A, B, and C and a target pixel D in a conventional image processing apparatus. FIG. 12B is a diagram showing a state of pixel processing in FIG.

FIG. 13A is a diagram of a third example showing the positional relationship between the surrounding pixels A, B, and C and the target pixel D in the conventional image processing apparatus. FIG. 13B is a diagram showing a state of pixel processing in FIG.

[Explanation of symbols]

 100 Thinning processing unit 200 Surrounding pixel reading processing unit 300 Binarization processing unit 400 Output processing unit 500 Image memory unit D Target pixel D1, D2, D3 Surrounding pixels

Claims (3)

[Claims] 1. An image processing apparatus for converting input resolution of input image data into output resolutions of a plurality of different resolutions and outputting as output image data, wherein pixels of the input image data are thinned according to the output resolution. Thinning means for performing processing, a first memory for storing density data of pixels selected by the thinning processing, a second memory for storing binarized data of the selected pixels, and binarization processing Read-out means for determining one or a plurality of predetermined address groups of the first memory according to the address of the target pixel and reading the density data of the determined address groups, and a threshold value from the read density data Threshold value determining means for determining data, and binarization processing means for comparing the density data of the target pixel with the threshold value data to perform binarization processing of the target pixel. Storing the binarized data of the target pixel that has been binarized at an address corresponding to the address of the target pixel in the second memory, and storing the density data of the target pixel in the first memory. A writing means for storing the target pixel at an address corresponding to the address of the target pixel; and a data output means for reading the binarized data of the target pixel from the second memory and using this as the output image data. An image processing device characterized by: 2. The image processing apparatus according to claim 1, wherein the reading unit determines the address group by adding a predetermined integer to an address of the first memory. 3. The first and second memories are a single memory having a storage area of a plurality of bits for each address, and the binarized data is stored in one bit thereof, and the density data remains. The image processing apparatus according to claim 1, wherein the image processing apparatus stores the data in each bit.