JPH0775397B2 - Image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image processing apparatus including a memory having a plurality of storage units for respectively storing multi-valued image data and binary image data.

ii) Prior Art Generally, an image scanning system using a rotary polygon mirror or a vibrating mirror has a large scanning angle, a small color dispersion, and the like, and thus a facsimile device using laser light, various image display devices, and a printing device. It is widely used as a high-speed scanning system, in particular, the one using a rotating polygon mirror.
In order to record and display a halftone image by such an image scanning system, conventionally, one pixel on the recording / display surface is constituted by a matrix structure composed of n × n fine pixels where n is a positive integer. The halftone is recorded / displayed by the black and white distribution of each fine pixel in the matrix, that is, the distribution of the white fine pixel and the black fine pixel. That is, for example, as shown in FIG. 1, one pixel has a matrix structure composed of 2 × 2 fine pixels,
In order to reproduce the halftone of No. 2 by the combination of the black and white of the fine pixels 2, as shown in sequence (0) to (4) in FIG.
The number of fine pixels 2 to be black is sequentially increased so as to reproduce the halftone brightness of five stages, and generally, n × n + 1 stages of gradation are reproduced by n × n fine pixel matrix.

The advantages of the halftone image recording / display according to the above-described aspect are as follows: (1) Since the recording / display of each fine pixel can be controlled by a binary digital signal of black and white, the system configuration is simplified.

(2) Therefore, the gamma characteristic of the photoconductor can be made non-linear, and the photoconductor can be arbitrarily selected.

Etc. can be mentioned.

Such an image processing method is generally called a density pattern method, and one pixel read from the original image is associated with a density pattern consisting of n × n fine pixels, and a predetermined number of black fine patterns corresponding to respective gradations. In order to express the gradation by a pixel and improve the reproducibility of a halftone, it is necessary to increase the number n and use a fine pixel matrix having a large area. However, if the fine pixel matrix is increased, the gradation of the image is improved, but the resolution is impaired.
When an original binary image having no halftone such as a line drawing is reproduced, a pattern peculiar to the edge portion of the character or line drawing appears, and the edge of the binary pixel becomes unclear. On the contrary, if the number of fine pixels in the matrix forming the pixels is reduced to reduce the fine pixel matrix, the resolution is improved for binary images such as characters and line drawings, but for halftone images. There is a drawback that the gradation is deteriorated.

In order to solve such a drawback, a technique for performing image processing suitable for each of the input image and the halftone image portion or the binary image portion is disclosed in, for example, JP-A-55-120025. Has been done.

However, in the above technique, since the input pixel data is processed in real time, it is possible to efficiently store the image data while maintaining the resolution and gradation when performing the above processing. Was not considered.

iii) Object The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, efficiently store multi-valued image data and binary image data among pixel data input by the input means, and improve resolution and gradation. It is an object of the present invention to provide an image processing device capable of obtaining a good composite image of.

In order to achieve such an object, the present invention includes an input unit (corresponding to the input device 40 in the embodiment) for inputting image data for each pixel, and a plurality of pixels for the image data input by the input unit. Multi-valued image processing means (also A / D converter 42, clock W ₂ ) for extracting multi-valued image data representing a representative value of the density in the block, and image data input by the input means. A binary image processing means (similarly to a binarization circuit 43) for processing the image data as binary image data, and the multivalued image data extracted by the multivalued image processing means in units of blocks from the binary image processing means. Of 2
A memory having a plurality of storage units (also image memory (A) 46A and image memory (B) 46B) for storing the value image data in pixel units, and a representative of the densities in the blocks stored in the storage unit. A conversion unit (also an address counter 51A) that outputs multi-valued image data for each pixel that represents the light and shade of each pixel based on the multi-valued image data that indicates a value; Signal generating means (also zone memory 41) for generating a signal indicating position information for synthesizing with image data, and multi-valued image data and binary image data are synchronously read out from the plurality of storage sections, and the conversion is performed. Output means for synthesizing and outputting the multi-valued image data output by the means and the binary image data read out from the storage unit in accordance with a signal indicating position information from the signal generating means. Characterized in that it has.

iv) Examples Hereinafter, the present invention will be described in detail with reference to the drawings.

First, FIG. 2 shows a schematic configuration of an image recording apparatus suitable for applying the image processing according to the present invention. In the configuration shown in the figure, the light beam modulated by the image signal from the semiconductor laser 11 is applied to the rotary polygon mirror 12 via the collimator lens 10 to be deflected, and the deflected light beam causes the imaging lens 13
The photosensitive drum 16 is scanned via. At the time of scanning the light beam, the tip of one-line scanning of the light beam is reflected by the mirror 14 and made incident on the photodetector 15, and the photodetector 15
The detection signal from is used as a synchronization signal for constant scanning in image scanning.

Further, FIG. 3 shows an example of a schematic configuration of an image reading apparatus which forms an image signal to be processed by the image processing apparatus of the present invention. In the configuration shown, the original image 20 is placed on the digitizer 24, and a preceding image from the original image is formed on the line sensor 22 via the imaging lens 21 arranged above. The line sensor 22 is moved in the direction of the arrow at right angles to the longitudinal direction of the original image 20 to scan the surface of the original image 20.

Then, the original image original 30 read as described above is
As shown in FIG. 4 (A), it is assumed that the image is divided into a halftone image region 31 and a character part region 32, and is designated by identification codes “0” and “1” as shown in FIG. 4 (B). Then, the identification codes “0” and “1” are stored in a small capacity area designation memory, that is, a zone memory. For example, if an A4 size original is sampled with a roughness of 1 pixel per 1 mm square, approximately 200 x 300 = 60,000 pixels will be obtained. For such an image configuration, the area identification code described above for each pixel will be obtained. Even if the mark is added, it is sufficient to provide a zone memory with a capacity of 64K bits for one page of A4 size document.
Each pixel area identification code formed by the digitizer is stored in the zone memory.

FIG. 5 shows an example of a flow chart for storing such area identification code. In the flow chart shown in the figure, it is determined in step S1 whether or not the document to be processed is the image portion. If it is the image portion, "0" is stored in the corresponding address of the zone memory in step S2. , If it is not the image part, step
In S3, it is determined whether it is a character part. If it is a character part,
At step S4, set the corresponding address in the zone memory to "1".
And store the next signal respectively.

FIG. 6 shows an example of a circuit configuration for storing the image signal read by the image input device in the image memory based on the stored contents of the zone memory stored as described above. In the configuration shown in the figure, the analog image signal read out as a time series signal from the input device 40 is converted by the A / D converter 42 into, for example, a digital image signal having an 8-bit configuration. On the other hand, the clock generator 50 generates two types of clock signals w ₁ and w ₂ . Then, in the digital image signal, the halftone image portion is stored in the image memory in the form of the density data of the converted 8-bit structure as it is, and the character portion is binarized by a fixed threshold value to form a 1-bit structure. The image is stored in the image memory in the form of. If the density data of the halftone image is binarized by the density pattern method based on the 4 × 4 threshold matrix as shown in FIG. 7, the sampling width at the time of reading the image is the halftone image. Is required every 4 pixels, and characters and the like every 1 pixel. Therefore, the clock signal from the clock generator 50 is also of two types, the 1-pixel clock signal w ₁ and the 4-pixel clock signal w _2, and these two types of clock signals w ₁ and w ₂ are stored in the zone memory 41. Depending on the output signal, it is switched by the selector 49 and used for driving the image memory. That is, the 1-pixel clock signal w ₁ is used when the output signal of the zone memory is “1” corresponding to the character area, and the 4-pixel clock signal w ₁ is used when the output signal of the zone memory is “0” corresponding to the halftone image area. Use w ₂ .
Further, when reading data from the zone memory 41, the image memory 46 performs memory by fine sampling, whereas the zone memory 41 performs memory by sampling N times as coarse as that. Therefore, the 1-pixel clock signal is read.
Driven by the 1 / N division of w ₁ . For that purpose, the 1-pixel clock signal w ₁ from the clock generator 50 is divided by 1 / N by the 1 / N divider 48 to activate the address counter 47, and the address of the zone memory 41 is counted to make the zone memory 41
To drive.

The sampling interval of the input image signal from the input device 40 is set to the sampling interval of the A / D converter 42 by either of the clock signals w ₁ and w ₂ selected by the selector 49 which controls the switching operation by the output signal of the zone memory 41. Specify according to the content. That is, when the content of the input image signal is the character portion, sampling is performed at the cycle of the 1-pixel clock signal w ₁ , and when it is the halftone image portion, sampling is performed at the cycle of the 4-pixel clock signal w _2. Do. The digital image signal from the A / D converter 42 is guided to the data selector 45, and the zone memory 41
Under the control of the output signal of, the binarization circuit 43 binarizes the character portion based on a single threshold value to convert it into one-bit density data, and the one-bit density data is serialized. The parallel converter 44 collects the parallel density data of 8 bit structure in 8 bit cycle and supplies it to the image memory (B) 46B. For the halftone image part, the density data of 8 bit structure is directly stored in the image memory (B). A) Supply to 46A. Each image memory 46A and 46
In B, the address counters 51A and 51B for counting, via the converter 52, the respective clock signals w ₂ and w ₁ switched by the selector 49 for the halftone image part density data and the character part density data of 8 bit constitution. To specify the respective addresses and sequentially store them in the respective memory addresses.

For pixel clock signals for addressing such image memories 46A, 46B, for halftone images,
Since one pixel data corresponding to the 4 × 4 size of the read pixel may be stored as the density data, the pixel clock signal used for reading the image signal and storing it in the image memory 46A may be a constant scan of the image. It is possible to use a 4-pixel clock w ₂ for the direction and a horizontal synchronizing signal with a cycle four times that for the sub-scanning direction. The relationship of such clock cycles is shown in FIGS. 8 (A), (B),
It shows in (C). 6A shows a horizontal synchronizing signal, FIG. 6C shows a halftone image reading / writing clock signal, and FIG. 7B shows a pixel clock signal having a one-pixel clock period T. As can be seen from these figures, only in the halftone image area within one cycle of the horizontal synchronizing signal, the clock signal is generated at a cycle four times as long as the pixel clock cycle, and the clock signal is not generated in the other three pixel clock cycles. In this way, the 4-pixel clock signal w ₂ is generated from the clock generator 50 in the configuration shown in FIG.

On the other hand, for the character area, the sampling interval of the AD converter 42 is one pixel clock cycle shown in FIG. 8 (B), but the data is parallel-converted when writing to the image memory 46B. The operation is performed in an 8-pixel clock cycle. The conversion of the clock cycle is performed by the converter 52 in the configuration shown in FIG.

The input address for each of the image memories 46A and 46B is read by the address counter 51 at the various clock cycles described above.
Image memory 46A, 46B formed by A, 51B
To store the image data in each area. As for the arrangement of the image data to be written in the image memories 46A and 46B, as shown by hatching in FIGS. 9 (A) and 9 (B), the data is written from the beginning of the memory address. . That is, it is the output signal of the zone memory 41 that synchronizes the image in both the horizontal and vertical directions, and the image memories 46A and 46B simply pack the input data sequentially according to the instructions of the zone memory 41. The zone memory 41 controls to read the original document in accordance with the arrangement corresponding to the original document.

Next, FIG. 10 shows an example of a circuit configuration for reading out the image data respectively stored in the image memories 46A and 46B as described above and supplying the image data to the output device 64. In the configuration shown in the figure, as in the write circuit configuration shown in FIG. 6, the clock generator 50 generates clock signals having two types of clock frequencies w ₁ and w ₂ which are proportional to each other. These clock frequencies w ₁ , w ₂
Can be the same as in the write circuit configuration shown in FIG. In addition, the generator 50
The clock signal w.sub.1 from ₁ is divided by 1 / N by the 1 / N divider 48 and supplied to the address counter 47 to form an address signal for the zone memory 41. The image area control signal is read from the zone memory 41 under the control of the address signal, and the selector 49 is driven to select the two types of clock signals w ₁ and w ₂ from the generator 50.

In addition, the image memory 46
The A and 46B are driven by the two types of address counters 51A and 51B, respectively, and the image data of each area is read out. That is, the density data of the halftone image area is read from the image memory (A) 46A, and sequentially compared by the comparator 60 with the density data of the density pattern matrix 7 shown in FIG. 7 sequentially fetched from the read-only memory 61. And binarize it and supply the binarized density data to the selector 43. Further, the image data of the character area is read out in parallel from the image memory (B) 46B by 8 bits, converted into a bit serial state by the parallel-serial converter 62, and supplied to the selector 63 one bit at a time.

The above-mentioned two types of image data are controlled by the output signal of the zone memory 41 and selectively taken out by switching the selector 63, and supplied to the output device 64 such as a laser beam printer.

In the image processing device of the present invention, as described above, a plurality of types of images having different image qualities are respectively stored in the plurality of types of image memories under the control of the zone memory, and further read out to output the output device. The usefulness of such image processing includes the following items.

(1) Images to be processed in different modes can be divided and sequentially output, and for example, a character and a halftone image can be appropriately processed and output.

(2) Since the halftone image and the character can be stored in the memory device in separate modes, the memory capacity can be compressed and saved.

(3) Since the halftone image and the character are stored in separate memory devices, the subsequent processing is facilitated. For example, in the case of a color image, it becomes easy to perform masking processing, inking processing, etc. separately only on the halftone image, and different memory compression can be applied to each memory device. It is possible to perform run-length compression on the image data of the partial image and to perform differential quantization on the image data of the halftone image image.

Here, the memory capacity compression described in the item (2) will be described in detail. Generally, when applying the dither method and the density pattern method, appropriate threshold values are set for the image data of the halftone image area and the character area, respectively. Set it all 2
Suppose that it has been valued. At that time, the image data in the halftone image area is compared with the threshold matrix shown in FIG.
Since the binarization is performed, 16 bits of image data are formed for a 4 × 4 matrix.
It is possible to reduce the required memory capacity by storing the density data of 1 pixel, for example, 8 bits per 4 × 4 matrix. In addition, as the concentration data,
Although 8 bits of data are stored as described above, it is not always necessary to store all 8 bits, and 4 ×
It is possible to achieve halftone reproduction sufficiently with 4 to 5 bits as the density data for 4 matrices, and therefore it is possible to further reduce the memory capacity.
The reason why the 8-bit density data is stored in the above description is because the subsequent image processing is taken into consideration and the case where the threshold matrix is further increased is taken into consideration.

Further, although two kinds of image memories are used for storing the halftone image data and the character data, a single image memory may be divided and stored in different memory areas. A configuration example of a main part of a writing / reading circuit for an image memory according to this aspect
Shown in Figure 11. In the configuration shown in the figure, a selector 70 is provided to select different address signals from the address counters 51A and 51B in order to give different memory addresses to the image memory 46 for the halftone image data and the character data. At that time, each address signal is set in advance so that the image memory 46 can be spatially divided.

Further, it is needless to say that the case where the different processing is performed on the halftone image and the character can be dealt with by further developing the mode of the image processing described above.

v) Effects As described above, according to the present invention, the input unit for inputting image data for each pixel, and the image data input by the input unit are divided into a plurality of pixels in units of blocks. Multi-valued image processing means for extracting multi-valued image data representing the representative value of the density in the image, binary image processing means for processing the image data input by the input means as binary image data, and the multi-valued image The multi-valued image data extracted by the processing means is divided into the blocks, and
On the basis of a memory having a plurality of storage units for respectively storing the binary image data from the value image processing means on a pixel-by-pixel basis, and the multi-valued image data indicating the representative value of the density in the block stored in the storage unit. A conversion means for outputting multi-valued image data for each pixel, which represents the light and shade of each pixel, and a signal indicating position information for synthesizing the multi-valued image data and the binary image data stored in the storage section. And a multi-valued image data output from the conversion unit and a binary image read from the storage unit. By having the output means for synthesizing the data and the data in accordance with the signal indicating the positional information from the signal generating means,
It is possible to eliminate the above-mentioned drawbacks of the prior art and efficiently store multi-valued image data and binary image data among the image data input by the input means, and obtain a composite image with good resolution and gradation. it can.

[Brief description of drawings]

FIG. 1 is a diagram sequentially showing an example of a mode of halftone reproduction by a fine pixel matrix, FIG. 2 is a perspective view showing a schematic configuration of an image recording apparatus to which the present invention is applied, and FIG. 4 is a perspective view showing a schematic configuration of an image reading apparatus for carrying out image reading, FIGS. 4A and 4B are diagrams showing examples of images to be processed by the present invention, and FIG. 5 is image area identification according to the present invention. FIG. 6 is a flow chart showing an example of the process, FIG. 6 is a block diagram showing a configuration example of the image processing apparatus of the present invention, FIG. 7 is a diagram showing an example of a threshold matrix used in the present invention, FIG. 8 (A), 9 (B) and 9 (C) are signal waveform diagrams showing examples of various clock signals used in the image processing apparatus of the present invention, respectively.
11A and 11B are diagrams showing examples of the manner of storing image data in the image memory, and FIG. 10 is a block diagram showing another configuration example of the image processing apparatus of the present invention. FIG. 11 is a block diagram showing still another configuration example of the main part of the same. 10 ... Collimating lens, 11 ... Semiconductor laser, 12 ... Rotating polygon mirror, 13 ... Imaging lens, 14 ... Mirror, 15 ... Photodetector, 16 ... Photosensitive drum, 20 ... Original, 21 ...... Imaging lens, 22 ...... Line sensor, 23 ...... Density scale, 24 ...... Digitizer, 30 ...... Original, 31 ...... Halftone image area, 32 ...... Character area, 40 ...... Input device, 41 ...... Zone memory, 42 …… AD converter, 43 …… Binarization circuit, 44 …… Serial-parallel converter, 45 …… Data selector, 46,46A, 46B …… Image memory, 47,51A, 51B …… Address counter, 48 …… 1 / N divider, 49,63,70,71 …… Selector, 50 …… Clock generator, 52 …… Converter, 60 …… Comparator, 61 …… Lead Only memory, 62 ... Parallel-to-serial converter, 64 ... Output device.

Claims (1)

[Claims] 1. An input means for inputting image data for each pixel, and a multi-value indicating representative value of densities in the block for each block composed of a plurality of pixels for the image data input by the input means. Multi-valued image processing means for extracting value image data, Binary image processing means for processing the image data input by the input means as binary image data, Multi-valued image extracted by the multi-valued image processing means The data from the binary image processing means in units of 2
A memory having a plurality of storage units for respectively storing the value image data on a pixel-by-pixel basis, and the density of each pixel is represented based on the multivalued image data representing the representative value of the density in the block stored in the storage unit. Conversion means for outputting multi-valued image data for each pixel; signal generation means for generating a signal indicating position information for synthesizing the multi-valued image data and binary image data stored in the storage section; The multi-valued image data and the binary image data are synchronously read out from a plurality of storage sections, and the multi-valued image data output by the conversion means and the binary image data read out from the storage section are generated as the signal. An image processing apparatus comprising: an output unit configured to combine and output according to a signal indicating position information from the unit.