CN116721627B - Data signal processing method and data signal processing device - Google Patents
Data signal processing method and data signal processing device Download PDFInfo
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
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Abstract
The embodiment of the invention provides a data signal processing method and a data signal processing device, which are characterized in that a first gray control signal is received and transmitted to a data storage processing module; primary color distinguishing processing is carried out on the first gray control signal, and a second gray control signal is obtained; processing the second gray level control signal according to a preset climbing type width modulation allocation rule to generate PDS-PWM processing data; the embodiment of the invention improves the data processing of the PDS-PWM on the basis of the S-PWM, uses a jumping distribution climbing pulse width modulation method, and aims to make up for the defect of low gray scale, and distributes the pulse number to each data period according to regular jumping when the gray scale is extremely low, so that the refreshing frequency is not too slow, the occurrence of the low gray scale time-to-time flashing frequency can be avoided, and the visual softness of the display screen is improved.
Description
Technical Field
The present invention relates to the field of LED technologies, and in particular, to a data signal processing method and a data signal processing device.
Background
The LED full-color display screen is a novel information display medium which is rapidly developed worldwide in the 90 th century, combines the modern high and new technology, and has a series of advantages of energy conservation, environmental protection, bright color, capability of displaying dynamic pictures, characters, wide visible range and the like. The improvement of the gray level is an important index for measuring the display effect of the LED display screen, and the higher the gray level is, the finer and more realistic the color displayed by the LED display screen is. The gray level of the existing LED large-screen display products in the market is generally more than 12bits, a screen with finer display effect is required, and the gray level is more than 16 bits. The 16-bit gray scale of the RGB LED pixel means that each of the red, green and blue LEDs has 16-bit gray scales (16 th power of 2=65536, so that the resulting light palette is clearer and finer.
One of the current common methods of adjusting the gray scale of an LED is pulse width modulation ("PWM"). Briefly, PWM generates a series of voltage pulses to drive an LED. When the pulse voltage is higher than the forward turn-on voltage VF of the LED, the LED is turned on. Otherwise, the LED remains off. Accordingly, when the pulse amplitude exceeds the forward on voltage VF, the pulse duration (i.e., pulse width) of the PWM signal determines the on-time and off-time of the LED. The percentage of the on-time plus the off-time (i.e., PWM period) is the duty cycle of the PWM, which determines the brightness of the LED.
However, the traditional PWM method reaches 16 bits, and more than hundred megabytes of oscillating circuits are needed, which causes difficulty in design. In order to reduce the frequency design of the oscillating circuit, a climbing pulse width modulation (Sramble PWM) S-PWM method appears to generate a gray control signal with high gray level, but the method also has the advantages that because of an average distribution mode, high-bit data of 16-bit data have no data when the gray level is extremely low, one frame refresh rate is changed from a subtle refresh rate to a millisecond refresh rate, the refresh rate is slow, and a stroboscopic phenomenon is brought to eyes, so that the display effect of an LED screen is affected.
Disclosure of Invention
In view of the above problems, embodiments of the present invention have been made to provide a data signal processing method and a data signal processing apparatus that overcome or at least partially solve the above problems.
A first aspect of an embodiment of the present invention provides a data signal processing method, including:
Receiving a first gray control signal and transmitting the gray control signal to the data storage processing module;
Primary color distinguishing processing is carried out on the first gray control signal, and a second gray control signal is obtained;
Processing the second gray level control signal according to a preset climbing type width modulation allocation rule to generate PDS (Pulsate Distribution Scramble-PWM) processing data;
Displaying the PDS-PWM processing data.
Optionally, the method further comprises:
And updating the first gray control signal every preset time period.
Optionally, the PDS-PWM processed data includes at least a first number of bytes of high gray scale bit data and a second number of bytes of low gray scale bit data.
Optionally, the processing the second gray level control signal according to a preset climbing type width modulation allocation rule to generate PDS-PWM processing data includes:
Dividing the high gray level bit data of the second gray level control signal to obtain divided data;
Carrying out recombination processing on the divided data to obtain recombined data;
splitting the low gray level bit data of the second gray level control signal under the condition that the low gray level bit data is 0 to obtain low level data and high level data;
and executing the climbing type width modulation allocation rule on the recombined data according to the low-order data and the high-order data to obtain the PDS-PWM processing data.
Optionally, the splitting the low-gray-scale bit data to obtain low-order data and high-order data includes:
and dividing the low gray level bit data to obtain low 2-bit data and high 4-bit data.
A second aspect of an embodiment of the present invention provides a data signal processing apparatus, the apparatus comprising:
The input end interface module is used for receiving a first gray control signal and transmitting the gray control signal to the data storage processing module;
the data storage processing module is used for carrying out primary color distinguishing processing on the first gray control signal to obtain a second gray control signal;
The PDS-PWM generation module is used for processing the second gray level control signal according to a preset climbing type width modulation distribution rule to generate PDS-PWM processing data, wherein the PDS-PWM processing data at least comprises high gray level bit data of a first byte number and low gray level bit data of a second byte number;
And the output port interface module is used for displaying the PDS-PWM processing data.
Optionally, the data storage processing module is further configured to:
And updating the first gray control signal every preset time period.
Optionally, the PDS-PWM processed data includes at least a first number of bytes of high gray scale bit data and a second number of bytes of low gray scale bit data.
Optionally, the PDS-PWM generation module is configured to:
Dividing the high gray level bit data of the second gray level control signal to obtain divided data;
Carrying out recombination processing on the divided data to obtain recombined data;
splitting the low gray level bit data of the second gray level control signal under the condition that the low gray level bit data is 0 to obtain low level data and high level data;
and executing the climbing type width modulation allocation rule on the recombined data according to the low-order data and the high-order data to obtain the PDS-PWM processing data.
Optionally, the PDS-PWM generation module is configured to:
and dividing the low gray level bit data to obtain low 2-bit data and high 4-bit data.
The embodiment of the invention has the following advantages:
The data signal processing method and the data signal processing device provided by the embodiment of the invention are characterized in that a first gray control signal is received and transmitted to a data storage processing module; primary color distinguishing processing is carried out on the first gray control signal, and a second gray control signal is obtained; processing the second gray level control signal according to a preset climbing type width modulation allocation rule to generate PDS-PWM processing data; the embodiment of the invention improves the data processing of the PDS-PWM on the basis of the S-PWM, uses a jumping distribution climbing pulse width modulation method, and aims to make up for the defect of low gray scale, and distributes the pulse number to each data period according to regular jumping when the gray scale is extremely low, so that the refreshing frequency is not too slow, the occurrence of the low gray scale time-to-time flashing frequency can be avoided, and the visual softness of the display screen is improved.
Drawings
FIG. 1 is a flow chart of an embodiment of a data signal processing method of the present invention;
FIG. 2 is a schematic diagram of an embodiment of a data signal processing system according to the present invention;
FIG. 3 is a schematic diagram showing the distribution of the control gray level 65536 steps of the PDS-PWM mode of the invention;
fig. 4 is a waveform diagram of a gradation climbing type width modulation assignment corresponding to LSB data of PDS-PWM control according to the present invention;
FIG. 5 is a schematic diagram of a gray scale climbing type width modulation distribution circuit for PDS-PWM mode control of the invention;
FIG. 6 is a schematic diagram of a method for splitting gray scale control signals according to the present invention;
FIG. 7 is a waveform simulation diagram illustrating the present invention;
FIG. 8 is a schematic representation of yet another waveform simulation of the present invention;
FIG. 9 is a schematic diagram of a PWM waveform display of the present invention;
FIG. 10 is a schematic diagram of yet another PWM waveform display of the present invention;
FIG. 11 is a diagram illustrating a low-bit significant bit data splitting according to the present invention;
fig. 12 is a flowchart of an embodiment of a data signal processing apparatus according to the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 1, a flow chart of an embodiment of a data signal processing method of the present invention is shown, the method includes:
S101, receiving a first gray control signal and transmitting the gray control signal to a data storage processing module;
s102, primary color distinguishing processing is carried out on the first gray control signal, and a second gray control signal is obtained;
s103, processing the second gray level control signal according to a preset climbing type width modulation allocation rule to generate PDS-PWM processing data;
s104, displaying PDS-PWM processing data.
The embodiment of the invention is particularly applied to a data signal processing system, which comprises an input end interface module, an output end interface module, a PDS-PWM generation module and a data storage processing module, wherein the input end interface module of the system is connected with the data storage processing module, the input end interface module receives an externally transmitted gray control signal and sends the gray control signal to the data storage processing module, and the data storage processing module distributes gray data of the gray control signal into a memory according to a communication protocol, continuously judges whether a new gray control signal is input or not and judges whether the original gray data is changed or not.
The data storage processing module of the system is connected with the PDS-PWM generation module, the data storage processing module sends the gray data in the memory into the PDS-PWM generation module, the PDS-PWM generation module receives the gray data and realizes climbing type width modulation distribution according to the internally designed operation logic, and PDS-PWM is output.
The PDS-PWM generating module of the system is connected with the output interface module and outputs the PDS-PWM to the external display control.
Through PDS-PWM climbing type pulse width modulation, the data refresh rate and the visual update rate are improved, and the LED display screen is better in effect.
The PDS-PWM (Pulsate distribution scramble pulse width modulation) of the PDS-PWM generation module changes the problem of low refresh rate of the traditional PWM when the data with low bit is stored, and realizes higher visual refresh rate. To achieve this, PDS-PWM is divided into 64 parts in the PWM period at the step 65536 of the total gray value, and a plurality of PWM pulses are added, i.e., the on time of the switching device of the external LED display screen is added with a plurality of PWM pulses. In a conventional PWM mode, there may be only one PWM pulse, so the LED will be continuously on for a period of time, and the LED will not be on for the remaining period of time. In contrast, PDS-PWM (allows LEDs to emit light in successive short pulses within a PWM period, such that the light pulses are more regularly and evenly distributed throughout the PWM period, thereby avoiding or reducing flicker.
Optionally, the method further comprises:
The first gray control signal is updated every preset time period.
Optionally, the PDS-PWM processed data includes at least a first number of high gray scale bits and a second number of low gray scale bits.
Optionally, processing the second gray level control signal according to a preset climbing type width modulation allocation rule to generate PDS-PWM processing data, including:
dividing high gray scale bit data of the second gray scale control signal to obtain divided data;
Carrying out recombination processing on the divided data to obtain recombined data;
Splitting the low-gray-scale bit data to obtain low-order data and high-order data under the condition that the low-gray-scale bit data of the second gray-scale control signal is 0;
And executing climbing type width modulation allocation rules on the reconstruction data according to the low-order data and the high-order data to obtain the PDS-PWM processing data.
Optionally, splitting the low-gray-scale bit data to obtain low-order data and high-order data, including:
And dividing the low gray level bit data to obtain low 2-bit data and high 4-bit data.
Specifically, the input end of the PDS-PWM generation module is connected to the output end of the data storage processing module, the gray-scale value of the memory in the data storage processing module is sent to the PDS-PWM generation module, the PDS-PWM generation module receives the gray-scale data and realizes climbing type width modulation distribution according to the internally designed operation logic, the continuous gray-scale control signal with 1024 Clocks (CLK) and high level is repeated 64 times, namely, the gray-scale control signal obtained by the low-bit data (LSB) of 6bits is divided into 64 parts (Count), namely, count=count+1 after 1024 CLK passes, and then the divided 64 parts are distributed into 4 parts for operation, namely, a=0-15, b=16-31, c=32-47 and d=49-63. When the high bit data (MSB) of 10bits of gray data is 0, the low bit data (LSB) of 6bits is in existence, the LSB of 6bits is divided into low 2 bits (L1 and L2) and high 4 bits (H4)), and the distribution number of A, B, C, D parts is logically operated according to the low 2 bits (L1 and L2) and the high 4 bits (H4) of the LSB, so as to realize climbing type width modulation distribution.
The PDS-PWM of the PDS-PWM generation module realizes climbing type width waveform compensation when high bit DATA, namely 10bits of high bit DATA (MSB) exist when gray DATA is higher than 6bits, and PWM_DATA= (10 bits of high DATA) PDSPWM _H+ (6 bits of low DATA) PDSPWM _L; the PWM pulse width waveform with the height of 10bits is compared according to the gray value data stored by 1024 CLK, and when the CLK is full 1024, count2=Count2+1; count2 is used to Count whether the low 6bits of data are compensated, and the compensated PWM pulse width waveform is compensated by distributing the high bit of data to 0. Examples: (lower 6bits data) PDSPWM _l=10; and when the Count2 is smaller than 10, the jumping allocation climbing type width waveform compensation is realized according to the logic operation of the LSB.
The embodiment of the invention is improved on the basis of S-PWM, and a jumping distribution climbing pulse width modulation method (Pulsate Distribution Sramble-PWM) PDS-PWM is used, which is generated for compensating the defect of low gray scale. When the gray level is extremely low, the pulse number is distributed to each data period according to the regular jitter, so that the refreshing frequency is not too slow, the occurrence of the low gray level time-flashing frequency can be avoided, and the visual softness of the display screen is improved.
Fig. 2 is a schematic structural diagram of an embodiment of a data signal processing system according to the present invention, namely, a climbing type pulse width modulation system, which includes an input interface module, an output interface module, a PDS-PWM generating module, and a data storage processing module. The output end of the input end interface module is connected with the input end of the data storage processing module, the output end of the data storage processing module is connected with the input end of the PDS-PWM generating module, and the output end of the PDS-PWM generating module is connected with the input end of the output end interface module. After entering the input interface module, the gray control signal enters the data storage processing module, and in the data storage processing module, gray values of three primary colors (RGB) distinguished by the gray control signal are stored and sent into the PDS-PWM generating module. But at the same time, whether a new gray control signal enters the system is judged, and the stored gray value is changed at any time. The PDS-PWM generating module is a circuit core structure. The input interface module receives the externally transmitted gray control signals and sends the gray control signals to the data storage processing module, the data storage processing module distributes the gray data of the gray control signals into the memory according to the communication protocol, and continuously judges whether new gray control signals are input or not and judges whether the original gray data are changed or not. The data storage processing module sends the gray data in the memory into the PDS-PWM generation module, the PDS-PWM generation module receives the gray data and realizes climbing type width modulation distribution according to the internally designed operation logic to output PDS-PWM.
The pulse duration (i.e., pulse width) of the PWM signal determines the on-time and off-time of the LED. The percentage of on-time that is the sum of on-time and off-time (i.e., PWM period) is the duty cycle, which determines the brightness of the LED. The conventional PWM method is used to generate the gray control signal with such high gray level, so that the LED lamp is in the off state for a long time when the high bit data is 0, which brings the defect of low data refresh rate, and the LED lamp may have a flicker feel to eyes, thereby affecting the display effect of the LED screen. The S-PWM is generated to compensate for the defect, however, when only low-bit data is used, for example, when the gray data of the gray control signal is 0000000000100000, the gray level control signal generated by the S-PWM is almost identical to that generated by the conventional PWM method, the advantages of the S-PWM are not exerted, when the gray data is 0000000000100000, that is, when the low-bit data is used, the S-PWM and the PWM are still the same refresh frequency and display effect, the problem is still not improved, the LED lamp is still in an off state for a long time, the defect that the data refresh rate is low is brought, and the flicker is brought to eyes.
The present application proposes an improved S-PWM called PDS-PWM (Pulsate distribution scramble pulse width modulation) in order to improve this phenomenon. Referring to fig. 3, fig. 3 is a schematic diagram showing the distribution of control gray scale 65536 in PDS-PWM mode. PDS-PWM can split 16bits gray scale data into two parts: high gray scale bit data (MSB) of 10bits and low gray scale bit data (LSB) of 6bits as shown in fig. 6.
The number of high-level clocks included in the gradation control signal generated by the entire PDS-PWM may have 65536 gradation levels (0 to 1023) x (0 to 63) according to gradation data. The sequential gray control signal having a high level of 1024 Clocks (CLK) is repeated 64 times, that is, the gray control signal portion (Count) where LSB is divided into 64 portions is formed, that is, count=count+1 for every 1024 CLK, and then the divided 64 portions are divided into 4 portions to perform the operation, that is, a=0 to 15, b=16 to 31, c=32 to 47, d=49 to 63. When MSB of gray data is 0, the low bit data (LSB) of 6bits is data, and the LSB of 6bits can be divided into low 2 bits (L1 and L2) and high 4 bits (H4), and the distribution number of A, B, C, D four parts is logically operated according to the low 2 bits (L1 and L2) and high 4 bits (H4) of LSB, so as to realize climbing type width modulation distribution.
But the whole PDS-PWM generated gray scale control signal contains clock data to perform jitter distribution instead of average distribution in (0-1023) x (0-63) digital data, i.e., (1024x64) pen data having 65536 gray scales, according to the gray scale data. The gray control signal of high level, i.e., the high 10bits of valid bit data, is repeated 64 times every 1024 clock Cycles (CLK), and the low 6bits of valid bit data are divided into 64 parts denoted by Count, compensating for the total of 64 cycles after every 1024 clock CLK cycles. The jitter distribution mode is used to compensate to the high 10bits of valid bit data, namely every 1024 clock CLK cycles, it can be understood that the PWM waveform of the MSB (10 bits) of the high gray data is processed at 1024CLK, and the PWM waveform of the LSB (6 bits) of the gray data is processed at 64 Count. As shown in fig. 9;
in fig. 9, the PDS-PWM generation module divides the received gray-scale values into two parts for processing: 1. the gray value is lower than 63, LSB 6bits have values, and MSB 10bits are all 0, without high gray values. 2. The gray value is higher than 63, i.e. the MSB 10bits has a value, and the gray value is 10bits higher.
If the gray value is lower than 63, that is, the MSB's are all 0, there is no gray value of 10bits higher. The PDS-PWM generation module distributes low 6bits (LSB) data according to regular jitter distribution, and distributes the number of generated waveforms in 65536 gray scales according to mathematical logic operation. The operation distribution mode is as follows: the Cycle (CLK) is repeated 64 times every 1024 clock cycles, divided into 64Count portions. The four groups a, B, C, D are allocated to be calculated, namely, four parts a=0 to 15, b=16 to 31, c=32 to 47, d=49 to 63, as shown in fig. 10:
the processing operation is as follows: when the high-bit 10 significant bit data is all 0 in the low gray scale data, the low-bit significant bit data of 6bits is split into the low 2bits (L1 and L2) and the high 4bits (H4) for operation when the low-bit significant bit data of 6bits exists, as shown in fig. 11:
The high 4bits data H4 is divided into 16 groups, the data L2 AND L1 are divided into 4 groups in the 16 groups, AND the judgment of the position of the number of the placed pulses is made by the following logic operation, namely A=H2+ (L2|L1), B=H2+L2, C=H2+L2 & L1 AND D=H2, wherein the symbol "=" represents mathematical operation equal to "+" represents mathematical operation addition, the symbol "|" represents logic operation OR (OR), AND the symbol "heat" represents logic operation AND (AND). The operation is used for carrying out logic operation on the number of the pulse for regularly jumping distribution on A, B, C, D groups of time distribution in a time period according to the low 2 bits (L1 and L2) and the high 4bits (H4) of the 6-bit low-bit valid bit data, so that the improved jumping climbing width modulation distribution is realized. The total expression is that PWM waveforms are sent by sequentially climbing from group A to group D, and the numbers of the four groups of distributed pulses of A, B, C and D are sequentially climbing and increasing according to regular jumping distribution, so that jumping distribution climbing pulse width modulation is realized.
The details are shown in Table 1 below: the number of PWM waveforms distributed in the four groups a, B, C, and D is represented by A1, B1, C1, and D1):
TABLE 1
And compares whether PWM output is required in A, B, C, D of four sets of internal allocations, the lower 4 bits of Count are required and compared with A1, B1, C1, D1. Therefore, when count=0 to 15, the lower 4 bits of Count are compared with the a group, that is, the value of A1 is the number of waveforms to be output in the a group. When count=16 to 31, the lower 4 bits of Count are compared with group B, i.e., the value of B1 is the number of waveforms to be output in group B. When count=32 to 47, the lower 4 bits of Count are compared with group C, i.e., the value of C1 is the number of waveforms to be output in group C. When count=48 to 63, the lower 4 bits of Count are compared with the D group, i.e., the value of D1 is the number of waveforms to be output in the D group.
When the gray value is higher than 63, the MSB has a value, i.e. there is a gray value higher by 10 bits. When the gradation data is higher than 6bits, that is, when the high bit data (MSB) of 10bits is the presence of data, then the PDS-PWM value= (high 10bit data) PDSPWM _h+ (low 6bit data) PDSPWM _l; the PWM pulse width waveform with the height of 10bits is compared according to the gray value data stored by 1024 CLK, and when the CLK is full 1024, count2=Count2+1; count2 is used to indicate whether the low 6bits of data are compensated, and the compensated PWM pulse width waveform is compensated by distributing the high bit data to 0. For example: when gray scale (lower 6bits of data) PDSPWM _l=10, count2 will have a climbing type width waveform compensation when less than 10. The specific climbing type width waveform compensation is expressed as follows: after the comparison of the gray value data stored in the PDSPWM _h pulse width waveform according to 1024 CLK is completed, whether the waveform compensation is required or not is judged after PDSPWM _h, and if so, the waveform compensation is performed according to the climbing type width waveform. Otherwise, it is not. For example, when the gradation value is 65, that is, when the gradation data is 0000000001_000001, a1=1, b1=0, c1=0, d1=0 at this time; and the upper 10bits, i.e. MSB, is 1, the waveform is simulated as shown in FIG. 7.
As can be seen in fig. 7, the PWM pulse width waveform of 10bits high, i.e., (high 10bits of data) PDSPWM _h, is compared with the stored gray-scale value data for every 1024 CLK, and then (high 10bits of data) PDSPWM _h is generated, when count=0, i.e., in group a, because gray-scale data is 00000000000001_000001, a1=1, b1=0, c1=0, d1=0; therefore, it is necessary to perform (lower 6-bit data) PDSPWM _l waveform compensation after the PWM pulse width waveform of 10bits higher, that is, (upper 10-bit data) PDSPWM _h.
But because the gradation data is 0000000001_000001, b1=0, c1=0, d1=0; therefore, in count=15 to 63, the PWM pulse width waveform of the upper 10bits, that is, (upper 10bits of data) PDSPWM _h is not compensated by the waveform PDSPWM _l (lower 6 bits of data), and at this time, a Count is taken at will, and the waveform is as shown in fig. 8:
as can be seen from fig. 8, in count=15 to 63, the PWM pulse width waveform of the upper 10bits, that is, (upper 10bits of data) PDSPWM _h is not compensated by the waveform PDSPWM _l (lower 6 bits of data).
Referring to fig. 4, fig. 4 is a waveform diagram of a gray scale climbing type width modulation allocation corresponding to LSB data of PDS-PWM control. The overall expression is that the PWM waveform is sent by sequentially climbing and increasing from the A group to the D group, and the number of the internal pulses of A to D is sequentially climbing and increasing according to the regular jumping distribution, so that the jumping distribution climbing pulse width modulation is realized. As shown in fig. 4, A1, B1, C1, D1 are the number of PWM waveforms internally distributed in a to D; in comparing whether PWM output is required in the split A, B, C, D, the lower 4 bits of Count are compared with A1, B1, C1, D1. Therefore, when count=0 to 15, the lower 4 bits of Count are compared with the a group, that is, the value of A1 is the number of waveforms to be output in the a group. When count=16 to 31, the lower 4 bits of Count are compared with group B, i.e., the value of B1 is the number of waveforms to be output in group B. When count=32 to 47, the lower 4 bits of Count are compared with group C, i.e., the value of C1 is the number of waveforms to be output in group C. When count=48 to 63, the lower 4 bits of Count are compared with the D group, i.e., the value of D1 is the number of waveforms to be output in the D group. In contrast to fig. 2, in the conventional PWM mode, there may be only one PWM pulse, and thus the LED is continuously lit for a period of time, and the LED is not lit for the remaining period of time, as shown in fig. 4. In contrast, PDS-PWM allows LEDs to emit light in successive short pulses within a PWM period, such that the light pulses are more regularly distributed in the PWM period, thereby avoiding or reducing flicker.
PDS-PWM realizes climbing type width waveform compensation when high bit DATA, and PWM_DATA= (10 bits high DATA) PDSPWM _H+ (6 bits low DATA) PDSPWM _L when gray DATA is higher than 6 bits; referring to fig. 5, fig. 5 is a schematic diagram of a gray scale climbing type PWM distribution circuit for PDS-PWM control, in which a PWM pulse width waveform with a height of 10bits is compared with stored gray scale value data based on 1024 CLK. After counting every cnt 10bits, i.e. 1024 CLK s, a cnt up signal is given to the cnt 6bits to prompt count2=count2+1; count2 is used to indicate whether the low 6bits of data are compensated, and the compensated PWM pulse width waveform is compensated by distributing the high bit data to 0. For example: when gray scale (lower 6bits of data) PDSPWM _l=10, count2 will have a climbing type width waveform compensation when less than 10. The specific climbing type width waveform compensation is expressed as follows: after the comparison of the gray value data stored in the PDSPWM _h pulse width waveform according to 1024 CLK is completed, whether the waveform compensation is required or not is judged after PDSPWM _h, and if so, the waveform compensation is performed according to the climbing type width waveform. Otherwise, it is not. For example, when the gradation value is 65, that is, when the gradation data is 0000000001_000001, a1=1, b1=0, c1=0, d1=0 at this time; and the upper 10bits, MSB, is 1. A simulation of the waveform at this time is shown in fig. 7.
As can be seen in fig. 7, the PWM pulse width waveform of 10 bits higher, i.e., (10-bit data) PDSPWM _h, is compared with the stored gray-scale value data for every 1024 CLK, and then (10-bit data) PDSPWM _h is generated, when count=0, i.e., in group a, because gray-scale data is 00000000000001_000001, a1=1, b1=0, c1=0, d1=0; therefore, it is necessary to perform (lower 6-bit data) PDSPWM _l waveform compensation after the PWM pulse width waveform of the upper 10 bits, that is, (upper 10-bit data) PDSPWM _h.
But because the gradation data is 0000000001_000001, b1=0, c1=0, d1=0; therefore, in count=15 to 63, the PWM pulse width waveform PDSPWM _h (high 10 bits of data) of 10 bits is not compensated by PDSPWM _l waveform (low 6 bits of data), and at this time, a Count is arbitrarily taken as shown in fig. 8:
As can be seen from fig. 8 above, in count=15 to 63, the PWM pulse width waveform of the upper 10bits, that is, (upper 10bits of data) PDSPWM _h is not compensated by the waveform PDSPWM _l (lower 6 bits of data).
And to avoid metastable disturbances, the positive edge of the CLK clock is selected for processing and the negative edge is output.
Referring to fig. 12, an embodiment of the present application provides a data signal processing apparatus, which includes:
an input interface module 1201, configured to receive the first gray control signal and transmit the gray control signal to the data storage processing module;
a data storage processing module 1202, configured to perform primary color distinguishing processing on the first gray control signal to obtain a second gray control signal;
The PDS-PWM generating module 1203 is configured to process the second gray scale control signal according to a preset climbing type width modulation allocation rule, and generate PDS-PWM processing data, where the PDS-PWM processing data at least includes high gray scale bit data of the first byte number and low gray scale bit data of the second byte number;
The output interface module 1204 is used for displaying the PDS-PWM processing data.
Optionally, the data storage processing module is further configured to:
The first gray control signal is updated every preset time period.
Optionally, the PDS-PWM processed data includes at least a first number of high gray scale bits and a second number of low gray scale bits.
Optionally, the PDS-PWM generation module is configured to:
dividing high gray scale bit data of the second gray scale control signal to obtain divided data;
Carrying out recombination processing on the divided data to obtain recombined data;
Splitting the low-gray-scale bit data to obtain low-order data and high-order data under the condition that the low-gray-scale bit data of the second gray-scale control signal is 0;
And executing climbing type width modulation allocation rules on the reconstruction data according to the low-order data and the high-order data to obtain the PDS-PWM processing data.
Optionally, the PDS-PWM generation module is configured to:
And dividing the low gray level bit data to obtain low 2-bit data and high 4-bit data.
The data signal processing method and the data signal processing device provided by the embodiment of the invention are characterized in that a first gray control signal is received and transmitted to a data storage processing module; primary color distinguishing processing is carried out on the first gray control signal, and a second gray control signal is obtained; processing the second gray level control signal according to a preset climbing type width modulation allocation rule to generate PDS-PWM processing data; the embodiment of the invention improves the data processing of the PDS-PWM on the basis of the S-PWM, uses a jumping distribution climbing pulse width modulation method, and aims to make up for the defect of low gray scale, and distributes the pulse number to each data period according to regular jumping when the gray scale is extremely low, so that the refreshing frequency is not too slow, the occurrence of the low gray scale time-to-time flashing frequency can be avoided, and the visual softness of the display screen is improved.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, electronic devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing electronic device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing electronic device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or electronic device that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or electronic device. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or electronic device that comprises an element.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (4)
1. A method of data signal processing, the method comprising:
Receiving a first gray control signal and transmitting the gray control signal to a data storage processing module;
Primary color distinguishing processing is carried out on the first gray control signal, and a second gray control signal is obtained;
processing the second gray level control signal according to a preset climbing type width modulation allocation rule to generate PDS-PWM processing data;
displaying the PDS-PWM processing data;
the step of processing the second gray level control signal according to a preset climbing type width modulation allocation rule to generate PDS-PWM processing data comprises the following steps:
the second gray scale control signal is 16-bit gray scale data;
The 16-bit gradation data is divided into two parts: high gray-scale bit data of 10 bits and low gray-scale bit data of 6 bits; the gray control signal obtained by the low bit data of 6 bits is distributed into 4 parts for operation, namely A=0 to 15, B=16 to 31, C=32 to 47 and D=49 to 63; when the 10-bit high-bit data of the gray data are all 0, and the 6-bit low-bit data exist, the 6-bit low-gray-level data are divided into low-2-bit data L1 and L2 and high-4-bit data H4, according to the following logic operation: the pulse number of the A part is H4 < + > (L2L 1), the pulse number of the B part is H4 < + > L2, the pulse number of the C part is H4 < + > L2& L1, the pulse number of the D part is H4, and logic operation is carried out on the distributed pulse number of the A, B, C, D four parts to realize climbing type width modulation distribution.
2. The data signal processing method of claim 1, wherein the method further comprises:
And updating the first gray control signal every preset time period.
3. A data signal processing apparatus, characterized in that the data signal processing apparatus comprises:
The input end interface module is used for receiving the first gray control signal and transmitting the gray control signal to the data storage processing module;
the data storage processing module is used for carrying out primary color distinguishing processing on the first gray control signal to obtain a second gray control signal;
The PDS-PWM generation module is used for processing the second gray level control signal according to a preset climbing type width modulation distribution rule to generate PDS-PWM processing data;
the step of processing the second gray level control signal according to a preset climbing type width modulation allocation rule to generate PDS-PWM processing data comprises the following steps: the second gray scale control signal is 16-bit gray scale data; the 16-bit gradation data is divided into two parts: high gray-scale bit data of 10 bits and low gray-scale bit data of 6 bits; the gray control signal obtained by the low bit data of 6 bits is distributed into 4 parts for operation, namely A=0 to 15, B=16 to 31, C=32 to 47 and D=49 to 63; when the 10-bit high-bit data of the gray data are all 0, and the 6-bit low-bit data exist, the 6-bit low-gray-level data are divided into low-2-bit data L1 and L2 and high-4-bit data H4, according to the following logic operation: the pulse number of the A part is H4 < + > (L2L 1), the pulse number of the B part is H4 < + > L2, the pulse number of the C part is H4 < + > L2& L1, the pulse number of the D part is H4, and logic operation is carried out on the distributed pulse number of the A, B, C, D four parts to realize climbing type width modulation distribution.
4. A data signal processing device according to claim 3, wherein the data storage processing module is further configured to: and updating the first gray control signal every preset time period.
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