Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu LtdfiledCriticalFujitsu Ltd
Priority to JP6366586ApriorityCriticalpatent/JPS62247444A/ja
Publication of JPS62247444ApublicationCriticalpatent/JPS62247444A/ja
Publication of JPH056219B2publicationCriticalpatent/JPH056219B2/ja
G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F13/10—Program control for peripheral devices
G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
System for dynamic association of a variable number of device addresses with input/output devices to allow increased concurrent requests for access to the input/output devices
Adapter for interleaving second data with first data already transferred between first device and second device without having to arbitrate for ownership of communications channel