JPS62247263A - High speed response followup comparison type speed voltage generation circuit - Google Patents

Abstract

PURPOSE:To enable a high speed response even in an increase in the number of bits for a higher accuracy, by providing a comparator which compares a count value outputted from a D flip flop with a count value outputted from a reversible counter and outputs a control signal when the difference between both the count values exceeds a set value. CONSTITUTION:A reversible counter 1 inputs a positive or negative pulse +P or -P outputted from a PG into an up terminal UP and a down terminal DOWN respectively to count through inverters 4 and 5 in parallel with a reversible counter 6 and outputs a count valve N0 counted at each fixed cycle T preset while being cleared. A comparator 3 receives an input of a count value N1 outputted from a D flip flop 2 to compare both the count values N1 and N2 and outputs a signal LOAD to the reversible counter 6 when the difference between both the count values N1 and N2 exceeds a certain set value to replace the count value N2 of the reversible counter 6 with the current count value N1 as measured at this time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an F/V converter that converts an output frequency F of a pulse encoder (hereinafter referred to as PG) into an analog voltage (2) in a servo system or the like.

[Conventional technology]

Conventionally, a small DC generator (tacho generator) was used to detect the rotational speed of a motor, etc., but in order to make the device more compact and cost-effective, the tacho generator was replaced with a tacho generator for position detection. The output pulse of the PG to be used is now converted to voltage by an F/V converter/capacitor.
Since a servo system using a /V converter has a large ripple component in the output voltage at low speeds, it has been considered impossible to use it for NC or the like.

Therefore, the pulses output from the PG are counted by a reversible counter, a reversible pulse rate proportional to the counted value is generated by an integrating means, and the absolute value of the counted value of the two input terminals of the reversible counter is reduced. Patent application No. 59-2707 discloses a circuit that tracks and balances the count value output from a reversible counter by inputting it to the side input terminal, and converts the balanced count value into an analog voltage using a D/A converter.
91 r-Following Comparison Type Speed Voltage Generating Circuit”.

[Problem that the invention seeks to solve]

- In the conventional circuit described above, the pulses from the PG are digitally processed and finally converted to analog voltage by the D/A converter, so pulse ripples at low speeds are not a problem at all, and the output is proportional to the speed. It is now possible to obtain perfect linearity, and the accuracy of temperature drift l- etc. is D
This is due to the characteristics of the /A converter only. However, this circuit has a first-order lag circuit configuration, so accuracy is important! However, when the number of bits is increased to increase the speed, the response becomes poor.

[Means for solving problems]

The high-speed response follow-up comparison type speed voltage generation circuit of the present invention has a PG
It counts up or down the positive direction and negative direction pulses output from and outputs the counted value,
A second reversible counter that is cleared at each set cycle and a count I1 are input from the second reversible counter, and each cycle the current count value is increased by a magnification corresponding to the cycle. The D flip-flop outputs a count equal to the count output by the first reversible counter in steady state, and the count output from the D flip-flop is compared with the count output by the first 117 reversible counter. When the difference between the two counts exceeds a certain set value, the count value of the first reversible counter is
It has a comparator that outputs a control signal to be replaced with the lit value output from the D flip-flop.

[Effect]

In this way, the number of pulses input from the PG is sampled in a fixed time unit by the second counter and the D flip-flop, and the counted value obtained by increasing the sampling value by a certain factor is the first one in the steady state IE. The sampling period is set to be the same as the count value output by the counter, and when the values of both hands are compared and the values of both hands are significantly different, the above-mentioned multiplier is applied to the count value counted by the first counter and the sampled count value. Since it is replaced by the multiplied count value, the response is quick even when the number of bits is increased to improve accuracy.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a fast response follow-up comparison type speed voltage generating circuit of the present invention.

This embodiment includes a reversible counter 1, a D flip-flop 2, a comparator 3, and an inverter 4.5 shown in the dashed line in the circuit of the above-mentioned Japanese Patent Application No. 59-270791 "R-Following Comparison Type Speed Voltage Generation Circuit". This is an additional configuration.

A reversible counter 1 receives pulses +F force direction or negative direction pulses +p and -p outputted from a PG (not shown) in parallel with a reversible counter 6 and connects them to up terminals U through inverters 4.5, respectively.
P is input to the down terminal DOWN for counting, and the counted value No. is output at every preset period T and is cleared. D flip-flop 2 is
The count a value No inputted from the reversible counter l is shifted to a higher position by the digit corresponding to the magnification that makes it equal to the count flfl)h output from the counter 6 in the steady state, and the count value N is obtained.
is outputted every cycle T. Comparator 3 is D
The count value N1 output from the flip-flop 2 is manually input, and the two-hand value Ml * N2 is compared to obtain the two-hand value N,
, When the difference between N2 exceeds a certain set value, a signal LO^D is output to the reversible counter 6 and the count value N? of the reversible counter 6 is output. is replaced with the count value N at that time. The second reverse counter 6 is a reversible counter shown in the above-mentioned Japanese Patent Application No. 59-270791, which counts pulses +p and -p in the positive and negative directions and outputs a count value N2.

In this way, the D flip-flop 2 acts as a kind of frequency counter, and by appropriately selecting the multiplying factor of the period T and the D clip-flop output count value N0, the D flip-flop 2 is generated by multiplying by the multiplying factor in the steady state. It is possible to make the count value N1 and the count value N2 of the reversible counter 6 the same.

For example, in the case of 8-bit configuration, clock pulse CP=5
Positive pulse rate up to 254 for 12KHz
Kpps, and the reversible counter 6 at that time has a count value N
Outputs 2=7F. If the period is T = 8KHz
Then, the output count value No. of the D flip-flop becomes IF, and by shifting this 4 times higher, that is, by 2 bits, the recount value N and count value N2 are compared in the comparator 3, and the PG speed is When the recount value ``I + N2'' exceeds a set value, such as when the number suddenly changes, the signal LOAD is output from the comparator 3 to the reversible counter 6, and the count value No. of the reversible counter 1 becomes 4.
The counted value N2 of the reversible counter 6 is replaced by the multiplied count I1M1. Therefore, a response in 1252 seconds is possible.

On the other hand, in the case of a conventional circuit with an 8-bit configuration, the number of
The response speed was Sec, and the 12-bit configuration was unusable.

〔Effect of the invention〕

Here it is! -As explained in the book-5i! ! The method is to up-count or down-count the positive or negative pulses output from the pulse encoder, respectively. n) Sample the count value at each set period using an inverse counter, D flip-flop, and comparator. Then, multiply this count value by an appropriate multiplier to make it equal to the count value output during normal operation, and then compare the re-count values. If the difference between the 1-car count values increases to a certain value or more, priority is given to sampling count A1. By outputting the same voltage, it is possible to obtain a highly accurate follow-up comparison type speed voltage generating circuit that can respond quickly when the input coverage rate suddenly changes.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a fast response follow-up comparison type speed voltage generating circuit of the present invention. 1.6...Reversible counter, 2...D flip-flop, 3...
·····comparator. 4.5...Inverter, 10P...Positive pulse, -P...Negative pulse, T...Period, LOAD... ·Control signal.

Claims (1)

[Claims] Pulses output from a pulse encoder are counted by a first reversible counter, a reversible pulse rate proportional to the counted value is generated by an integrating means, and two input terminals of the reversible counter are Follow-up comparison type speed that follows and balances the count value output from the reversible counter by inputting the absolute value of the count value to the input terminal on the side that reduces it, and converts the balanced count value into an analog voltage using the D/A converter. In the voltage generation circuit, the positive direction and negative direction pulses output from the pulse encoder are counted up or down respectively to output the counted value, and the second pulse is cleared at every set period.
A reversible counter inputs a count value from a second reversible counter, increases the current count value for each cycle by a multiplier corresponding to the cycle, and calculates the count output from the first reversible counter during steady state. When the D flip-flop outputs a value equal to the numerical value and the count value output from the D flip-flop and the count value output from the first reversible counter, the difference between the two count values exceeds a set value. A high-speed response follow-up comparison type speed voltage generation circuit comprising a comparator that outputs a control signal for replacing the count value of the first reversible counter with the count value output from the D flip-flop.