JPS63170701A - Quick response servo-balacing type speed voltage generating circuit - Google Patents

Abstract

PURPOSE:To quickly respond with a high precision and a high stability by counting pulses outputted from a pulse encoder and a carry signal outputted from an integrating means and loading the operation result of an operating circuit at interval of a certain time. CONSTITUTION:A reversible counter 1 counts positive pulses +P or negative pulses -P outputted form a pulse encoder (PG) and pulses of the carry signal outputted from an ALU 7 and is cleared at every certain period T. A D flip-flop 2 latches the counted value each time to output it as a counted value N1. That is, the counted value N1 is zero when the PG is rotated at a certain speed, and it is outputted as the error to be corrected corresponding to the acceleration when the rotation number of the PG is changed. The counted value N1 is added to a counted value N, which indicates the pulse rate of the PG, outputted from a reversible counter 6 by an ALU 3, and the result is loaded as a counted value N2 to the reversible counter 6 at intervals of the unit time T. Thus, the counted value N outputted from the reversible counter 6 is substituted with the counted value N2 at intervals of the unit time T to resolve the error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an F/V converter that converts an output frequency F of a pulse encoder (hereinafter referred to as PG) into an analog voltage (2) in a servo system or the like.

(Prior art) Conventionally, a speed detection Konashi DC generator (tacho generator) was used to detect the rotational speed of a motor, etc.
In order to downsize the device and increase fI quantification, the output voltage of the PG used for single-position detection is now converted into voltage using an F/V converter instead of the tacho generator. However, since the servo system using the F/V converter has a large ripple component in the output voltage at low speeds, it has been considered impossible to use it for NC or the like.

Therefore, the pulses output from the PG are counted by a reversible counter, a carry signal rate proportional to the counted value is generated by an integrating means, and the absolute value of the counted value is calculated between the two input terminals of the reversible counter. A patent application published in 1973 provides a circuit that tracks and balances the count value output from a reversible counter by inputting it to the input terminal on the decrementing side, and converts the balanced count value into an analog voltage using a D/A converter.
No. 9-270791 "Following comparison type speed voltage generation circuit".

(Problems to be Solved by the Invention) In the conventional circuit described above, the pulse from the PG is digitally processed and finally converted into an analog voltage by the D/A converter, so there is no pulse ripple at low speeds. There is no problem, and it is possible to obtain complete linearity of the output with respect to speed, and the accuracy of temperature drift etc. is better than that of D/A.
This is due to the characteristics of the converter only. However, since this circuit has a first-order lag circuit configuration, it has the disadvantage that increasing the number of bits to improve accuracy results in a loss of responsiveness.

(Means for Solving the Problems) The high-speed response follow-up comparison type speed voltage generating circuit of the present invention includes a frequency dividing means for dividing the frequency of a manually inputted clock signal, and a frequency dividing means for dividing the frequency of a manually inputted clock signal, and a frequency dividing means for dividing the frequency of a manually inputted clock signal, and a second reversible counter that outputs a counted value by up-counting or down-counting the pulse and the carry signal output from the integrating means, and is cleared every cycle of the input frequency dividing means; A D flip-flop that inputs a count value from a reversible counter and outputs the current count value for each cycle, and an arithmetic circuit that adds the count value input from the D flip-flop and the output of the first reversible counter. and counts the pulses output from the pulse encoder and the carry signal output from the integrating means, and is loaded with the calculation results of the calculation circuit every cycle.
It has a reversible counter.

(Function) Therefore, while the PG is operating, the second reversible counter is
The difference between the number of pulses of G and the number of pulses of the carry signal output from the integrating means, that is, the tracking error, is output, and the D flip-flop latches and outputs the tracking error every cycle of the frequency dividing means, and the arithmetic circuit The tracking error is added to the count value output by the reversible counter of 7J1 and output, and the first reversible counter is loaded with the calculation result every cycle of the frequency dividing means, so the speed of the PG changes rapidly. Even when this occurs, the count value output by the first reversible counter can follow the changing speed of the PG at high speed, and is output as an analog output via the D/A converter (Embodiment).Embodiment of the present invention will be explained with reference to the drawings.

Figure 'dS1 is a block diagram showing an embodiment of the high-speed response follow-up comparison type speed voltage generation circuit of the present invention.

This embodiment is based on the circuit shown in FIG. 1 of the above-mentioned Japanese Patent Application No. 59-270791 "Following comparison type speed voltage generation circuit".
This circuit is constructed by adding a reversible counter 1, a D flip-flop 2, AlO2, a frequency divider 4, and an inverter 5 shown within the dotted line.

The frequency divider 4 divides the frequency of the manually inputted clock signal CP by 1/n (n is any positive integer), and the inverter 5 inverts the inputted output of the frequency divider 4. The reversible counter 1 receives ten pulses in the positive or negative direction output from a PG (not shown),
-P and the carry signal output from AlO7 are input in parallel with the counter 6 via the OR circuit 8.9 to the up terminal UP and the down terminal DOWN, respectively, and counted, and the frequency-divided signal manually inputted from the inverter 5 For each cycle T of the input frequency-divided signal, the current count value N0 input from the reversible counter 1 is latched and output. The ALU 3 receives the output of the D flip-flop 2 and the count value N1 output from the reversible counter 6.
Which addition is performed and the count value N2 of the calculation result is output.

Similar to the reversible counter 1, the reversible counter 6 receives positive or negative pulses +p, -p and a carry signal from the ALU 7 via an OR circuit 8.9 to an up terminal U.
P, is input to the down terminal DOWN and counted, and the count value N2 is loaded from the ALU 3 every fixed cycle T of the signal input from the inverter 5. Other circuit configurations are shown in the aforementioned Japanese Patent Application No. 59-270791, and will therefore be omitted.

Next, the operation of this embodiment will be explained.

Similar to the counting operation of the reversible counter 6 explained in Japanese Patent Application No. 59-270791, the reversible counter 1 receives the positive pulse +P or negative pulse -P output from the PG and the carry signal output from the ALU 7. The pulses are counted and cleared every fixed period T. The D flip-flop 2 latches the count value each time the reversible counter 1 is cleared and outputs it as a count value N. In other words, the count value N is the tracking error between the pulse rate output from the PG per unit time T and the carry signal rate output from the ALU 7, and when the PG is rotating at a constant speed, the count value N is calculated. The numerical value N is 0, and when the rotational speed of the PG changes, it is output as an error to be corrected corresponding to the acceleration/deceleration.

The count value N is calculated by adding the PG pulse rate output from the reversible counter 6 to the hail count value N by the ALU 3,
The count value N2 is loaded into the reversible counter 6 every writing time T. Therefore, the count value N output by the reversible counter 6 is replaced by the count value N2 every unit time T, and the error is eliminated. The output N of the reversible counter 6 can be made to follow changes in the speed of the PG at a high speed that cannot be obtained by counting operations. Of course, when the speed of the PG is constant, the output count value N of the D flip-flop 2 is O, so the reversible counter 6 stably outputs the count value N corresponding to the steady speed of the PG.

The output count value N of the reversible counter 6 is the output count value N of the reversible counter 6.
0 to the outside as an analog output corresponding to the speed of the PG.

〔Effect of the invention〕

As explained above, in the present invention, the pulses input from the PG and the pulses input from the integrating means are counted by the second reversible counter, and the tracking error with respect to the speed of the PG is calculated at regular intervals using a D flip-flop. Take it out as the first
By adding the output of the reversible counter using an arithmetic circuit and replacing the output of the first reversible counter with the added value, the output of the first reversible counter is changed every fixed period by the error during that period. This modification has the effect of providing a highly accurate and highly stable F/V converter that can respond quickly even when the speed of the PG changes rapidly or when the number of bits of the processed signal is large.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a high-speed response follow-up comparison type speed voltage generation circuit of the present invention. 1・・・・・・・・・・・・Reversible counter, 2-
−−−−−−−−−−−−− D flip-flop, 3
・・・・・・・・・・・・・-ALU. 4・・・・・・・・・・・・・・・ Frequency divider, 5---
−−・・・・・・・Inverter, 6−−−−−−−
−−・・・・・・Reversible counter, 7−−−−−・−−−
--------A L U, 8, 9---------
OR circuit, 10----------------------D
/ A converter, +p, -p...Encoder output pulse, CP-...Clock signal.

Claims (1)

[Claims] Pulses output from a pulse encoder are counted by a first reversible counter, and a carry signal rate proportional to the counted value is generated by an integrating means, and the pulses are applied to two inputs of the reversible counter. Tracking comparison in which the counted value output from the reversible counter is tracked and balanced by inputting it to the input terminal on the side that reduces the absolute value of the counted value, and the balanced counted value is converted into an analog voltage by the D/A converter. In the type speed voltage generation circuit, a frequency dividing means divides the input clock signal, positive direction pulses output from the pulse encoder, negative direction pulses output from the pulse encoder, and a carry signal output from the integrating means are respectively up-counted or The second counter counts down and outputs the counted value, and is cleared every cycle of the input frequency dividing means.
a reversible counter, a D flip-flop that inputs the count value from the second reversible counter and outputs the count value at that time for each cycle; a count value input from the D flip-flop;
the first reversible counter counts the pulses output from the pulse encoder and the carry signal output from the integrating means, and adds the output of the reversible counter at each cycle. A high-speed response follow-up comparison type speed voltage generation circuit characterized by being loaded with the calculation results of the circuit.