JPH0551104B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for controlling the output frequency F of a pulse encoder (hereinafter referred to as PG) in a servo system, etc.
This invention relates to an F/V converter that converts a voltage into an analog voltage V.

[Conventional technology]

Conventionally, a small DC generator for speed detection (tachogenerator) was used to detect the rotational speed of a motor, etc., but in order to make the device smaller and lighter, the PG output pulse used for position detection was replaced with a tachometer generator. is now converted to voltage using an F/V converter. However, a servo system using an F/V converter had a large ripple component in the output voltage at low speeds, so it was considered impossible to use it for NC, etc.

Therefore, the pulses output from the PG are counted by a reversible counter, a reversible pulse rate proportional to the counted value is generated by an integrating means, and the side that reduces the absolute value of the counted value of the two input terminals of the reversible counter A circuit that follows and balances the count value output from a reversible counter by inputting it to the input terminal of , and converts the balanced count value into an analog voltage using a D/A converter is disclosed in Japanese Patent Application No. 59-270791 ``Following Comparison Type''. "Speed Voltage Generating Circuit".

[Problem that the invention seeks to solve]

In the conventional circuit described above, the pulses from the PG are digitally processed and finally converted to analog voltage by the D/A converter, so pulse ripples at low speeds are not a problem at all, and the output is low relative to the speed. It is now possible to obtain perfect linearity, and the accuracy of temperature drift, etc. depends only on the characteristics of the D/A converter. However, since this circuit has a first-order lag circuit configuration, increasing the number of bits to improve accuracy has the disadvantage that responsiveness deteriorates.

[Means for solving problems]

The high-speed response follow-up comparison type speed voltage generation circuit of the present invention counts up or down the positive direction and negative direction pulses output from the PG, outputs a counted value, and clears the counted value at every set cycle. a second reversible counter; a count value is inputted from the second reversible counter, and the current count value is increased for each cycle by a multiplier corresponding to the cycle, and the output of the first reversible counter during steady state; The D flip-flop outputs a count equal to the count value, and the count output from the D flip-flop is compared with the count output from the first reversible counter, and when the difference between the two count values exceeds a set value, the It has a comparator that outputs a control signal to replace the count value of the reversible counter No. 1 with the count value output from the D flip-flop.

[Effect]

In this way, the number of pulses input from the PG is sampled in a fixed time unit by the second counter and the D flip-flop, and the counted value obtained by increasing the sampling value by a certain factor is the number of pulses input from the first counter in a steady state. The sampling period is set so that it is the same as the output count value, and when the two count values are compared and the two count values are significantly different, the first
Since the counted value counted by the counter is replaced with the counted value obtained by multiplying the sampled calculated value by the multiplication factor, the response becomes quick even when the number of bits is increased to improve accuracy.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a high-speed response follow-up comparison type speed voltage generating circuit according to the present invention.

This embodiment is based on the circuit of the above-mentioned Japanese Patent Application No. 59-277091 "Follow-up Comparison Type Speed Voltage Generating Circuit" with a reversible counter 1 shown within the dashed line and a D flip-flop 2.
It is constructed by adding a comparator 3 and inverters 4 and 5.

The reversible counter 1 inputs positive or negative pulses +P and -P output from a PG (not shown) in parallel with the reversible counter 6 to the up terminal UP and down terminal DOWN via inverters 4 and 5, respectively. It counts, and outputs the counted value N ₀ at every preset constant period T, and is also cleared. The D flip-flop 2 shifts the count value N ₀ inputted from the reversible counter 1 to a higher position by a digit corresponding to the magnification that makes it equal to the count value N ₂ output from the counter 6 in the steady state, and converts it to the count value N _{1 .}
is outputted every cycle T. Comparator 3
is the count value output from D flip-flop 2
When N ₁ is input and both count values N ₁ and N ₂ are compared, and the difference between both count values N ₁ and N ₂ exceeds a set value, a signal LOAD is output to the reversible counter 6 and the reversible counter 6 Replace the count value N ₂ with the count value N ₁ at that time. The reversible counter 6 is a reversible counter shown in the above-mentioned Japanese Patent Application No. 59-270791.
Count P and -P and output the count value _N2 .

In this way, the D flip-flop 2 acts as a kind of frequency counter, and by appropriately selecting the period T and the multiplying factor of the D flip-flop output count value _N0 , a calculation is generated by multiplying the multiplying factor in the steady state. Numeric value N ₁ and count value of reversible counter 6
It is possible to make N ₂ the same.

For example, in the case of an 8-bit configuration, the clock pulse
The pulse rate in the positive direction for CP=512KHz is a maximum of 254Kpps, and the reversible counter 6 at that time outputs a count value N ₂ =7F. If the period is T8KHz
Then, the output count value N ₀ of the D flip-flop is
1F, by multiplying this by 4 times, that is, by shifting it upwards by 2 bits, both count values _N1 and _N2 are compared by comparator 3, and both count values are changed as in the case where the speed of PG suddenly changes. When the difference between N ₁ and N ₂ exceeds a certain set value, the signal LOAD is output from the comparator 3 to the reversible counter 6,
Count value N ₀ of reversible counter 1 is multiplied by 4
The count value _N2 of the reversible counter 6 is replaced by _N1 .
Therefore, response time of 125 μsec is possible. On the other hand, in the case of a conventional circuit with an 8-bit configuration, the number of
The response speed was msec, and the 12-bit configuration was unusable.

〔Effect of the invention〕

As explained above, the present invention uses a reversible counter that counts up or down, respectively, pulses in the positive direction or negative direction output from a pulse encoder, a D flip-flop, and a comparator to count the pulses at each set period. Sample a numerical value, multiply this counted value by an appropriate multiplier to make it equal to the counted value output during steady state, compare both counted values, and when the difference between both counted values is expanded to a certain value or more, the sampling counted value By preferentially outputting the following, it is possible to obtain a highly accurate follow-up comparison type speed voltage generating circuit that can respond quickly when the input pulse rate suddenly changes.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a fast response follow-up comparison type speed voltage generating circuit according to the present invention. 1, 6... Reversible counter, 2... D flip-flop, 3... Comparator, 4, 5... Inverter, +P... Positive direction pulse, -P... Negative direction pulse, T... Period, LOAD... Control signal.

Claims (1)

[Claims] 1. Pulses output from a pulse encoder are counted by a first reversible counter, a reversible pulse rate proportional to the counted value is generated by an integrating means, and two input terminals of the reversible counter are connected to each other. Follow-up comparison type speed that follows and balances the count value output from the reversible counter by inputting the absolute value of the count value to the input terminal on the side to be reduced, and converts the balanced count value into an analog voltage using the D/A converter. In the voltage generation circuit, a second reversible counter outputs a counted value by up-counting or down-counting the positive direction and negative direction pulses outputted from the pulse encoder, and is cleared at every set cycle; The count value is inputted from the reversible counter of the first reversible counter, and the count value at that time is increased by a multiplier corresponding to the cycle for each cycle, and outputted by making it equal to the count value output by the first reversible counter in a steady state. Compare the count value output from the D flip-flop and the count value output from the first reversible counter,
A high-speed response follow-up comparison type characterized by having a comparator that outputs a control signal to replace the count value of the first reversible counter with the count value output from the D flip-flop when the difference between the two count values exceeds a set value. Speed voltage generation circuit.