JPS62244174A - Output device for change transfer device - Google Patents

Abstract

PURPOSE:To operate an FET at an arbitrary operation point by forming the gate region of an initial stage FET of an amplifier as a common floating diffusion region of either one of source and drain of a reset FET and forming a control electrode through an insulating layer on a gate region. CONSTITUTION:An amplifier which inputs and amplifies a signal charge trans ferred from a charge transfer element 10 from the gate 22 of an initial stage FET 3 to output it, and a reset FET 2 for sweeping out the remaining charge on the region 22 of the FET 3 are provided. In the output device of such a charge transfer element, the region 22 of the FET 3 is used as a common float ing diffusion region of either one of source and drain of the FET 2. Further, a control electrode 34 is formed through an insulating layer 24 on the gate region, a voltage to be applied to the electrode 34 is selected to set the opera tion point of the FET 3. The FET 3 is, for example, composed of a P<+> type region 30, an N-type region 22 and a p-type substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output device for a charge transfer device, and more particularly to an output device for a charge transfer device that can set the potential of the gate of a first stage transistor to the optimal operating point of the transistor.

Kei Higemi 1 In the output device of a charge transfer device, the final stage of the CCD transfer channel is connected to the gate of the first stage FET of the output amplifier, and a reset FET is provided for resetting. is connected to the gate of the first stage FET of the output amplifier.

The potential when there is no charge in the gate portion of the first-stage FET of the output amplifier is determined by manufacturing conditions such as the shape, concentration, and junction depth of the gate portion that are set when the gate portion is manufactured. Therefore, since the created gate part has a constant potential when there is no charge, the operating point of the first stage FET is determined by this, and the operating point of the first stage FET is determined according to the amount of signal charge transferred by the CCD and sent to the gate of the first stage FET. The outputs output from the output amplifier are set in a predetermined relationship, and this relationship cannot be changed.

For example, if the potential of a gate is set in such a way that an output is obtained only when a certain amount of charge is accumulated in the gate, then even if you try to set the relationship such that an output is obtained when even a small amount of charge is accumulated in the gate, , since the potential of the uncharged gate is assumed to be constant, it cannot be changed. Therefore, since the operating point of the transistor cannot be changed, it is necessary to manufacture the gate portion so that it operates at the optimum operating point. However, since the manufacturing conditions for the gate portion to achieve the optimum operating point of such a transistor have a very narrow tolerance range, it has been difficult to manufacture a gate portion that satisfies the conditions.

In addition, when applying a voltage for resetting to the gate of the reset FET and discharging the charge M accumulated at the gate of the first stage FET through the reset FET,
Depending on the potential determined at the time of fabrication of the gate portion of the ET, it is difficult to discharge charges, resulting in a drawback that a complete reset cannot be performed.

OBJECTS It is an object of the present invention to provide an output device for a charge transfer device that eliminates the drawbacks of the prior art and allows an FET to operate at an arbitrary operating point.

According to the present invention, a signal charge transferred from a charge transfer element is input from the gate of a first-stage FET, and an amplifier that amplifies and outputs the signal charge is input to the first-stage FET of the amplifier when no charge is transferred from the charge transfer element. An output device for a charge transfer element has a reset FET for sweeping out charges remaining in the gate region of the amplifier. At the same time,
By providing a control electrode in the gate region through an insulating layer and selecting the voltage applied to the control electrode, the first stage F of the amplifier
This is to set the operating point of ET.

DESCRIPTION OF EMBODIMENTS Next, embodiments of an output device for a charge transfer device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows a circuit of an embodiment of the output device of the charge transfer device according to the present invention, and FIG. 1(a) is a plan view of the device within the dotted line in FIG. ) is shown in FIG. 1(b).

An n◆ region 2o is formed on the surface of the p-type silicon substrate 1, and a p10 region 3o is formed at a distance from the total region 20. An n region 22 is formed around the p◆ region. A gate electrode 26 is formed on the substrate surface between the n+ region 20 and the n region 22 with an insulating layer 24 interposed therebetween, and the n◆ region 2
0, n region 22. The gate electrode 28 constitutes the reset FET 2 shown in FIG. The n+ region 2° is the drain of the reset FET 2, and is connected to the power supply VDD through an aluminum electrode.

In addition, the p◆ region 30, the n region 22, and the p substrate 1 provide a second
The FET 3 shown in the figure is configured. In addition, FET3
may be either a junction FET (JFET) or a static induction transistor. In this specification, the term FET is used to include SIT.

The p-domain region 30 is the drain of the FET 3 and is connected to the power source -VDD via a resistor R by an aluminum electrode 32 and to the gate of the FET 4.

The n region 22 is the gate of FET 3 and is the gate of reset FE.
This is common to the source of T2. The n region 22 is a floating diffusion region. A control electrode 34 made of polysilicon or the like is provided on this n-region 22 via an insulating layer 24.
is provided. A control electrode 34 is provided for selecting the operating point of the FET 3 by adjusting the applied voltage. The source of the FET 3 is the p-substrate 1, and the p-substrate 1 is grounded.

Further, a buried n-channel 12 is formed on the surface of the substrate l, and a plurality of electrodes 16 made of polysilicon or the like provided on the upper surface of the n-channel 12 via an insulating layer 14 are used as drive electrodes for transfer. 10 are configured. c.
The n-channel 12 of cn to is connected to the n-region 22, which is the gate of FET 3. In Figure 2, c
The signal charge from cn io is transferred from input terminal 6 to FET 3
input into the gate.

The n region 22, which is the gate of the FET 3, is doped with n-type impurities at a concentration of 1!10 to 1xlO18/cm3. Preferably, B is introduced so that 5 to 10 to Q, 5!1018/c-, is depleted.

In addition, the gate electrode 26 and the electrode 16 are connected to the insulating layer 1 of PSG.
8.

In FIG. 2, the drain of FET 4 is connected to the power supply VDD, and the source of FET 4 is connected to output terminal 8 and to the drain of FET 5.
The gate and source of FET 5 are short-circuited so that it functions as a resistor.

Note that each of the above FETs may be of a different conductivity type, or the source and drain may be reversed.

Next, the operation will be explained using the timing chart shown in FIG.

Signal charges are transferred within the n-channel 12 of the CCD 10 by applying a voltage to the drive electrode 16.

(C:I) When the clock pulse shown in FIG. 4(a) applied to the final stage drive electrode 16 of 10 is at a high level, it is accumulated in the n channel 12 below the final stage drive electrode 16, and the clock pulse becomes low. When the signal reaches the level, it is transferred to the n region 22 which is the gate of FET 3. That is, it is accumulated in the n9R region 22 which is the gate of FET 3 from the input terminal B in FIG.

As a result, the potential of n-region 22 changes, and the voltage applied to the gate of FET 3 changes, so the drain current of FET 3 changes, and in response to this change, a voltage drop occurs due to resistor R, and the potential of point 101 changes. changes. This point 10
When a change in potential of 1 is applied to the gate of FET 4,
Accordingly, the drain current of FET4 changes, and the FET
5 acts as a resistor, the potential at point 102 changes,
This potential change is output from the output terminal 8.

Next, the reset by the reset FET 2 will be explained.

When the clock pulse applied to the final stage drive electrode 16 of the COD 10 in FIG. 4(a) is at a high level and a little before changing to a low level, the reset pulse in FIG. 4(b) is at a high level. level, and is applied to the gate of the reset FET 2 from the terminal 201. Then, reset F
ET 2 becomes conductive, and the charge remaining in the n-region 22, which is the source of the reset FET 2 and the gate of the FET 3, flows to the power supply vDD through the reset FET 2, and the electrons in the n-region 22 are swept out and reset. .

Here, as shown in FIG. 4(C), the FET applied to the electrode
The gate control pulse No. 3 and the change in the potential of the n-region 22, which is the gate portion of the FET 3, will be explained.

The fourth signal applied from the gate control terminal 7 in FIG.
The gate control pulse in figure (C) is as shown in figure 4 (b).
A reset pulse is applied to the gate of reset FET2 at terminal 2.
01 to the low level V approximately corresponding to the time when it is applied.
gL, and when the clock pulse of FIG. 4(a) applied to the final stage drive electrode IB of the COD 10 becomes low level, it becomes VgH, which is high level. That is, the gate control pulse becomes a low level VgL when the reset FET 2 is reset, and becomes a high level VgH when the charge transferred from the COD 10 is applied to the gate of the FET 3 and a signal is read out.

The potential of n-region 22, which is the gate portion of FET 3, is shown in FIG. In the figure, DOx indicates the thickness of the insulating layer 14 at the gate portion sandwiched between the n region 22 and the control electrode 34.

As shown in the figure, when the gate control pulse is at the low level VgL, the potential 303 of the n region 22 which is the gate portion of the FET 3 is small, and when the gate control pulse is at the high level VgH, the potential 301 of the n region 22 is small. growing. When reading signal charges, a gate control pulse of VgH is applied to increase the potential of the gate portion so that signal charges are easily accumulated in the gate portion. on the other hand,
When resetting using the reset FET 2, the potential of the gate portion is made small to make it easier for signal charges to be discharged from the gate portion.

Note that when the charge is transferred to the n-region 22 and accumulated when reading the signal charge, the potential of the n-region 22 becomes the potential shown in 301 when there is no charge in the n-region 22, as shown in 302 in FIG. 3. becomes smaller compared to

In FIG. 5, the gate control pulse Vg is increased in the order of graphs 501, 502, 503, and 504 showing the relationship between the amount of charge and the output of the output circuit according to the gate control pulse Vgc7)&.

As can be seen from the figure, the gate control pulse Vg
If , the output becomes smaller even if the amount of charge transferred from the CCD 10 to the n region 22 is the same.

As can be seen from FIGS. 4 and 5, the potential of the n-region 22 is changed by changing the gate control pulse Vg applied to the control electrode 34 above the n-region 22, which is the gate portion of the FET 3, to 'a'. This allows the output to be changed depending on the amount of charge transferred to the n-region 22. That is, by selecting the gate control pulse V8, the FET
3 and FET 4 can be operated at their optimum operating points.

For example, the gate control pulse Vg is set to 50 in FIG.
If set to the value shown in 2, there will be no output when there is no signal charge, and an output will be obtained when a small amount of signal charge is generated, which is preferable as the operating point of FET 3.Also, gate control pulse Vg 503 in all 85 diagrams, If set to 504, an output is obtained only when a certain amount of signal charge is generated. Conversely, if the gate control pulse Vg is set to 501, an output can be obtained even when there is no charge.

Since the potential of the n-region 22 in the gate part of the conventional FET 3 is determined by the conditions set at the time of fabrication such as its shape, concentration, junction depth, etc., the operating point of the FET 3 is fixed, as shown in Fig. 5. However, it was not possible to operate at the optimal operating point by changing the operating point. Therefore, when creating the n-region 22 which is the gate part, the n-region 22 is
It is necessary to set the potential of n region 2
It was extremely difficult to fabricate the n-region 22 so that the potential of 2 could be set to a predetermined value.

According to this embodiment, the n region 22 which is the gate of the FET 3
By applying a gate control pulse Vg to the control electrode 34 provided through the insulating layer 14, the potential of the n-region 22, which is the gate, can be changed, so that the FET 3 can be operated at the optimal operating point. be able to. Therefore, the allowable range of manufacturing conditions when manufacturing n-region 22 can be increased.

Further, by setting the gate control pulse Vg to a low level when resetting by the reset FE 72, the charges accumulated in the n-region 22 can be easily discharged. The permissible range of the reset pulse applied to the gate can be increased.

Moreover, since the floating diffusion region of the n region 22 has a low impurity concentration, it can be completely depleted by the reset by the reset FE↑2, and no charge remains.

Therefore, after resetting the reset FET 2, a certain amount of charge remains in the n region 22 each time, and this does not cause reset noise.

In the above embodiment, the channel of the CCD is an n-channel, and the gate of the FET is an n-region, but they may be of different conductivity types.

Effects According to the present invention, since the gate electrode is provided in the gate region of the first stage FET of the output device via the insulating layer, the potential of the gate region can be changed by selecting the voltage to be applied to the gate electrode. This allows the FET to operate at its optimum operating point. Therefore, the allowable range of manufacturing conditions when manufacturing the gate region can be increased.

[Brief explanation of drawings]

Figure 1 (a) is a plan view showing the dotted line part in Figure 2;
b) is a cross-sectional view taken along the line I--I in FIG. ) is a diagram showing the relationship between the potential of the n-region 22 and the voltage applied to the electrode 34. FIG. 4 is a timing chart showing the operation of the device shown in FIG. 1, and FIG. 5 is a diagram showing the relationship between the amount and output of charges accumulated in the n-region 22 of FIG. 1. Explanation of symbols of main parts 180. Substrate 210. Reset FET 3, , FET 601. Input terminals to, , , cc. 12, , n channel 14, , insulating layer 1B, , electrode 20, , n+ region 2, , n region 24, , insulating layer 2f3. ,,gate electrode 30,,,P+ region 34,,,control electrode book l! l] Skin 2 Design 3 Figure

Claims (1)

[Claims] 1. The signal charge transferred from the charge transfer element is transferred to the first stage FET.
An output of a charge transfer element comprising: an amplifier that receives input from the gate of the charge transfer element, amplifies and outputs the output; and a reset FET for sweeping out charges remaining in a first stage FET gate region of the amplifier when no charge is transferred from the charge transfer element. In the device, the gate region of the first-stage FET of the amplifier is a floating diffusion region common to one of the source and drain of the reset FET, and a control electrode is provided in the gate region via an insulating layer. An output device for a charge transfer element, characterized in that an operating point of a first stage FET of the amplifier is set by selecting a voltage applied to the control electrode. 2. In the device according to claim 1, when the charge remaining in the gate region of the first stage FET of the amplifier is swept out by the reset FET, the voltage applied to the control electrode is set to a value different from that when reading the signal. 1. An output device for a charge transfer element, characterized in that charge remaining in the gate region can be easily swept out by changing the amount of charge. 3. An output device for a charge transfer element according to claim 1 or 2, wherein the first stage FET is a junction FET. 4. An output device for a charge transfer element according to claim 1 or 2, wherein the first stage FET is a static induction transistor.