JP2669009B2 - Voltage comparison circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage comparison circuit used in an analog-to-digital conversion circuit and the like, and more particularly to a voltage comparison circuit having a structure in which an output voltage can be obtained from an impurity diffusion region.

[Summary of the Invention]

The present invention provides a voltage comparison circuit that compares a voltage difference between a signal voltage and a reference voltage, a potential difference conversion unit that converts a potential difference between the two voltages into a signal charge, and a signal charge transferred from the potential difference conversion unit to the impurity diffusion region. By comprising output means for outputting a corresponding signal, and reset means for resetting at least the signal charge of the impurity diffusion region,
The number of elements is reduced, the circuit size is reduced, and the through current is reduced.

[Conventional technology]

Generally, in an analog / digital conversion circuit and other various electronic circuits, a voltage comparison circuit is provided which compares the input signal voltage Vsig with a reference reference voltage Vref and outputs an output voltage Vout according to the comparison result. To be

FIG. 19 shows an example of a conventional voltage comparison circuit, which has a CMOS configuration. The signal voltage Vsig is input from the input terminal 101, and the reference voltage Vref is input from the input terminal 102. Each input terminal 10
1, 102 are respectively connected to the capacitor 105 via the switch 103104. The other end of the capacitor 105 is connected to the input side of the CMOS inverter 106, and the CMOS inverter 106 is connected to the CMOS inverter 108 via the capacitor 107. A reset switch 109 is also provided in a loop that short-circuits the input / output terminals of the CMOS inverters 106 and 108.

In this voltage comparison circuit, the signal voltage Vsig and the reference voltage Vref are sequentially supplied to one end of the capacitor 105 by opening and closing the switches 103 and 104, and the potential difference operates the CMOS inverter 106. The output from the CMOS inverter 106 drives the CMOS inverter 108 to obtain the output voltage Vout.

[Problems to be solved by the invention]

However, such a voltage comparison circuit has a problem that a through current and a circuit scale increase.

That is, as shown in FIG. 19, CMOS inverters 106 and 108 are used to amplify the potential difference, and at the time of output inversion, a through current flows from the power supply voltage V _DD toward the ground voltage GND, resulting in power consumption. The amount increases. Especially
When many CMOS inverters are arranged in series, the power consumption increases.

Also, in order to obtain sufficient sensitivity, it is necessary to increase the number of CMOS inverters and the size of the capacitor, but doing so increases the circuit scale and the number of elements and the area of the elements. Will increase.

Accordingly, an object of the present invention is to provide a voltage comparison circuit that prevents a through current and does not increase the circuit scale.

[Means for solving the problem]

In order to achieve the above object, a voltage comparison circuit according to the present invention has a first field-effect transistor in which a signal voltage is input to a gate, and one of the source and the drain is common to the first field-effect transistor. A second field effect transistor and a switching circuit that switches between a reference voltage and a ground voltage and supplies the voltage to the gate of the second field effect transistor, and the switching circuit connects the gate of the second field effect transistor to the ground voltage. And the first field-effect transistor accumulates charges according to the signal voltage in the source / drain common to the second field-effect transistor, and the switching circuit causes the gate of the second field-effect transistor to A reference voltage is supplied, a potential difference between the signal voltage and the reference voltage is converted into a signal charge, and the signal charge is converted into the first field effect transistor. Potential difference converting means for transferring to the impurity diffusion region which is one of the source and drain of the second field effect transistor which cannot be shared; and outputting a signal corresponding to the signal charge transferred from the potential difference converting means to the impurity diffusion region. Output means and reset means for resetting at least signal charges in the impurity diffusion region before the potential difference converting means converts a potential difference between the signal voltage and the reference voltage into signal charges.

In the voltage comparison circuit of the present invention, the switching means for switching between the signal voltage and the reference voltage, and the signal voltage or the reference voltage switched by the switching means are input to the gate.
And one source / drain is common to both the source / drain of the first field effect transistor, and a second voltage is applied to the gate of the second transistor.
And one of the sources and drains of the second field-effect transistor is not common with the first field-effect transistor of the second field-effect transistor, and the other source and drain has a gate of the second field-effect transistor. A third field effect transistor having a gate input with a voltage higher than the voltage input to the second field effect transistor and a reset signal having a voltage higher than the voltage input to the other source / drain; And output means for outputting a signal corresponding to the signal charge of the common source / drain of the third field-effect transistor, wherein the switching means inputs a signal voltage to the gate of the first field-effect transistor, The third field effect transistor is configured to receive both source signals of the first field effect transistor based on the reset signal. Transfers signal charges in said third
The field-effect transistor resets a signal charge of a common source / drain of the second field-effect transistor and the third field-effect transistor based on the reset signal, and the switching means controls a gate of the first field-effect transistor. And the first field-effect transistor converts a potential difference between the signal voltage and the reference voltage into a signal charge, so that the second field-effect transistor and the third field-effect transistor have a common potential. It is characterized in that the signal is transferred to the source / drain, and the output means outputs a signal corresponding to the signal charge of the common source / drain of the second field effect transistor and the third field effect transistor.

[Action]

In the voltage comparison circuit of the present invention, the switching circuit of the potential difference conversion means switches between the ground voltage and the reference voltage supplied to the gate of the second field effect transistor. The potential difference converting means converts a potential difference between the signal voltage and the reference voltage into a signal charge based on the switching operation of the switching circuit, and transfers the signal charge to the impurity diffusion region of the second field effect transistor. Then, the output means extracts the voltage corresponding to the signal charge and obtains the output voltage.

Further, in the voltage comparison circuit of the present invention, the charge corresponding to the reset signal input to the gate of the third field effect transistor is transferred to the source / drain of the first field effect transistor. The switching means switches between a reference voltage and a signal voltage input to the gate of the first field effect transistor. Based on the switching operation of the switching means, a signal charge corresponding to the potential difference between the reference voltage and the signal voltage is transferred to the source / drain of the second field effect transistor. Then, the output means extracts the voltage corresponding to the potential difference and obtains the output voltage.

Embodiment A preferred embodiment of the present invention will be described with reference to the drawings.

First Embodiment This embodiment is an example having a potential difference conversion means in which the signal voltage Vsig and the reference voltage Vref are input to separate field effect transistors.

First, the circuit configuration is as shown in FIG. An nMOS transistor 1 is provided as a first field effect transistor whose signal voltage Vsig is input to the gate 1g. One source / drain of the nMOS transistor 1 is provided.
The signal Φ ₁ is supplied to 1sd. The other source / drain 6 of the nMOS transistor 1 has a capacitance 8 equivalently to the substrate, and the source / drain 6 is a source / drain common to the nMOS transistor 2 as a second field effect transistor. Has become. The reference voltage Vref is supplied to the two gates 2g of the nMOS transistor. The other source / drain 7 of the nMOS transistor 2 has a capacitance 9 with the substrate and serves as one source / drain of the transfer gate 3. The potential difference converting means is composed of the nMOS transistor 1 and the nMOS transistor 2 and generates a signal charge according to the signal voltage Vsig and the reference voltage Vref. The signal charge is supplied with the transfer pulse signal Φ _2. Forwarded over.

The other source / drain 5 of the transfer gate 3 functions as a floating diffusion region formed of an impurity diffusion region, and is used as an output unit for performing output according to a signal charge. The source / drain 5 also has a capacitance 10 equivalently to the substrate, and is further connected to an output buffer 11. The source / drain 5 is also one of the source / drain of the reset nMOS transistor 4, and the other source / drain 4sd of the nMOS transistor 4 is supplied with the power supply voltage _VDD . The reset signal Φ ₃ is supplied to the gate 4g of the nMOS transistor 4.

The voltage comparison circuit having such a circuit configuration can take a cross-sectional structure of a chip as shown in FIG. 2, for example. P
An N ⁺ type impurity diffusion region is formed facing the surface of the type silicon substrate 12. With this N ⁺ type impurity diffusion region, nM
Source / drains 1sd and 6 of the OS transistors 1 and 2, a source / drain 5 functioning as a floating diffusion region, and the other source / drain 4sd of the nMOS transistor 4 are formed. NMOS to which signal voltage Vsig is supplied
The gate 1g of the transistor 1 and the reference voltage Vref are supplied n
For the gate 2g of the MOS transistor 2 and the gate 4g of the nMOS transistor 4 to which the power supply voltage V _DD is supplied, for example, the first electrode layer is used. Further, since the gate electrode 3g of the transfer gate 3 is formed adjacent to the nMOS transistor 2, for example, the second electrode layer is used. Each of the gates 1g to 4g is formed on a channel forming region between the N ⁺ -type impurity diffusion regions via a gate insulating film. The other source / drain 7 of the nMOS transistor 2 shown in FIG. 1 may be omitted by the structure in which the gate electrode 3g and the gate 2g are provided adjacent to each other as shown in FIG.

Next, FIGS. 3 and 4a to 4f and 5a.
The operation of the voltage comparison circuit of this embodiment will be described with reference to FIGS.

FIG. 3 shows signal Φ ₁ , transfer pulse signal Φ ₂ , reset signal Φ
_{3 is} a time chart of No. ₃ , showing changes in the voltage of each signal in one cycle. FIGS. 4a to 4f and 5
5A to 5F are energy characteristic diagrams sequentially showing changes in the potential of each part of the voltage comparison circuit having the cross-sectional structure of FIG. 2, and FIGS. 4A to 4F show signal voltages. When Vsig> reference voltage Vref, FIGS. 5A to 5F show the case where signal voltage Vsig <reference voltage Vref.

First, the case of Vsig> Vref will be described with reference to FIGS. 4A to 4F. At time t _1a in FIG. 3, the signal Φ ₁ and the reset signal Φ ₃ are at a high level, and the transfer pulse signal Φ ₂ is It is a low level. Therefore, as shown in FIG. 4a, the potential barrier E ₁₃ of the transfer gate 3 to which the transfer pulse signal Φ ₂ is supplied becomes high, and the signal Φ of the nMOS transistor 1 becomes Φ.
Low level of charge e ₁₁ at the source and drain 1sd _{which 1} is supplied decreases. Further, the level of the potential barrier E ₁₄ of the nMOS transistor 4 to which the reset signal Φ ₃ is supplied is lowered, and as a result, the charge of the source / drain 5 as the floating diffusion region is reset.

Next, in the third diagram of the time t _1b, signal [Phi ₁ is changed to a low level. As a result, the reset operation is performed in the potential difference conversion means, and as shown in FIG. 4b, the electric charge overflows from the potential well of the source / drain 1sd, and the electric charge is filled in the range of the nMOS transistors 1 and 2. Be done.

Next, at time t _1c in FIG. 3, the signal Φ ₁ changes from low level to high level, and the overflowed charges are again absorbed in the potential well of the source / drain 1sd as shown in FIG. 4c. . At this time, the signal voltage Vsig is supplied to the gate 1g of the nMOS transistor 1, the reference voltage Vref is supplied to the gate 2g of the nMOS transistor 2, and
Since the relationship between the voltages is Vsig> Vref, the potential barrier E ₁₁ applied to the nMOS transistor 1 on the source / drain 1sd side is lower than the potential barrier E ₁₂ applied to the nMOS transistor 2. Thus, charges stored in the potential well of the common source and drain 6 in the MOS transistor is determined by the potential barrier E _11, the potential barrier E of this potential well
_No signal is stored on the ₁₃ side.

Next, at time t _1d in FIG. 3, the reset signal Φ _{3 which} has been high level until now becomes low level, and as a result, the potential barrier E _{14 which} has been low becomes high as shown in FIG. 4d. . This means the end of the reset of the floating diffusion, potential well according to the source and drain 5 is in a state sandwiched between the potential barrier E ₁₃ and potential barriers E _14.

Next, at time t _1e in FIG. 3, the signal charges are transferred. That is, the transfer pulse signal [Phi ₂ is changed from a low level to a high level, as shown in FIG. 4 e, the transfer gate 3
Potential barrier E ₁₃ according to the lower. Then, the potential barriers E ₁₂ and E ₁₃ become stair-shaped potentials, and if signal charges are present on the potential barrier E ₁₂ , they are transferred, but since the signal voltage Vsig is larger than the reference voltage Vref here. , There is no signal charge on the potential barrier E ₁₂ , so that no signal charge is transferred to the potential well applied to the source / drain 5.
Therefore, the level of charge e ₁₅ potential well according to the source and drain 5 is an impurity diffusion region does not change.

Next, in the third diagram of the time t _1f, returned to the low level transfer pulse signal [Phi ₂ again, as a result, as shown in FIG. 4 f, the height of the potential barrier E ₁₃ becomes high. When the charge of the source / drain 5 is determined in this way, a signal corresponding to the signal charge transferred via the output buffer 11 is output. However, in this case, since the signal charge is not transferred, the output voltage V _OUT from the source / drain 5 which is the floating diffusion becomes a high level.

On the other hand, the case of Vsig <Vref will be described with reference to FIGS. 5A to 5F. At time t _1a in FIG. 3, the signals Φ _{1 to} Φ are generated.
₃ is as described above, and as shown in FIG. 5A, the potential barriers E _{11 to} E ₁₄ are the same except the potential barrier E ₁₁ , and the potential barrier E ₁₁ is high. This means that the reference voltage Vref is constant and only the signal voltage Vsig has become low.

Then, at time t _1b, signal [Phi ₁ is changed to the low level, the reset operation in the unit Tsu potential conversion. Then, as shown in FIG. 5b, the electric charge overflows from the potential well of the source / drain 1sd, and the nMOS
The charge is filled in the area of the transistors 1 and 2.

Next, at time t _1c , the signal Φ ₁ changes from low level to high level, and the overflowed charges are again absorbed in the potential well of the source / drain 1sd as shown in FIG. 5c. At this time, since the potential barrier E ₁₁ on the source / drain 1sd side is high, the potential barrier E
_{At the} same level as ₁₁ , the signal charge ΔQ remains in the range of the nMOS transistor 2.

Subsequently, at time _t1d , the same reset operation for resetting the floating diffusion as in FIG. 4d is performed (FIG. 5d).
See), then the transfer pulse signals [Phi ₂ at time t _1e is changed from low level to high level, as shown in FIG. 5 e, the potential barrier E ₁₃ according to the transfer gate 3 is low. Then, the potential barriers E ₁₂ and E ₁₃ become stepwise potential barriers, and the signal charges ΔQ are accumulated in the potential wells applied to the source / drain 5 which is the impurity diffusion region.

Then, at time t _1f , the level of the transfer pulse signal Φ ₂ is returned to the low level, and the height of the potential barrier E ₁₃ is increased as shown in FIG. As a result, the signal charge ΔQ corresponding to the potential difference between the signal voltage Vsig and the reference voltage Vref is entirely stored in the source / drain 5. This source / drain 5
Then, the voltage is lowered by the accumulated signal charge ΔQ,
The output voltage V _OUT from the source / drain 5 becomes low.

In the voltage comparison circuit of this embodiment, the signal voltage Vs
The potential difference between ig and the reference voltage Vref is transferred to the source / drain 5 functioning as a floating diffusion in the form of the signal charge ΔQ appearing in the potential well. Therefore, there is no shoot-through current as in the case of using a CMOS inverter, and the number of elements can be reduced without the need to form a large capacitance, so that the circuit scale can be reduced. Further, the speeding up is easy. Further, in order to achieve high sensitivity, a large output voltage may be obtained even if ΔQ is small. Therefore, the capacitance 10 of the source / drain 5 is reduced, and conversely, the capacitance 8 is relatively increased. As a result, a large potential difference is finally obtained even if ΔQ is small.

Although the source / drain 5 is used as the floating diffusion in the above embodiments, the charge may be converted to the voltage by the floating gate. Although the voltage comparison circuit of this embodiment can be applied to various electronic circuits, it is suitable for use in, for example, a 100 MHz / 10-bit all-parallel A / D converter. The conductivity type of the semiconductor region may be opposite. Further, a MOS transistor to which the signal voltage Vsig is input may be arranged adjacent to the transfer gate 3.

Second Embodiment This embodiment is different from the circuit of the first embodiment in that the reference voltage
This is an example of changing the circuit structure of Vref input.
This is a circuit that can be manufactured in a transistor process.

First, FIG. 6 shows the circuit configuration. An nMOS transistor 21 is provided as a first field-effect transistor for inputting a signal voltage Vsig to a gate 21g. A signal Φ ₂₁ is supplied to one source / drain 21sd of the nMOS transistor 21. The other source / drain 26 of the nMOS transistor 21 equivalently has a capacitance C ₁ with the substrate, and this source / drain 26 is a source / drain common to the nMOS transistor 22 which is the second field effect transistor. It is a drain.

NMOS transistor as a second field effect transistor
The reference voltage Vref and the ground voltage GND are supplied to the gate 22g of the gate 22. That is, the gate 22g is supplied with the reference voltage Vref via the switching transistor 27 and the ground voltage GND via the switching transistor 28.
The gate of the switching transistor 27 is supplied with the signal Φ ₂₂ , and the gate of the switching transistor 28 is supplied with the signal ▲ ▼. Therefore, the switching transistors 27 and 28 are alternatively turned on according to the signal Φ ₂₂ .
The potential difference converting means is composed of the nMOS transistor 21 and the nMOS transistor 22, and has a signal voltage Vsig as described later.
And a signal charge corresponding to the reference voltage Vref is generated. This nM
The other source / drain 25 of the OS transistor 22 has a capacitance C ₂ with the substrate and functions as a floating diffusion region. The source / drain 25 is used as an output unit for performing an output according to the signal charge, and is connected to an output buffer 29. This source / drain 25 is used for resetting nM as in the circuit of the first embodiment.
It is also one of the source and drain of OS transistor 24,
The other source / drain 24sd of this nMOS transistor 24
Is supplied with a power supply voltage V _DD . The reset signal Φ ₂₃ is supplied to the gate 24g of the nMOS transistor 24.

FIG. 7 shows an example of the structure of a voltage comparison circuit having such a circuit configuration, in which N ⁺ -type impurity diffusion regions are formed on a P-type silicon substrate 20 so as to be separated from each other. The N ⁺ -type impurity diffusion region connected to the signal Φ ₂₁ is an nMOS transistor.
21 source / drain 21sd. An impurity diffusion region between the gate 21g to which the signal voltage Vsig is supplied and the gate 22g to which the reference voltage Vref or the ground voltage GND is supplied serves as a common source / drain 26. The other source / drain 25 of the nMOS transistor 22 is a region functioning as a floating diffusion, and is also one source / drain of the reset nMOS transistor 24. The other source / drain 24sd of this nMOS transistor 24 is
This is an N ⁺ type impurity diffusion region connected to V _DD . Each of the gates 21g, 22g, and 24g is formed on a region between the N ⁺ -type impurity diffusion regions via a gate insulating film. Compared to the first embodiment, the structure in which the gate electrodes overlap each other is eliminated, and the gate electrode can be composed of only the first electrode layer. Therefore, it is advantageous for miniaturization of the element.

Next, the operation of the voltage comparison circuit of this embodiment will be described with reference to FIGS. 8 and 9a to 9d.
FIG. 8 is a waveform diagram of the signal Φ ₂₁ , the signal Φ ₂₂ , and the reset signal Φ ₂₃ , showing a one-cycle voltage change. 9a to 9d are diagrams showing a change in potential in one cycle of the voltage comparison circuit having the structure of FIG.

Here, a case where the reference voltage Vref is higher than the signal voltage Vsig will be described. First, at time _t2a in FIG.
The signal Φ ₂₁ and the signal Φ ₂₂ are at a low level, and the reset signal Φ ₂₃ is at a high level. Then, as shown in FIG. 9A, since the signal Φ ₂₁ is set to the low level, the electric potential overflows the potential barrier E ₂₁ from the potential well applied to the source / drain 21sd, and the potential difference conversion is performed. Reset the area according to the means. Also, the signal Φ ₂₂
Is low, the switching transistor
27 is off, switching transistor 28 is on,
The ground voltage GND is supplied to the gate of the nMOS transistor 22. Therefore potential barrier E ₂₂ becomes high. Also, since the reset signal Φ ₂₃ is at a high level,
The potential barrier E ₂₃ applied to the nMOS transistor 24 is lowered, and excess charges are absorbed by the power supply voltage V _DD to form a floating diffusion source / drain 25.
Is reset. The reset is the level of the source and drain 25, the preparation of the level of the reset signal [Phi _23, can be reset to the inflection point or the like which rises steeply in input-output voltage transfer characteristic diagram of an output buffer 29.
By setting such an inflection point, an output signal Vout can be obtained at high speed and with high sensitivity.

Next, at time t _2b in FIG. 8, the signal Φ ₂₁ changes from low level to high level. Then, as shown in FIG. 9B, the charges overflowing on the potential difference converting means side are discharged from the source / drain 21.
It is absorbed into the potential well in accordance with the sd, source and drain between the potential barrier E ₂₁ and the potential barrier E ₂₂
The signal charge ΔQ corresponding to the signal voltage Vsig is accumulated in the 26 potential wells.

At the next time t _2C in FIG. 8, the reset signal Φ ₂₃ changes from the high level to the low level. As a result, as shown in FIG. 9C, the height of the potential barrier E ₂₃ applied to the nMOS transistor 24 to which the reset signal Φ ₂₃ is supplied is increased, and the source / drain 25 functioning as a floating fusion is reset. In the state, source
It will be separated from the drain 24sd.

Next, at time _t2d in FIG. 8, transfer of the signal charge ΔQ is performed. That is, as the signal Φ ₂₂ changes to a high level, as shown in FIG. 9d, the potential barrier E ₂₂ that has functioned as a barrier between the potential difference conversion means and the output means in this cycle is set to the reference voltage Vref. It has potential. Then, from the potential difference from the signal voltage Vsig, Vs
If ig> Vref, E ₂₁ <E ₂₂ (barrier height) at time t _2d , and there is no transfer of signal charge to the source / drain 25. Conversely, if Vsig <Vref, E ₂₁ > E ₂₂ at time t _2d , and the signal charge ΔQ to the source / drain 25 is transferred.

Then, the signal Φ ₂₂ goes low again, the potential barrier E ₂₂ goes high, and an output signal is output from the source / drain 25. The output signal is Vsig>
If Vref, the output is high, and if Vsig <Vref, the output is low.

In such a voltage comparison circuit of the second embodiment,
Similarly to the first embodiment, the potential difference between the signal voltage Vsig and the reference voltage Vref is transferred to the source / drain 25 which is a floating diffusion in the form of a signal charge ΔQ. Therefore, there is no shoot-through current as when using a CMOS inverter, and the circuit scale can be reduced.
In particular, as compared with the first embodiment, the area of the charge transfer portion is reduced by the amount that the transfer gate 3 is omitted. In addition, it is possible to manufacture in the process of a MOS transistor in terms of process, which is suitable for fine processing. Furthermore, the capacity C ₁ /
By increasing the ratio of the capacitance C _2, it is possible to achieve the high sensitivity.

In the above embodiment, the source / drain 25 was used as a floating diffusion, but a floating gate may be formed. The conductivity type of the semiconductor region may be opposite. Further, the source / drain from which the output is taken out may be a MOS transistor whose signal voltage Vsig is inputted to the gate. Further, the reset may be performed by causing the electric charge to overflow over the entire voltage comparison circuit.

Third Embodiment In the voltage comparison circuit of the present embodiment, the signal voltage Vsig and the reference voltage Vref are sequentially input to one field effect transistor (MOS transistor) that constitutes the potential difference conversion means, and the electric charge according to the potential difference is output. This is an example of transfer to a means.

First, FIG. 10 shows a circuit configuration of the voltage comparison circuit.
The gate 31g of the nMOS transistor 31 having a pair of sources and drains connected in common has a switching transistor 3
The signal voltage Vsig is supplied via 6 and the reference voltage Vref is supplied via the switching transistor 37.
The signal φ ₃₃ is supplied to the gate of the switching transistor 36, and the signal ▲ is supplied to the gate of the switching transistor 37.
▼ is supplied. Therefore, the reference voltage Vref and the signal voltage Vsig are alternatively supplied to the gate 31g of the nMOS transistor 31.

The source / drain 35 of this nMOS transistor 31 is nM
These are the source and drain of the OS transistor 32. This nMOS
The transistor 32 is supplied with a constant voltage V _{DC at} its gate 32g and controls the overflow of charges as described later.
An output buffer 40 including transistors 38 and 39 is connected to the other source / drain 34 of the nMOS transistor 32, and the source / drain functions as a floating diffusion. The source / drain 34 is an impurity diffusion region of the output means, and is a reset nMOS.
It is also the source / drain of the transistor 33.

Reset means is made of an nMOS transistor 33 having a pair of source and drain 34,33Sd, is controlled by a signal [Phi ₃₂ applied to its gate 33 g. The signal [Phi ₃₁ is supplied to the source-drain 33Sd.

The voltage comparison circuit having such a circuit configuration can have, for example, a cross-sectional structure as shown in FIG.

The structure is such that the surface of the P-type silicon substrate 30 is exposed to N ⁺
Type impurity diffusion regions are formed, and these N ⁺ type impurity diffusion regions are respectively the source / drain 35 of the nMOS transistor 31, the source / drain 34 functioning as a floating diffusion, and the source to which the signal Φ ₃₁ for reset is supplied. -Used as the drain 33sd. Here, the source / drain 35 of the nMOS transistor 31 is a gate
It is formed so as to surround 31g, and its plane pattern is formed to have a substantially U-shape as shown in FIG.
The source / drain 34 from which the output voltage Vout is taken out
Are adjacent to the source / drain 35 via a gate 32g to which a constant voltage V _DC is supplied. And nMO for reset
The source / drain 33sd of the S transistor 33 is the nMOS.
The transistor 33 is provided with the gate 33g interposed therebetween.

Next, the operation of the voltage comparison circuit of this embodiment will be described with reference to FIGS. 13 and 14a to 14g.
FIG. 13 is a waveform diagram of the signal Φ ₃₁ , the signal Φ ₃₂ , and the signal Φ ₃₃ ,
The change of the voltage in one cycle is shown. Fig. 14a to 14
FIG. G is a diagram showing a potential change in one cycle including data reset in the voltage comparison circuit having the structure shown in FIG.

Initially, in FIG. 13 at time t _3a, the signal [Phi ₃₁ is the reset level (approximately 4V), the signal [Phi ₃₂ and the signal [Phi ₃₃ is to be in a low level (approximately 0V). At this time, as shown in FIG. 14a, the signal charge applied to the previously sampled data is not equal to the potential barrier E ₃₃ and the potential barrier E.
It remains in the potential well of the source / drain 34 between ₃₂ . The constant voltage V _DC is a by potential barrier approximately 1V E ₃₂ has a height which is fixed throughout.
Further, the power supply voltage V _DD is about 5 V, and the reference voltage Vref is supplied to the gate 31g applied to the potential barrier E ₃₁ .

Next, in the 13 view time t _3b, the signal [Phi ₃₂ changes from the low level to the high level (approximately 5V). Then, FIG. 14 b
As shown in, the potential of the gate 33g to which the signal Φ ₃₂ is supplied is increased, and the height of the potential barrier E ₃₃ is decreased. As a result, the signal charge left in the potential well of the source / drain 34 is absorbed by the source / drain 33sd.

Next, at time t _3C in FIG. 13, the signal Φ ₃₃ changes from low level to high level. As a result, the signal voltage Vsig of the data for this cycle is
Would enter the gate 31g via, as shown in FIG. 14 c, height signal voltage of the potential barrier E ₃₁ Sig
Will be the one.

Next, at time t _3d in FIG. 13, the signal Φ ₃₁ is changed from the reset level to the low level (about 0 V). As a result, as shown in FIG. 14d, the electric charge overflows from the potential well of the source / drain 33sd to which the signal Φ ₃₁ is supplied, and the electric charge spreads over the whole.

Next, in FIG. 13 at time t _3e, again signal [Phi ₃₁ is returned from the low level to the reset level. Then, as shown in FIG. 14e, the charges over the entire source and drain are
The potential of the source / drain 34, which is absorbed by 33sd and becomes a floating diffusion, is reset. At the same time, even on the potential barrier E ₃₁ side formed by inputting the signal voltage Vsig, the charge is filled with the height of the barrier E ₃₂ obtained from the constant voltage V _DC , and at this stage, the signal voltage Vsig Is applied to the potential barrier E
₃₂ will be present on the gate 31g side.

Next, at time t _3f in FIG. 13, the signal Φ ₃₂ changes from the high level to the low level. As a result, the height of the potential barrier E ₃₃ increases as shown in FIG. 14f.

Then, at time t ₃₉ of FIG. 13, the signal [Phi ₃₃ changes from the high level to the low level, the switching transistor 36 is turned off, the switching transistor 37 is turned on. Therefore, the gate 31g becomes the reference voltage Vref is switched from the signal voltage Vsig is applied, the height of the potential barrier E ₃₁ varies depending on the potential difference. Signal voltage Vsi
When g> reference voltage Vref, as shown in FIG.
An amount of signal charge corresponding to the potential difference is transferred to the source / drain 34 over the potential barrier E ₃₂ , and the potential of the source / drain 34 becomes low, so that the output signal Vout
Is output. Conversely, the signal voltage Vsig <
In the case of the reference voltage Vref, there is no signal charge transferred over the potential barrier E ₃₂ , and the output signal Vout remains high voltage.

The voltage comparison circuit according to the present embodiment has the reference voltage Vref
And the signal voltage Vsig is input and converted into the form of electric charge, so that the amount of transferred signal electric charge is not affected by the variation of the transistor. Even if the switching transistors 36 and 37 vary, they only affect the gm and there is no problem with the gate voltage of the gate 31g.

Also, as in the first and second embodiments, the through current can be suppressed, and the circuit scale can be reduced. In addition, by increasing the capacitance with the substrate, that is, the area ratio of the source / drain 35 / source / drain 34, etc., high sensitivity can be achieved, and microfabrication is easy because the manufacturing process of the MOS transistor can be applied. .

Although the present embodiment uses a floating diffusion amplifier, a floating gate amplifier may be used. After input of the signal voltage Vsig, the reference voltage Vref
, And the voltages are compared, but the order may be reversed. The conductivity type of the semiconductor region may be opposite.

Fourth Embodiment A voltage comparison circuit according to a fourth embodiment is a voltage comparison circuit in which a signal voltage Vsig and a reference voltage Vref are sequentially input to the gate of one field-effect transistor. This is an example of a voltage comparison circuit in which the source and drain are directly used as a floating diffusion.

First, the circuit configuration is such that the switching transistor 4 is connected to the gate 41g of the nMOS transistor 41 as shown in FIG.
The reference voltage Vref is supplied via 5 and the signal voltage Vsig is supplied via the switching transistor 46. The signal Φ ₄₃ is supplied to the gate of the switching transistor 45, and the signal ▲ ₄₃ is supplied to the gate of the switching transistor 46.
▼ is supplied. A capacitance C ₁ is formed between one of the source / drain 41sd of the nMOS transistor 41 and the substrate, and the other source / drain 43 of the nMOS transistor 41 is a floating diffusion for extracting the output voltage Vout. , capacitance C ₂ is formed. The source / drain 43 is an nMOS transistor 42 for reset.
NMOS transistor
The signal Φ ₄₂ is supplied to the gate 42 g of the ₄₂ . Also this n
A signal Φ ₄₁ is supplied to the other source / drain 44 of the MOS transistor 42.

The voltage comparison circuit having such a circuit configuration can have a sectional structure as shown in FIG. An N ⁺ type impurity diffusion region is formed facing the surface of the p type silicon substrate 50. These N ⁺ type impurity diffusion regions are nMOS transistor
A source / drain 41sd, a source / drain 43 common to the nMOS transistors 41 and 42, and a source / drain 44 of the nMOS transistor 42 are formed. A gate 41g is formed between the source / drain 41sd and the source / drain 43 using an electrode layer, and a gate 42g is formed between the source / drain 43 and the source / drain 44 using the electrode layer. Gate 4
The 1g signal voltage Vsig and the reference voltage Vref is supplied are switched by the switch means, to the gate 42g signal [Phi ₄₂ is supplied.

Next, the operation of the voltage comparison circuit of this embodiment will be described with reference to FIGS. 17 and 18a to 18d.
FIG. 17 is a waveform diagram of the signal Φ ₄₁ , the signal Φ ₄₂ , and the signal Φ ₄₃ ,
The change of the voltage in one cycle is shown. Fig. 18a to 18
FIG. D is a diagram showing a change in potential in one cycle in the voltage comparison circuit having the structure of FIG.

First, at time t _4a in FIG. 17, the signal Φ ₄₁ is made low. As a result, as shown in FIG. 18A, the electric charge overflows from the potential well applied to the source / drain 44, and the electric charge is filled in the whole and reset. At this time, signal Φ
₄₂ is high level, the potential barrier E ₄₂ is kept low, and the signal Φ ₄₃ is low level,
The gate 41g is supplied with the signal voltage Vsig.

Then, at time t _4b of FIG. 17, the signal [Phi ₄₁ is returned from the low level to the high level. Then, as shown in FIG. 18b,
The charges that have overflowed the whole are absorbed by the source / drain 44, and at the same time, the source / drain 43 functioning as a floating diffusion is reset. Further, the potential barrier E ₄₁ has a height corresponding to the signal voltage Vsig, and the potential well applied to the source / drain 41sd is filled with electric charges at a height corresponding to the signal voltage Vsig.

Next, at time t _4C in FIG. 17, the signal Φ ₄₂ changes from the high level to the low level. As a result, as shown in FIG. 18 c, the higher the potential barrier E _42. By thus increasing the potential barrier E _42, then the signal charges it becomes possible to stop the reliable source and drain 43 even when transferred.

Then, at time t ₄₄ of FIG. 17, the signal [Phi ₄₃ changes from the low level to the high level, the switching transistor 45 is turned on, the switching transistor 46 is turned off. As a result, the gate voltage supplied to the gate 41g of the nMOS transistor 41 changes from the signal voltage Vsig to the reference voltage Vref. As a result, the height of the potential barrier E ₄₁ changes. Then, when the signal voltage Vsig> the reference voltage Vref,
Since the potential barrier E ₄₁ becomes high, there is no charge transferred to the source / drain 43. However, when the opposite signal voltage Vsig <reference voltage Vref, as shown in FIG. 18d, the potential barrier E ₄₁ becomes low, and the charges filled at the height corresponding to the signal voltage Vsig are charged to the potential barrier E _41. E
It will be transferred to the source / drain 43 over ₄₁ .

As described above, in the voltage comparison circuit of the present embodiment, in order to transfer the signal charge corresponding to the potential difference between the signal voltage Vsig and the reference voltage Vref, and to amplify it, an output signal is obtained.
There is no through current and the number of elements can be reduced. Also, the signal voltage Vsig is applied to one nMOS transistor 41.
Since the reference voltage Vref is switched and input, the resistance to the variation of the element is stronger than that in the case where the charge corresponding to the potential difference is generated by using the plurality of transistors. Also, the capacity C ₁ / C ₂
By increasing, the gain can be increased and high sensitivity can be achieved.

In the above embodiment, a floating diffusion type amplification is performed, but a floating gate type amplification may be performed. After the reference voltage Vref, the signal voltage Vs
ig may be supplied to the gate 41g. Further, a circuit can be formed even if the conductivity type of the impurity diffusion region is the opposite conductivity type.

〔The invention's effect〕

In the voltage comparison circuit of the present invention, the switching circuit of the potential difference conversion means switches between the ground voltage and the reference voltage and supplies the ground voltage and the reference voltage to the gate of the second field effect transistor. Based on the switching operation of the switching circuit, the potential difference between the signal voltage and the reference voltage is converted into signal charge and transferred to the impurity diffusion region of the second field effect transistor. Then, the output means extracts the voltage corresponding to the signal charge and obtains the output voltage. As a result, the shoot-through current can be suppressed and the circuit scale can be reduced.

Further, by switching the reference voltage supplied to the gate of the second field effect transistor to the ground voltage, the transfer gate can be omitted, and the area of the second field effect transistor for charge transfer can be reduced. it can. Furthermore, by increasing the ratio of the source-drain capacitance of the second field effect transistor that is equivalently generated between the second substrate and the second substrate, higher sensitivity can be achieved.

Further, in the voltage comparison circuit of the present invention, the charge corresponding to the reset signal input to the gate of the third field effect transistor is transferred to the source / drain of the first field effect transistor. The switching means switches between the reference voltage and the signal voltage input to the gate of the first field effect transistor. Based on the switching operation of the switching means, a signal charge corresponding to the potential difference between the reference voltage and the signal voltage is transferred to the source / drain of the second field effect transistor. Then, the output means extracts the voltage corresponding to the potential difference and obtains the output voltage. As a result, a through current can be suppressed, and the circuit scale can be reduced.

The first field-effect transistor alone converts a potential difference between the reference voltage and the signal voltage into a charge amount. As a result, variations in signal charges due to variations in transistors are suppressed, and output characteristics are improved. In addition, by reducing the capacitance applied to the impurity diffusion region of the output means and increasing the capacitance of a portion where charges corresponding to the potential difference between the signal voltage and the reference voltage are increased, the gain can be increased. It is easy to increase the sensitivity.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an example of a voltage comparison circuit of the present invention, FIG. 2 is a cross-sectional view showing the structure of the example, FIG. 3 is a timing chart of signals supplied to the example, and FIGS. Fourth
FIG. F and FIGS. 5a to 5f are diagrams showing the energy of each part for explaining the operation of one cycle of the example, and FIGS. 4a to 4f show the case where Vsig> Vref. , Fig. 5a
~ Fig. 5f shows the case where Vsig <Vref. 6 is a circuit diagram of another example of the voltage comparison circuit of the present invention, FIG. 7 is a sectional view showing the structure of another example of FIG. 6, and FIG. 9A to 9D are timing charts of signals supplied as an example, and FIGS. 9A to 9D are diagrams showing the energy of each part for explaining one cycle of the operation of the voltage comparison circuit having the structure of FIG. 7. Further, FIG. 10 is a circuit diagram of still another example of the voltage comparison circuit of the present invention, FIG. 11 is a sectional view showing the structure of the example of FIG. 10, and FIG. 12 is the voltage of the structure of FIG. FIG. 13 is a schematic plan view of a comparison circuit, FIG. 13 is a timing chart of each signal supplied to the example of FIG. 10, and FIGS. 14a to 14g are related to the voltage comparison circuit having the structure of FIG. It is a figure which shows the energy of each part for demonstrating operation | movement of 1 cycle. 15 is a circuit diagram of still another example of the voltage comparison circuit of the present invention, FIG. 16 is a cross-sectional view showing a structure of an example of FIG. 15, and FIG. 17 is an example of FIG. 18a to 18d are timing charts of the supplied signals, and FIG. 18a to FIG. 18d are diagrams showing the energy of each part for explaining the one-cycle operation of the voltage comparison circuit having the structure of FIG. FIG. 19 is a circuit diagram showing an example of a conventional voltage comparison circuit. 1,2,4,21,22,24,31,32,33,41,42 …… nMOS transistor 5,25,34,43 …… Source / drain (impurity diffusion region) Vsig …… Signal voltage Vref …… Reference voltage

Claims (2)

(57) [Claims] A first field effect transistor having a gate to which a signal voltage is input, a second field effect transistor having one of the source and drain common to the first field effect transistor, a reference voltage and a ground. A switching circuit for switching the voltage and supplying it to the gate of the second field effect transistor, the switching circuit supplying a ground voltage to the gate of the second field effect transistor, and the first field effect transistor A charge corresponding to the signal voltage is accumulated in a source / drain common to the second field effect transistor, the switching circuit supplies a reference voltage to the gate of the second field effect transistor, and the signal voltage and the reference voltage are applied. A potential difference from a voltage is converted into a signal charge, and the signal charge is converted to the second field effect transistor which is not common to the first field effect transistor. Potential difference converting means for transferring to one of the source / drain impurity diffusion regions; output means for outputting a signal corresponding to the signal charge transferred from the potential difference converting means to the impurity diffusion region; and the potential difference converting means. A voltage comparison circuit comprising: reset means for resetting at least the signal charge in the impurity diffusion region before converting the potential difference between the signal voltage and the reference voltage into signal charge. A switching means for switching between a signal voltage and a reference voltage; a first field effect transistor having a gate supplied with the signal voltage or the reference voltage switched by the switching means; A second field-effect transistor which is common to both the source and the drain of the first field-effect transistor and has a gate supplied with a predetermined voltage; and one of the source and the drain is a first electric field of the second field-effect transistor. A voltage that is common to one that is not common to the effect transistor and that is higher than the voltage that is input to the gate of this second field effect transistor is input to the other source / drain, and is higher than the voltage that is input to this other source / drain. A third field effect transistor having a gate to which a high voltage reset signal is input; An output means for outputting a signal corresponding to a signal charge of a common source / drain of the third field effect transistor, wherein the switching means inputs a signal voltage to a gate of the first field effect transistor; The third field effect transistor transfers a signal charge to both the source and the drain of the first field effect transistor based on the reset signal, and the third field effect transistor transfers the signal charge to the second source based on the reset signal. Resetting a signal charge of a common source / drain of the field effect transistor and the third field effect transistor; the switching means inputting a reference voltage to a gate of the first field effect transistor; Converts the potential difference between the signal voltage and the reference voltage into a signal charge and converts the potential difference between the second field-effect transistor and the The signal is transferred to the common source / drain of the third field effect transistor, and the output means outputs a signal corresponding to the signal charge of the common source / drain of the second field effect transistor and the third field effect transistor. A voltage comparison circuit, characterized in that: