JPS62242410A - Relaxation oscillation circuit - Google Patents

Abstract

PURPOSE:To stabilize oscillation frequency at the time of high frequency by constituting all transistors(TR) up to the base inputs of pnp TRs in a positive feedback route of rapid npn TRs and executing the unsaturated operation of an electrostatic charge/discharge controlling TR. CONSTITUTION:All TRs up to the base input of the 1st and 2nd pnp TRs P1, P2 in the positive feedback route are constituted of rapid npn TRs N1-N8. The 2nd pnp TR P2 for controlling charge/discharge is driven so as not to execute saturated operation. The bases of the pnp TRs P1, P2 having high base diffusion capacity are controlled by the emitter followers having low output impedance to execute charge/discharge at a rapid base diffusion speed. Conse quently, response delay can be extremely reduced as compared to an ordinary circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a relaxation oscillation circuit that outputs a triangular wave oscillation signal.

[Conventional technology]

Conventional relaxation oscillation circuits are shown in FIGS. 5 and 6.

Generally, a relaxation oscillation circuit using a voltage comparator is 1
There are two voltage comparator type circuits and two voltage comparator type circuits. FIG. 5 shows a one-voltage comparator type circuit, and FIG. 6 shows a two-voltage comparator type circuit.

In FIG. 5, Ql-Q9 is a transistor,
3 is a node, Ia is a constant current source, Ra and Rh are resistors, CT is a charging/discharging capacitor, and T1 is a voltage 6. T2 is a ground terminal connected to the ground, and T3 is an output terminal for outputting a triangular wave oscillation signal to the outside.

Next, the operation of the relaxation oscillation circuit configured as described above will be explained using the operating waveforms shown in FIG. First, C5 and C7 are in the on state, and the potential of the node X2 shown in FIG.
The diagram (the dotted line at C1 indicates the potential at node X1) is shown in Figure 7 (a
) Consider the case where the potential is higher than the potential at node X1 shown in ). In this state, the charge in the charge/discharge capacitor CT is discharged through the resistor Rb, so the potential at the node X2 decreases with time. When the potential of the node X2 becomes lower than the potential of the node x1, the voltage comparator composed of the constant current source 1a and the transistors Ql-Q4 works to lower the potential of the node X3 shown in FIG. 7(b). .

As a result, transistor Q5. Q7 turns off and node Xl
The potential of the resistor Ra increases, and since there is no longer a discharge path for the charge/discharge capacitor CT, only the charging current from the resistor Ra flows through the charge/discharge capacitor CT. Therefore, the potential at the node X2 increases with time.

When the potential at node X2 becomes higher than the potential at node XI, the voltage comparator composed of constant current sources Ia and Ql to Q4
It works to raise the potential of No. 3 to a high level.

As a result, transistor Q5. Q7 turns on and node XI
potential decreases and returns to its initial state.

Next, the configuration of the relaxation oscillation circuit shown in FIG. 6 will be explained.

In FIG. 6, QIO-Q18 is a transistor, Y1
~Y6 is a node, Ib is a constant current source, and Rc is a resistance. In FIG. 6, the same or equivalent parts as in FIG. 5 are given the same reference numerals.

Next, the operation of the relaxation oscillator circuit configured in this way will be explained in the eighth section.
This will be explained using the operation waveforms shown in the figure. First, the potential of the node Y2 shown in FIG. 8(d) (the dotted line L2 shown in FIG. 8(dl shows the potential of the node Y1, and the dotted line L3 shows the potential of the node Y3) is located between the potentials of the nodes Y1 and Y3. Consider a case where the potential of the node Y5 shown in FIG. 8(a) is at a low level and the potential of the node Y6 shown in FIG. 8(bl) is at a high level. When the potential is between the potentials of If so, the previous state is maintained.

When the potential at the node Y5 is at a low level, the potential at the node Y4 shown in FIG. 8(C) is also at a low level, and the transistor Q5 is in an off state. In this state, since a charging current flows to the charging/discharging capacitor CT through the resistor Ra, the potential at the node Y2 increases with time.

When the potential of the node Y2 is higher than the potential of the node Y3, the voltage comparator consisting of the constant current source 1a and the transistors Ql-Q4 operates, and the transistor Q3 is turned on.As a result, the potential of the node Y5 becomes high level. The potential at node Y6 becomes low level, the potential at node Y4 becomes high level, and transistor Q
5 turns on. When the transistor Q5 is turned on, a discharge current flows from the charging/discharging capacitor CT through the resistor Rb, so that the potential at the node Y2 decreases with time. Node Y2
When the potential of the constant current source 1b becomes lower than the potential of the node Yl, the constant current source 1b
, a voltage comparator composed of transistors QIO to Q15 operates, and transistor Q16 is turned on. This results in
The potential at the node Y5 becomes a low level, and the potential at the node Y6 becomes a high level, returning to the initial state.

[Problem that the invention seeks to solve]

FIG. 9 is a waveform diagram for explaining that the relaxation oscillation circuits of FIGS. 5 and 6 cannot obtain oscillation frequency accuracy at high frequencies. The reason why oscillation frequency accuracy cannot be obtained is that there is a response delay after the charging/discharging waveform of the charging/discharging capacitor CT passes the reference voltage of the voltage comparator until the charging/discharging transistor Q5 is sensitive to it. Each case of this response delay is shown in Fig. 9 (al, (b). Fig. 9 (a)
) is a case where there is a delay ts from when the charging/discharging waveform of the charging/discharging capacitor CT passes the reference voltage of the voltage comparator until the charging/discharging transistor Q5 starts to be sensitive. This delay results in waveform overshoot os. The case shown in FIG. 9 (bl) is a case where the charging/discharging transistor Q5 has started to respond but remains in an intermediate state between on and off. In this case, as shown in FIG. A flatness FN is generated for the time ts remaining in the state.

The relaxation oscillator circuits shown in FIGS. 5 and 6 include a lateral PNP transistor in the signal path and cause the charging/discharging transistor Q5 to perform a saturation operation. ), response delays as shown in (b) are likely to occur.

The present invention has been made in view of these points, and its purpose is to obtain a relaxation oscillation circuit whose oscillation frequency is stable even at high frequencies.

[Means for solving problems]

To achieve such an object, the present invention provides a first NPN transistor whose emitter is connected to a first constant current source, and a second NPN transistor whose emitter is connected to the emitter of the first NPN transistor. and the first NP
N The first transistor connected between the collector and the power supply
a second resistor connected between the collector of the transistor and the power supply, and a base of the first NPN transistor;
A third NPN transistor whose collector is connected to the power supply, and a second NPN transistor whose base is connected to the collector of the transistor.
a fourth NPN transistor whose collector is connected to the power source; a fifth NPN transistor whose emitter is connected to the second constant current source; and a fifth NPN transistor whose emitter is connected to the second constant current source and whose collector is connected to the second constant current source. a sixth NPN transistor connected to the base of the NPN transistor, and a fifth NPN transistor connected to the emitter of the third NPN transistor.
A third resistor connected between the base of the PN transistor and the emitter of the fourth NPN transistor and the sixth NP
a fourth resistor connected between the bases of the N transistor;
3rd NPN transistor emitter/5th NPN
a fifth resistor connected between the collectors of the transistors;
5th NPN transistor collector/6th NPN
a sixth resistor connected between the collectors of the transistors, a seventh NPN transistor whose collector is connected to the base of the fifth NPN transistor and whose base is connected to the base of the sixth NPN transistor; 6
8th NPN connected to the base of the transistor
a PN transistor, a first voltage level shift means connected between the emitter of the seventh NPN transistor and ground, and a second voltage level shift means connected between the emitter of the eighth NPN transistor and ground; The emitter is the third constant current source and the base is the third NPN. The emitter of the transistor is the first P whose colent is connected to ground.
an NP transistor with its emitter connected to a third constant current source and its base connected to a fourth NPN transistor; and a second PNP transistor whose collector is connected to the base of the first NPN transistor; and the collector of the second PNP transistor. - A fourth constant current source connected between the ground and a charge/discharge capacitor connected between the collector of the second PNP transistor and the ground are provided.

[Effect]

In the present invention, the transistor controlling charging and discharging does not perform saturation operation.

〔Example〕

An embodiment of the relaxation oscillation circuit according to the present invention is shown in FIG. In FIG. 1, 11 to I4 are first to fourth constant current sources with constant current values 11 to i4, and N1 to N8 are first to eighth NPs.
N transistor, Pl is the first -PNP transistor, R2 is the second PNP transistor for controlling charging and discharging, and R1-R6 are the first to sixth transistors with resistance values r1 to r6.
R7 is a resistor with a resistance value r7 which constitutes the first voltage level shifting means, R8 is a resistor with a resistance value r8 which constitutes the second voltage level shifting means, CT is a charging/discharging capacitor, and BT is a voltage. T1 is a power supply terminal to which a DC power supply of voltage v'cc is supplied, T2 is a ground terminal connected to the ground, T3 is an output terminal from which a triangular wave oscillation signal is output,
A-F are nodes.

Next, the operation of the relaxation oscillation circuit configured as described above will be explained using the operating waveforms shown in FIG. 4.

First, the potential of node F (point '41AL) shown in FIG.
4 indicates the potential of node A) is node A shown in FIG. 4(a).
Consider the case where the potential is higher than . At this time, since the NPN transistor N1 is on and the NPN transistor N2 is off, the potential of node B shown in FIG.
The potential of node C shown in Fig. 4(C) is VC1 Fig. 4(d)
The potential at the node shown in is VD, and the potential at the node E shown in FIG. 4 (Q) is VD.
Letting the potential of VE be VE, the following relationship holds true.

VB<VC...(1) VD<VE...(2) Therefore, NPN transistor N5 is off, NPN
Transistor N6 is in an on state. Node A in this case
The potential VA is given by the following equation.

VA-V, e-r 1 ・i 1- (r5+r6)
Hi 2 - Vlt3 (3) where V III is the base-emitter voltage of the NPN transistor N3. As shown in equation (l), VB
<Since VC, PNP transistor pi is on,
PNP transistor P2 is off, a discharge current of 14 flows from charging/discharging capacitor CT, and the potential at node F decreases with time. When the potential at node F becomes lower than the potential at node A, NPN transistor Nl begins to turn off, and node B
The potential at node A starts to rise, and the potential at node A also starts to rise, so that the degree to which the NPN transistor N1 is turned off further increases. Due to this positive feedback phenomenon, the NPN transistor N1
is completely off, and the NPN transistor N'2 is completely on.

When the NPN transistor N1 is completely off and the NPN transistor N2 is completely on, the following relationship holds true.

VB>VC (4) VD>VE (5) Therefore, the NPN transistor N5 is on and the NPN transistor N6 is off. In this case, the potential VA at node A is expressed by the following equation.

VA=Vcc-r 5 ・i 2 Vliz...1
6) In this case, the potential of node A is compared to the value of equation (3),
It is higher by rl-i 1+r6·12.

As shown in equation (4), since VB>VC, the PNP transistor Pi is off and the PNP transistor P2 is on. Assuming that i 3 > i 4, a charging current of 13-T4 flows through the charging/discharging capacitor CT, and the potential of the node F increases with time. The potential of node F is node A
When the potential becomes higher than the potential, the NPN transistor N1 starts to turn on, so the potential at the node B starts to decrease, the potential at the node A also starts to decrease, and the degree to which the NPN transistor N1 is turned on increases. Due to this positive feedback phenomenon, NPN
Transistor Nl is completely on and NPN transistor N2 is completely off, returning to its initial state.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. The circuit of FIG. 2 integrates the resistors R7 and R8 of FIG. 1 with an NPN transistor N9, and provides the same effect as the first embodiment.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention. The circuit of FIG. 3 consists of the resistors R7 and R8 of FIG. 1 and the NPN transistor N7. The arrangement is replaced with N8, and the same effect as in the first embodiment is achieved.

〔Effect of the invention〕

As explained above, the present invention provides first to fourth constant current sources, first to eighth NPN transistors, and first and second PNP transistors.
A transistor, first to sixth resistors, and a first to sixth resistor. By providing the second voltage level shift means and the charging/discharging capacitor, the first voltage level shift means and the charging/discharging capacitor are provided in the positive feedback route. The second PNP transistor has a fast N
It can be a PN transistor, and there is no need to operate the second PNP transistor that controls charging and discharging in saturation.The base of the PNP transistor, which has a large base diffusion capacitance, can be controlled by an emitter follower with low output impedance, and the base can be diffused. Since the capacitance can be charged and discharged quickly, response delay can be extremely reduced compared to conventional circuits, and a relaxation oscillation circuit with high precision can be obtained even at high frequencies.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a relaxation oscillation circuit according to the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention,
FIG. 3 is a circuit diagram showing a third embodiment of the present invention, FIG. 4 is a waveform diagram for explaining the operation of the circuit in FIG. 1, and FIG.
Figure 6 is a circuit diagram showing a conventional relaxation oscillation circuit, Figure 7 is a waveform diagram to explain the operation of the circuit in Figure 5, and Figure 8 is a waveform diagram to explain the operation of the circuit in Figure 6. 9 are waveform diagrams for explaining the oscillation frequency accuracy in a conventional circuit. 11~■4... Constant current source, N1-N3...NP
N transistor, Pi, R2...PNP transistor, R1-R8...resistor, CT...charging/discharging capacitor, BT...DC power supply, T1...power supply terminal, T2... ...Ground terminal, T3...Output terminal, A
-F... Node.

Claims (1)

[Claims] a first NPN transistor whose emitter is connected to the first constant current source; a second NPN transistor whose emitter is connected to the emitter of the first NPN transistor; and a collector of the first NPN transistor and a power supply. a first resistor connected between the second resistor, a second resistor connected between the collector of the second NPN transistor and the power supply, and a base connected to the collector of the first NPN transistor and the collector connected to the power supply. a fourth NPN transistor whose base is connected to the collector of the second NPN transistor and whose collector is connected to the power supply; and a fifth NPN transistor whose emitter is connected to the second constant current source. NP
an NPN transistor, a sixth NPN transistor whose emitter is connected to the second constant current source and whose collector is connected to the base of the second NPN transistor, the emitter of the third NPN transistor and the base of the fifth NPN transistor. a third resistor connected between the emitter of the fourth NPN transistor and the base of the sixth NPN transistor; a fourth resistor connected between the emitter of the third NPN transistor and the base of the sixth NPN transistor; a fifth resistor connected between the collector of the fifth NPN transistor and the collector of the sixth NPN transistor; a sixth resistor connected between the collector of the fifth NPN transistor and the collector of the sixth NPN transistor; a seventh NPN transistor connected to the base of the fifth NPN transistor and whose base is connected to the base of the sixth NPN transistor;
PN transistor, collector and base are the sixth NP
an eighth NPN transistor connected to the base of the NPN transistor, and a first voltage level shifting means connected between the emitter of the seventh NPN transistor and ground;
a second voltage level shifting means connected between the emitter of the eighth NPN transistor and ground; the emitter connected to a third constant current source, the base connected to the emitter of the third NPN transistor, and the collector connected to the third constant current source; a first PNP transistor connected to ground, and a second PNP transistor having an emitter connected to a third constant current source, a base connected to the emitter of the fourth NPN transistor, and a collector connected to the base of the first NPN transistor. and a second PNP transistor.
a fourth constant current source connected between the collector of the second PNP transistor and ground; and a charge/discharge capacitor connected between the collector of the second PNP transistor and ground; A relaxation oscillation circuit characterized in that a triangular wave oscillation signal is output from a collector.