JPH05122023A - Semiconductor circuit device - Google Patents

Abstract

PURPOSE:To obtain a novel counter circuit, regarding a semiconductor circuit device. CONSTITUTION:This semiconductor circuit device is provided with a flip-flop circuit part 2 composed of a pair of transistors T6, T7 performing inversion operations and a diode D1 turning on the transistor T7 and turning off the transistor T6 at the time of an initialization, a transistor T1 which is turned on by the rise of an input signal VIN, and a transistor T2 which a parallel connection is performed with the transistor T1 and an operation is performed by the transistor 7. The device is provided with a first control circuit part 3 performing the inversion operation of a pair of transistors T6, T7 when the transistor T2 is turned off and the transistor T1 is turned on by the input signal VIN, a transistor T12 which is turned on by the rise of the input signal VIN, and a transistor T11 which a parallel connection is performed with the transistor T12 and an operation is performed by the transistor T6. The device is provided with a second control circuit part 4 performing the inversion operations of a pair of the transistors T6, T7 when the transistor T11 is turned off and the transistor T12 is turned on by the input signal VIN.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit device.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 5, a flip-flop 20 is composed of a pair of transistors Tr1 and Tr2, resistors R50 to R59, capacitors C10 to C13 and diodes D10 to D15. Then, when the clock pulse Cp is input to the clock terminal CLK while the input terminals J and K are always at the H level, the counter circuit in which the output signal of the output terminal Q is alternately inverted every time the clock pulse Cp falls. Composed.

Therefore, by combining the four flip-flops 20 configured as described above as shown in FIG. 4 and two AND circuits 21 as required,
The hexadecimal counter circuit 22 is configured. Also, a semiconductor circuit device can be constructed by forming the four flip-flops 20 and the two AND circuits 21 on one chip.

[0004]

However, as described above, the present applicant has proposed that the pair of transistors Tr1, Tr2,
I was trying to make a new flip-flop other than the flip-flop 20 composed of the resistors R50 to R59, the capacitors C10 to C13, and the diodes D10 to D15.

An object of the present invention is to provide a semiconductor circuit device capable of forming a counter circuit with a novel flip-flop.

[0006]

In order to solve the above problems, the present invention operates a pair of alternately operating output transistors and one output transistor at the time of initial setting,
A flip-flop circuit unit including an initial setting unit that deactivates the other output transistor, a first transistor that operates based on a rise of an input signal, and the first transistor.
The flip-flop connected in parallel to the transistor
A second transistor that operates based on one of the output transistors in the flop circuit section, wherein the second transistor is deactivated based on the one output transistor, and the first transistor operates when the input signal rises. A first control circuit section that performs an inverting operation of a pair of output transistors in the flip-flop circuit section; a third transistor that operates based on a rising edge of an input signal; and a third transistor that is connected in parallel to the third transistor, A fourth transistor that operates based on the other output transistor in the flip-flop circuit section, the fourth transistor becomes inactive based on the other output transistor, and the third transistor operates when the input signal rises. In the flip-flop circuit section Further comprising a second control circuit unit for performing inverting operation of the output transistor of the pair as its gist.

[0007]

When the power is turned on to the initial state, one of the output transistors is activated and the other output transistor is deactivated by the initialization means of the flip-flop circuit section. The second transistor of the first control circuit unit is deactivated based on the operation of the one output transistor, and the fourth transistor of the second control circuit unit is activated based on the non-operation state of the other output transistor. .. Then, based on the rise of the input signal,
The three transistors are activated. At this time, since the fourth transistor is in the operating state even when the third transistor is in the operating state, the second control circuit unit does not perform the inverting operation of the pair of output transistors in the flip-flop circuit. On the other hand, since the second transistor is in the non-operating state and the first transistor is in the operating state, the first control circuit unit performs the inverting operation of the pair of transistors in the flip-flop circuit unit. As a result, one of the output transistors becomes inactive and the other output transistor becomes active. Therefore, the second transistor is in the operating state and the fourth transistor is in the non-operating state.

After that, when the input signal falls, the first and third
Although the transistor is inoperative, the first and second control circuit units do not perform the inverting operation of the pair of output transistors in the flip-flop circuit unit.

Then, when the input signal rises again, the first and third transistors are activated. At this time, the first
Even when the first transistor of the control circuit unit is in the operating state, the second transistor is in the operating state, so that the first control circuit unit does not perform the inverting operation of the pair of output transistors in the flip-flop circuit unit. On the other hand, since the fourth transistor of the second control circuit unit is in the non-operating state and the third transistor is in the operating state, the second control circuit unit performs the inverting operation of the pair of output transistors in the flip-flop circuit unit.

Therefore, the inversion operation of the pair of output transistors of the flip-flop circuit section can be performed every time the input signal rises.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention is shown in FIG.
It will be described with reference to FIG. As shown in FIG. 1, the counter circuit 1 includes a flip-flop circuit section 2 and a first control circuit section 3.
And a second control circuit section 4.

First, the first control circuit section 3 will be described in detail. The first control circuit unit 3 is provided with an input terminal ST1 to which an input signal VIN is input, and the base of a transistor T1 as a first transistor is connected to the input terminal ST1. The collector of the transistor T1 is connected to the power supply line Vcc via the resistor R1 and the emitter is connected to the ground line GND. The collector of a transistor T2 as a second transistor is connected to the node N1 between the collector of the transistor T1 and the resistor R1, and the emitter of the transistor T2 is connected to the ground line GND. Resistors R2 and R3 connected in series are connected between the power supply line Vcc and the ground line GND. A capacitor C1 is connected between the node N1 between the resistors R2 and R3 and the node N1.

An emitter of a transistor T3 is connected to the node N2, and a base of the transistor T3 is connected to a power source line Vcc via a resistor R4. The collector of the transistor T3 is connected to the base of the transistor T4. The collector of the transistor T4 is connected to the power supply line Vcc through the resistor R5, and the emitter is connected to the ground line GND.

Further, regardless of the states of the transistors T1 and T2, when the capacitor C1 is in a stable state, the node N2 is at H level, and the current Ibc1 flows from the base of the transistor T3 to the collector. This current Ibc1 turns on the transistor T4. However, the transistors T1 and T
2 from the off state, the transistors T1, T2
When any one of them is turned on, the capacitor C1 is grounded, so that the electric charge charged in the capacitor C1 is discharged. Therefore, the node N2 determined by the resistance ratio of the resistors R2 and R3 becomes L level.

Therefore, the current Ibc1 flowing from the base of the transistor T3 to the collector is cut off, and the current Ibe1 flows from the base of the transistor T3 to the emitter.
As a result, the transistor T4 is turned off. After the capacitor C1 is fully charged,
The potential of the node N2 returns to the H level again, the current Ibc1 flows from the base of the transistor T3 to the collector again, and the transistor T4 is turned on.

Next, the configuration of the flip-flop circuit section 2 will be described in detail. The base of the transistor T5 constituting the flip-flop circuit unit 2 is connected to the node N3 between the collector of the transistor T4 and the resistor R5. Therefore, the transistor T5 is turned on by the control current GS1 output when the transistor T4 is switched from on to off. The collector of the transistor T5 is connected to the power supply line Vcc through the resistor R6, and the emitter is connected to the ground line GND. The collector of the transistor T5 and the resistor R
The collector of a transistor T6 as the other output transistor is connected to the node N4 between the transistor T6 and the node N6, and the emitter of the transistor T6 is connected to the ground line GND.

The base of a transistor T7 as one output transistor is connected to the node N4.
The emitter of the transistor T7 is connected to the ground line GND. The collector of the transistor T7 is connected to the power source Vcc through a diode D1 as an initial setting means and a resistor R7. And the transistor T7
Node N5 between the collector of diode and diode D1
Is connected to the base of the transistor T6 and to the collector of the transistor T8.
The collector of the transistor T8 is connected to the ground line GND.

The base of the transistor T2 is connected to the node N5. Further, the node N
Output terminals VOUT and / VOUT are connected to 4 and N5 so that complementary signals are output.

Next, the second control circuit section 4 will be described in detail. The collector of the transistor T9 constituting the second control circuit unit 4 is connected to the power supply Vcc via the resistor R8, and the emitter is connected to the ground line GND. A node N6 between the collector of the transistor T9 and the resistor R8 is connected to the base of the transistor T8. or,
The base of the transistor T9 is connected to the collector of the transistor T10, and the base of the transistor T10 is connected to the power supply Vcc via the resistor R9. Further, resistors R10 and R11 are provided between the power supply line Vcc and the ground line GND.
Are connected in series. The emitter of the transistor T10 is connected to the node N7 between the resistors R10 and R11.

On the other hand, the input signal VIN is applied to the second control circuit section 4.
Is provided with an input terminal ST2 for inputting
A transistor T12 as a third transistor is provided in T2.
The base of is connected. The collector of the transistor T12 is connected to the power supply line VCC through the resistor R12,
The emitter of the transistor T12 is connected to the ground line GND. The collector of a transistor T11 as a fourth transistor is connected to a node N8 between the collector of the transistor T12 and the resistor R12, and the emitter of the transistor T11 has a ground line GND.
It is connected to the. The base of the transistor T11 is connected to the node N4. Further, the node N
A capacitor C2 is connected between 7 and N8.

In addition, regardless of the states of the transistors T11 and T12, when the capacitor C2 is in a stable state, the node N7 becomes H level and the transistor T10.
A current Ibc2 flows from the base to the collector. This current Ibc2 causes the transistor T9
Is turned on. However, when one of the transistors T11 and T12 is turned on while the transistors T11 and T12 are turned off, the capacitor C2 is grounded, so that the capacitor C2 is grounded.
The electric charge charged to 2 is discharged. Therefore, the resistance R1
Node N7 determined by the resistance ratio of 0 and R11
Becomes the L level.

Therefore, the current Ibc2 flowing from the base of the transistor T10 to the collector is cut off, and the current Ibe2 flows from the base of the transistor T10 to the emitter. As a result, the transistor T9 is turned off. Then, after the capacitor C2 is sufficiently charged, the potential of the node N7 returns to the H level again, the current Ibc2 flows from the base of the transistor T10 to the collector again, and the transistor T9 is turned on. The transistor T8 outputs a control current GS2 output when the transistor T9 is switched from on to off.
It is supposed to turn on.

Next, the operation of the counter circuit 1 in the semiconductor circuit device configured as described above will be described.
First, when power is supplied to the power line VCC, the counter circuit 1
The node N4 of the flip-flop circuit unit 2 in FIG.
Since it becomes H level before 5, the transistor T7 is turned on. As a result, the node N5 goes low and the transistor T6 is turned off. Therefore, the output terminal VOUT becomes L level and the output terminal / VOUT becomes H level.
Also, when the transistor T7 is turned on, the transistor T
2 is turned off, and the transistor T11 is turned on by turning off the transistor T6.

When the input signal VIN is at the L level, the transistor T1 of the first control circuit section 3 is turned off and the nodes N1 and N2 hold the H level, so that the current Ibc1 flows from the base of the transistor T3 to the collector. Flows. Therefore, since the transistor T4 is turned on, the control current GS1 is not output to the base of the transistor T5, the transistor T5 is turned off, and the H level of the node N4 is held.

Further, the transistor T1 of the first control circuit section 3
Is off, but the transistor T11 is already on, so the capacitor C2 is grounded. At this time, since the capacitor C2 is fully charged, the node N7 becomes H level and the transistor T10.
A current Ibc2 flows from the base of the to the collector. Therefore, the transistor T9 is turned on, so that the transistor T8 is turned on.
The control current GS2 is not output to the base of the transistor and the transistor T8 is turned off. Even if the transistor T8 is turned off, the transistor T7 is turned on.
Level does not change.

The input signal V which has risen from the above state
When IN is input to the input terminals ST1 and ST2, the transistors T1 and T12 are turned on. At this time, the second
Since the transistor T11 has already been turned on at the node N8 of the control circuit unit 4, the capacitor C2 is not discharged.
Also, since the capacitor C2 is fully charged,
The node N7 is in the H level state. Therefore, the state where the current Ibc2 flows from the base of the transistor T10 to the collector is maintained. Further, since the transistor T9 is kept on, the control current GS2 is not output to the base of the transistor T8, and the transistor T8 is kept off.

On the other hand, since the transistor T2 is off, the transistor C1 is turned on to turn on the capacitor C1.
Is grounded, the electric charge stored in the capacitor C1 is discharged. Therefore, the node N2 becomes L level, so that the current Ibc1 flowing from the base to the collector of the transistor T3 is cut off, and the current Ibe1 flows from the base to the emitter. As a result, the transistor T4 is turned off and the node N3 becomes H level, so that the control current GS1 flows to the base of the transistor T5 and the transistor T5 is turned on.

When the transistor T5 is turned on, the transistor T7 is turned off. Further, since the transistor T8 is off, the node N5 becomes H level and the transistor T6 is turned on. Therefore, the output terminal VOUT changes from the L level to the H level, the output terminal / VOUT changes from the H level to the L level, and the output signal is inverted.

When the capacitor C1 is sufficiently charged, the node N2 becomes H level, the current Ibe1 is cut off, and the current Ibc1 flows to the base of the transistor T4.
As a result, the transistor T4 is turned on and the control current GS1
Is not output to the base of the transistor T5, and the transistor T5 is turned off. Even if the transistor T5 is turned off, since the transistor T6 is turned on, the L level of the node 4 is maintained. Then, the operation of the transistors T6 and T7 is reversed, so that the transistor T2
Is on and the transistor T11 is off.

Next, when the input signal VIN switched from the H level to the L level is input to the input terminals ST1 and ST2, the transistors T1 and T12 are turned off, but the first and second control circuit units 3 and 4 are turned off. Nodes N2 and N7 at
Since the level is held, the control currents GS1 and GS2 are not output to the bases of the transistors T5 and T8. Therefore, the transistors T6 and T7 do not perform the inversion operation.

When the rising input signal VIN is input to the input terminals ST1 and ST2, the transistors T1 and T12 are turned on. At this time, since the transistor T2 has already been turned on at the node N1 of the first control circuit unit 3, the capacitor C1 is not discharged. Since the capacitor C1 is fully charged, the node N
2 is in the H level state. Therefore, the state where the current Ibc1 flows from the base of the transistor T3 to the collector is maintained. Therefore, since the transistor T4 is kept on, the control current GS1 is applied to the base of the transistor T5.
Is not output, and the OFF state of the transistor T5 is maintained.

On the other hand, since the transistor T11 is off and the transistor T12 is on, the capacitor C2 is grounded, and the electric charge stored in the capacitor C2 is discharged. Therefore, since the node N7 becomes L level, the current Ibc2 flowing from the base to the collector of the transistor T10 is cut off, and the current Ibc2 from the base to the emitter.
be2 flows. As a result, the transistor T9 is turned off and the node N6 becomes H level.
A control current GS2 flows to the base of the transistor T8,
Turns on.

When the transistor T8 is turned on, the transistor T6 is turned off. Further, since the transistor T5 is off, the node N4 becomes H level and the transistor T7 is turned on. Therefore, the output terminal VOUT changes from H level to L level, the output terminal / VOUT changes from L level to H level, and the output signal is inverted.

When the capacitor C2 is sufficiently charged, the node N7 becomes H level, the current Ibe2 is cut off, and the current Ibc2 flows to the base of the transistor T9.
As a result, the transistor T9 turns on and the control current GS2
Is not output to the base of the transistor T8, and the transistor T8 is turned off. Even if the transistor T8 is turned off, the transistor T7 is turned on, so that the L level of the node N5 is held. Then, by inverting the operation of the transistors T6 and T7, the transistor T
2 turns off and transistor T11 turns on.

Next, when the input signal VIN switched from the H level to the L level is input to the input terminals ST1 and ST2, the transistors T1 and T12 are turned off, but the first and second control circuit units 3 and 4 are turned off. Nodes N2 and N7 at
Since the level is held, the control currents GS1 and GS2 are not output to the bases of the transistors T5 and T8. Therefore, the transistors T6 and T7 do not perform the inversion operation.

As a result, the counter circuit 1 which can alternately invert the output of the flip-flop circuit section 2 every time the input signal VIN rises can be constructed.
As a result, the counter circuit 1 can be configured with a circuit configuration different from the conventional one.

Then, as shown in FIG. 2, four counter circuits 1A to 1D are arranged in series, and the counter circuit 1A is provided.
Output terminal / VOUT of the counter circuit 1B input terminal ST
1, ST2, and the output terminal / V of the counter circuit 1B
OUT is connected to the input terminals ST1 and ST2 of the counter circuit 1C. Further, the output terminal / VOUT of the counter circuit 1C is connected to the input terminals ST1 and ST2 of the counter circuit 1D. The output terminal VOU of each counter circuit 1A-1D
The output signals VOUT1 to VOUT4 are output from T.

As a result, when the input signal VIN serving as a clock pulse is input to the input terminals ST1 and ST2 of the counter circuit 1A, the counter circuits 1A to 1D operate to form a hexadecimal counter. If the counter circuits 1A to 1D are formed on one chip, a semiconductor circuit device that serves as a hexadecimal counter circuit can be constructed.

The first and second control circuit sections 3 and 4 need only be able to turn off the transistors T4 and T9 via the transistors T3 and T10 when the input signal VIN rises. The electric capacity can be reduced. As a result, the area for forming the capacitors C1 and C2 on one chip can be integrated, so that the chip area can be made compact.

In this embodiment, the flip-flop circuit section 2 of the counter circuit 1 is supplied by supplying power to the power supply line VCC.
In the initial state, due to the voltage drop of the diode D1, the node N4 is set to the H level before the node N5 to turn on the transistor T7 and turn off the transistor T6. However, as shown in FIG. Alternatively, the current source 5 may be provided.

In this case, when power is supplied to the power supply line Vcc to initialize the flip-flop circuit portion 2 of the counter circuit 1, the current source 5 causes more current to flow to the node N4 than to the node N5. .. As a result, the transistor T7 is turned on before the transistor T6, so that the node N5 becomes L level. Therefore, the transistor T6 can be turned off and the node N4 can be set at the H level.

The circuit shown in FIG. 1 can also be used as a frequency dividing circuit. That is, a cycle of 1/2 ⁿ can be obtained by configuring the circuit in n stages as shown in FIG.

[0043]

As described above in detail, according to the present invention, there is an excellent effect that the counter circuit can be constituted by the novel flip-flop.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram of a counter circuit according to the present invention.

FIG. 2 is a block configuration diagram of a hexadecimal counter configured by a counter circuit.

FIG. 3 is an electric circuit diagram showing another example of the configuration of the flip-flop circuit unit.

FIG. 4 is a block diagram of a conventional hexadecimal counter.

FIG. 5 is an electric circuit diagram of a conventional counter circuit.

[Explanation of symbols]

2 ... Flip-flop circuit section, 3 ... First control circuit section,
4 ... Second control circuit section, D1 ... Diode as initial setting means, T1 ... First transistor, T2 ... Second transistor, T6 ... Other output transistor, T7 ... One output transistor, T11 ... Fourth transistor, T12 …
Third transistor, VIN ... Input signal

Claims (1)

[Claims] 1. A pair of output transistors operating alternately, and one output transistor operating at the time of initial setting,
A flip-flop circuit section including an initialization means for deactivating the other output transistor; a first transistor that operates based on the rising edge of an input signal; and a parallel connection to the first transistor,
A second transistor that operates based on one of the output transistors in the flip-flop circuit section, the second transistor is deactivated based on the one of the output transistors, and the first transistor is turned on when the input signal rises. A first control circuit section that performs an inverting operation of a pair of output transistors in the flip-flop circuit section when operating, a third transistor that operates based on a rising edge of an input signal, and a parallel connection to the third transistor Was
A fourth transistor that operates based on the other output transistor in the flip-flop circuit section, the fourth transistor becomes inactive based on the other output transistor, and the third transistor operates when the input signal rises. A semiconductor circuit device comprising: a second control circuit section that performs an inverting operation of a pair of output transistors in the flip-flop circuit section when operated.