JPH06303117A - Startup circuit - Google Patents

Abstract

PURPOSE:To obtain a startup circuit whose operation is stable and which is realized with small scale configuration and less power consumption. CONSTITUTION:The startup circuit is provided with a bipolar transistor (TR) Q0 forming a current source supplying a current of a bias line LBIAS of a semiconductor integrated circuit 2 just after a power supply voltage Vcc is applied to the semiconductor integrated circuit 2. The startup circuit 1 is provided with a switching circuit 3 controlling a current of the TRQ0 supplying a current to the bias line LBIAS and a control circuit 4 having a delay characteristic to control the switching circuit 3. Then the switching circuit 3 is made nonconductive after lapse of a predetermined time after application of a power supply voltage to reduce current consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a start-up circuit having a current source for supplying a current to a bias line of a semiconductor integrated circuit immediately after a power supply voltage is applied to the semiconductor integrated circuit.

[0002]

2. Description of the Related Art A start-up circuit is provided to supply a current to a bias line of a semiconductor integrated circuit immediately after a power supply voltage is applied to the semiconductor integrated circuit.
Conventionally, as such a start-up circuit, one having a configuration shown in FIG. 11 is known. This startup circuit 101
As shown in FIG. 11, is an NPN bipolar transistor Q100 and an NPN transistor with a collector and base short-circuited.
Type bipolar transistors Q101 and Q102, and a resistor R
It consists of 100 and. That is, the transistor Q10
The collector of 0 is connected to the high potential power supply V _CC , and the base is connected to the bias line L _BIAS of the semiconductor integrated circuit 102 in the subsequent stage. The emitter of transistor Q100 is transistor Q10.
Connected to the collector and base of 1, transistor Q101
Is connected to the collector-base of the transistor Q102. The emitter of the transistor Q102 is connected to the ground potential GND via the resistor R100. The resistor R100 is selected to have a value of several tens KΩ to several hundreds KΩ in order to limit the emitter current flowing when the transistor Q100 becomes conductive.

The start-up circuit configured as described above operates so as to supply the current of the bias line L _BIAS of the semiconductor integrated circuit immediately after a predetermined power supply voltage is applied to the semiconductor integrated circuit including the start-up circuit.

[0004]

By the way, after the bias line of the semiconductor integrated circuit reaches the stable operation region, the start-up circuit is changed to a circuit which is substantially unnecessary. Therefore, there is a demand for a start-up circuit having a small circuit scale and low circuit power consumption after the bias line reaches the stable operation region.

When the bias line reaches the stable operation region, the power consumed by the start-up circuit has nothing to do with the circuit power required for the circuit operation, and the power consumption reduction for the recent small electronic devices has been achieved. Among them, it is not a problem.

Therefore, it is desirable that the power consumption of the start-up circuit is zero after the bias line of the semiconductor integrated circuit reaches the stable operation region. However,
The power consumption in the conventional start-up circuit is the circuit current I even after the bias line reaches the stable operation region.
_It keeps flowing as ₀ . This circuit current I ₀ is obtained by _changing the voltage of the bias line L _BIAS to V _BIAS and the transistors Q100 and Q10.
1, the base-emitter voltage of Q102 is V _BE100 , V
_{Let BE101} and V _BE102, and let the resistance value of the resistor R100 be R, then this is expressed by the following equation (1). I ₀ = {V _BIAS − (V _BE100 + V _BE101 + V _BE102 )} / R (1)

The circuit current I ₀ can be suppressed as small as possible, for example, by increasing the resistance value R of the resistor R100, but in order to provide a high resistance in the semiconductor integrated circuit, the area is greatly increased. Will be forced to. As another method, by increasing the number of stages of the transistors Q101 and Q102 whose collector and base are short-circuited, the resistance R10
The circuit current I ₀ can be suppressed to a small value without increasing the resistance value R of ₀ , but unless the number of transistors in the number of stages is increased, the effect is small, resulting in an increase in the circuit area. Will end up.

Moreover, even by the above method, the circuit current I ₀ of the start-up circuit cannot be made zero after the bias line reaches the stable operation region.

The present invention has been made in order to solve the above problems in the conventional start-up circuit, and an object thereof is to provide a start-up circuit which consumes less power, operates stably, and can be realized in a small-scale configuration. To do.

[0010]

In order to solve the above-mentioned problems, the present invention, as shown in the conceptual diagram of FIG. 1, immediately after a power supply voltage V _CC is applied to a semiconductor integrated circuit 2, the semiconductor integrated circuit 2 is integrated. In the start-up circuit 1 including the bipolar transistor Q0 forming a current source for supplying the current of the bias line L _BIAS of the circuit 2, the bias line L _BIAS
A switching circuit 3 for controlling the current of the bipolar transistor Q0 that supplies a current to the transistor and a control circuit 4 having a delay characteristic for controlling the switching circuit 3 are provided.

[0011]

Operation: The start-up circuit 1 constructed as described above
In the above, the control circuit 4 can bring the switching circuit 3 into a non-conducting state after a lapse of a predetermined time from the application of the power supply voltage V _CC , that is, after the bias line L _BIAS reaches the stable operation region. As a result, the circuit current of the start-up circuit 1 is dominated by the leak current in the switching circuit 3, so that the current consumption is reduced and the circuit scale is reduced while ensuring stable operation, as compared with the conventional start-up circuit. Can be planned.

[0012]

EXAMPLES Next, examples will be described. FIG. 2 is a circuit configuration diagram showing a first embodiment of the startup circuit according to the present invention. Start-up circuit 1 in this embodiment
Is composed of an NPN type bipolar transistor Q0, a P channel type MOS transistor M1, resistors R0 and R1 and a capacitor C1. That is, the transistor Q
The collector of 0 is connected to the high potential power supply V _CC , and the base is connected to the bias line L _BIAS of the semiconductor integrated circuit 2 in the subsequent stage. The emitter of the transistor Q0 is connected to the source terminal of the MOS transistor M1 and the resistor R1
Is connected to the gate terminal of the MOS transistor M1 via. The gate terminal of the MOS transistor M1 is connected to the ground potential GND via the capacitor C1, and M
The drain terminal of the OS transistor M1 is connected to the ground potential GND via the resistor R0. The MOS transistor M1 constitutes the switching circuit 3, and the resistor R1 and the capacitor C1 form a time constant circuit 5 to constitute a control circuit for controlling the gate terminal of the MOS transistor M1.

Next, the operation of the start-up circuit 1 thus constructed will be described. When a predetermined voltage is applied between the high potential power supply terminal V _CC and the ground potential terminal GND, the collector of the transistor Q0 becomes the power supply voltage and the base thereof is the voltage of the bias line L _BIAS of the semiconductor integrated circuit 2 in the subsequent stage. V _BIAS . This voltage V _BIAS does not show a stable value. That is, the state at this time is the state at the time t ₁ in the operation waveform diagram shown in FIG. 3 and the gate voltage V _G of the MOS transistor M1 is at the low level.
The MOS transistor M1 is activated, and the emitter current I ₀ of the transistor Q0 is GN via the resistor R0.
Flow to D. This is the same state that the emitter of the transistor Q0 is connected to GND via the resistor R0. When the transistor Q0 enters the operating state in this way, the base potential of the transistor Q0, that is, the potential V _BIAS of the bias line L _BIAS is drawn into the stable operation region.

On the other hand, a current also flows through the time constant circuit 5 which is composed of the resistor R1 and the capacitor C1.
Thus, the gate voltage V _G of the MOS transistor M1 when a certain time (t) has elapsed is given by the following equation (2). V _G = V _CC · (1-e ^{−t / C1R1} ) ・ ・ ・ ・ ・ (2)

When the gate terminal voltage V _G is at low level, MO
If it is lower than the threshold voltage V _th of the S-transistor M1, that is, in the period of t _{1 to} t ₂ in FIG. 3, the MOS transistor M1 is in the operating state, and the base-emitter voltage V _{BE (Q0) of} the transistor Q0 is given as above. The voltage V _{BIAS on the} bias line L _BIAS acts so as to converge to a value determined by the following equation (3). V _BIAS = (I ₀ × R0) + V _{BE (Q0)} (3)

Next, when the gate terminal voltage V _G is at a high level and is higher than the threshold voltage V _th , that is, t in FIG.
During the period from ₂ onward, the MOS transistor M1 is in the non-operating state, and the emitter current I ₀ is cut off. As a result, the circuit current of the startup circuit is dominated by the drain leak current of the MOS transistor M1,
The current value is as low as pA.

As described above, according to this embodiment, the MOS transistor M1 is controlled by the control circuit including the time constant circuit 5, so that after the start-up operation is completed, the consumption current which is unnecessary in the start-up circuit is almost zero. It is possible to suppress the level to an ideal start-up circuit.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a circuit configuration diagram showing a switching circuit and its control circuit portion in the startup circuit of the second embodiment. In this embodiment, a switching circuit 3 is constructed by using a PNP type bipolar transistor Q1 instead of the MOS transistor M1 of the first embodiment shown in FIG. 2, and it is possible to obtain the same effect as that of the first embodiment. You can

Next, a third embodiment will be described with reference to FIG. Similarly, FIG. 5 is a circuit configuration diagram showing a switching circuit and its control circuit portion in the startup circuit of the third embodiment. In this embodiment, instead of the MOS transistor M1 of the first embodiment shown in FIG. 2, the switching circuit 3 is configured by a bidirectional switch element SW composed of a MOS transistor. It is possible to obtain the same operational effect as.

In each of the embodiments shown in FIGS. 2 to 5, M
Although the switching circuit 3 is configured by a bidirectional switch element including an OS transistor, a bipolar transistor, or a MOS transistor, the switching circuit includes at least one MOS transistor and at least one bipolar transistor. It goes without saying that it can be realized by a combination.

In each of the above embodiments, the time constant circuit is used as the control circuit of the switching circuit, but the present invention is not limited to this, and, for example,
MOS transistor M in the first embodiment shown in FIG.
Instead of the CR time constant circuit for controlling the gate terminal potential of 1, a delay circuit composed of a logic circuit can be used.

The control of the setup time of the bias line current can be realized by selecting the circuit constant of the time constant circuit composed of the resistor R1 and the capacitor C1 in each of the above-mentioned embodiments.
The setup time can also be controlled by controlling the gate length and the gate width of the MOS transistors forming the switching circuit at the device level while the circuit constant of the time constant circuit remains fixed.

In each of the above embodiments, the start-up circuit is shown when a positive power supply voltage is used. FIG. 6 shows a schematic structure of a start-up circuit according to a fourth embodiment when a negative power supply voltage is used. . This embodiment comprises a PNP transistor Q0 ', a resistor R0, a switching circuit 3 and a time constant circuit 5. In this embodiment, for example, an N-channel type MOS transistor can be used as the switching circuit 3, and the same effect as that of the embodiment shown in FIG. 2 can be obtained.

Next, a fifth embodiment of the present invention will be described with reference to FIG. In this embodiment, in the start-up circuit 1 of each of the embodiments shown in FIGS. 2 to 6, the circuit components 6 including the switching circuit 3 excluding the time constant circuit 5 are on the same semiconductor substrate as the semiconductor integrated circuit 2. The time constant circuit 5 is provided on the upper side and is provided as an external circuit separately from the semiconductor substrate.

FIG. 8 is a diagram showing a sixth embodiment. In this embodiment, the switching circuit 3 and the time constant circuit 5 are excluded from the start-up circuit 1 of each of the embodiments shown in FIGS. The circuit configuration unit 6 is provided on the same semiconductor substrate as the semiconductor integrated circuit 2, and the switching circuit 3 and the time constant circuit 5 are provided.
Is provided as an external circuit separately from the semiconductor substrate.

As in the fifth and sixth embodiments, one or both of the time constant circuit and the switching circuit forming the start-up circuit can be formed as an external circuit, as shown in FIGS. It is possible to obtain the same effect as that of the embodiment.

Next, an example of using the startup circuit according to the present invention will be described with reference to FIG. In this usage example, the start-up circuits 11, 12, and 13 according to the present invention are connected to the power supply terminal V _CC.
Is arranged between the semiconductor integrated circuit and the GND, and is configured to supply a current to the bias line of one or a plurality of semiconductor integrated circuits. The semiconductor integrated circuit is adjusted by adjusting a control circuit of a switching circuit including a time constant circuit. Can be set up simultaneously or separately. FIG. 10 shows an operation mode in which the setup times are different and the setups are performed separately.

[0028]

As described above on the basis of the embodiments,
According to the present invention, it is possible to provide a start-up circuit that consumes less current, has a smaller circuit scale, and stably performs a desired operation.

[Brief description of drawings]

FIG. 1 is a conceptual diagram for explaining a startup circuit according to the present invention.

FIG. 2 is a circuit configuration diagram showing a first embodiment of the present invention.

3 is a diagram showing a waveform of a gate terminal voltage of a MOS transistor for explaining the operation of the first embodiment shown in FIG.

FIG. 4 is a circuit configuration diagram showing a main part of a second embodiment.

FIG. 5 is a circuit configuration diagram showing a main part of a third embodiment.

FIG. 6 is a schematic configuration diagram showing a fourth embodiment.

FIG. 7 is a schematic configuration diagram showing a fifth embodiment.

FIG. 8 is a schematic configuration diagram showing a sixth embodiment.

FIG. 9 is a diagram showing an example of use of a startup circuit according to the present invention.

FIG. 10 is a diagram showing an operation mode of the use example shown in FIG. 9.

FIG. 11 is a circuit configuration diagram showing a configuration example of a conventional startup circuit.

[Explanation of symbols]

 1 Startup circuit 2 Semiconductor integrated circuit 3 Switching circuit 4 Control circuit 5 Time constant circuit

Claims (11)

[Claims] 1. A start-up circuit having a current source for supplying a current to a bias line of the semiconductor integrated circuit immediately after a power supply voltage is applied to the semiconductor integrated circuit, wherein the current of the bias line current source is controlled. And a control circuit having a delay characteristic for controlling the switching circuit. 2. The start-up circuit according to claim 1, wherein the control circuit comprises a CR time constant circuit. 3. The start-up circuit according to claim 1, wherein the control circuit includes a delay circuit including a logic circuit. 4. The switching circuit comprises at least one switching circuit.
The start-up circuit according to claim 1, wherein the start-up circuit is composed of one or more MOS transistors. 5. The switching circuit comprises at least one switching circuit.
The start-up circuit according to claim 1, wherein the start-up circuit is composed of one or more bipolar transistors. 6. The switching circuit comprises at least one switching circuit.
The start-up circuit according to claim 1, wherein the start-up circuit is configured by a combination of one or more MOS transistors and one or more bipolar transistors. 7. The start-up circuit according to claim 1, wherein the switching circuit and the control circuit are provided on the same semiconductor substrate as the semiconductor integrated circuit. 8. The switching circuit is provided on the same semiconductor substrate as the semiconductor integrated circuit, and the control circuit is separately provided outside the semiconductor substrate. The start-up circuit according to any one of items. 9. The switching circuit and the control circuit,
The start-up circuit according to any one of claims 1 to 6, wherein the start-up circuit is separately provided outside a semiconductor substrate on which a semiconductor integrated circuit is formed. 10. A delay characteristic of the control circuit is fixed, and a setup time of a bias line current is controlled by controlling a gate length and a gate width of a MOS transistor forming the switching circuit. The start-up circuit according to claim 4, wherein 11. A plurality of start-up circuits according to any one of claims 1 to 10 are provided, and each start-up circuit is configured to supply a current to a bias line of one or a plurality of semiconductor integrated circuits. A start-up circuit device characterized in that a switching circuit of the circuit is configured to be controlled simultaneously or individually with different delay times.