JPH0315369B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a relaxation oscillation circuit that outputs a triangular wave oscillation signal.

[Prior Art] A conventional relaxation oscillation circuit is shown in FIGS. 5 and 6.
Relaxation oscillation circuits using voltage comparators generally include a one-voltage comparator type circuit and a two-voltage comparator type circuit. FIG. 5 shows a one-voltage comparator type circuit, and FIG. 6 shows a two-voltage comparator type circuit.

In FIG. 5, Q1 to Q9 are transistors,
X1 to X3 are nodes, Ia is a constant current source, Ra and Rb are resistors, CT is a charging/discharging capacitor, T1 is a power supply terminal to which voltage _Vcc power is supplied, T2 is a grounding terminal connected to ground, and T3 is a This is an output terminal for outputting a triangular wave oscillation signal to the outside.

Next, the operation of the relaxation oscillation circuit configured as described above will be explained using the operating waveforms shown in FIG. First, Q
Consider the case where Q7 is in the on state and the potential at node X2 shown in FIG. 7c (the dotted line in FIG. 7c indicates the potential at node X1) is higher than the potential at node X1 shown in FIG. 7a. . In this state, charge/discharge capacitor CT
Since the charge at the node X2 is discharged through the resistor Rb, the potential at the node X2 decreases with time. When the potential of node X2 becomes lower than the potential of node X1, constant current source Ia,
A voltage comparator composed of transistors Q1 to Q4 operates to lower the potential at node X3 shown in FIG. 7b to a low level.

This turns off transistors Q5 and Q7,
The potential of node X1 increases, and the charge/discharge capacitor CT
The discharge path of the charge-discharge capacitor disappears
Only the charging current from resistor Ra flows through CT. Therefore, the potential at the node X2 increases with time.
When the potential at node X2 becomes higher than the potential at node X1, the voltage comparator composed of constant current sources Ia, Q1 to Q4 operates to raise the potential at node X3 to a high level. As a result, transistors Q5 and Q7 are turned on, and the potential at node X1 decreases, returning to the initial state.

Next, the configuration of the relaxation oscillation circuit shown in FIG. 6 will be explained. In FIG. 6, Q10 to Q18 are transistors, Y1 to Y6 are nodes, Ib is a constant current source,
Rc is resistance. In FIG. 6, the same or corresponding parts as in FIG. 5 are given the same reference numerals.

Next, the operation of the relaxation oscillation circuit configured as described above will be explained using the operating waveforms shown in FIG. First, the potential of the node Y2 shown in FIG. 8d (the dotted line L2 shown in FIG. 8d shows the potential of the node Y1, and the dotted line L3 shows the potential of the node Y3) is between the potentials of the nodes Y1 and Y3. Consider a case where the potential at the node Y5 shown in FIG. 8a is at a low level and the potential at the node Y6 shown in FIG. 8b is at a high level. When the potential of node Y2 is between the potentials of nodes Y1 and Y3, both transistors Q3 and Q16 are in an off state. Since the circuit composed of transistors Q16 and Q18 and resistor Rc constitutes an RS latch, the previous state is maintained when both transistors Q3 and Q16 are off.

When the potential at node Y5 is at a low level, the potential at node Y4 shown in FIG. 8c is also at a low level, and transistor Q5 is in an off state. In this state, a charging current flows through the resistor Ra to the charging/discharging capacitor CT, so the potential at the node Y2 increases with time. When the potential of node Y2 becomes higher than the potential of node Y3,
A voltage comparator composed of constant current source Ia and transistors Q1 to Q4 operates, and transistor Q3 is turned on. As a result, the potential at the node Y5 becomes a high level, the potential at the node Y6 becomes a low level, and the potential at the node Y4 becomes a high level, and the transistor Q5 is turned on. When transistor Q5 turns on, the charging/discharging capacitor
Since discharge current flows from CT through resistor Rb,
The potential at node Y2 decreases with time. Node Y2
When the potential at node Y1 becomes lower than the potential at node Y1, a voltage comparator composed of constant current source Ib and transistors Q10 to Q15 is activated, and transistor Q16 is turned on. As a result, the potential at the node Y5 becomes a low level, and the potential at the node Y6 becomes a high level, returning to the initial state.

[Problem that the invention seeks to solve]

FIG. 9 is a waveform diagram for explaining that the relaxation oscillation circuits of FIGS. 5 and 6 cannot obtain oscillation frequency accuracy at high frequencies. The reason why oscillation frequency accuracy cannot be obtained is that there is a response delay after the charging/discharging waveform of the charging/discharging capacitor CT passes the reference voltage of the voltage comparator until the charging/discharging transistor Q5 is sensitive to it. Each case of this response delay is shown in FIGS. 9a and 9b. The case shown in FIG. 9a is a case where there is a delay ts from when the charging/discharging waveform of the charging/discharging capacitor CT passes the reference voltage of the voltage comparator until the charging/discharging transistor Q5 starts to be sensitive. This delay results in waveform overshoot OS. In the case shown in FIG. 9b, the charging/discharging transistor Q5 has started to respond, but remains in an intermediate state between on and off. In this case, as shown in FIG. 9b, a time ts for remaining in the intermediate state and a flatness FN occur.

The relaxation oscillator circuits shown in FIGS. 5 and 6 include a lateral PNP transistor in the signal path, and the charge/discharge transistor Q5 performs saturation operation. A response delay as shown in b is likely to occur.

The present invention has been made in view of these points, and its purpose is to obtain a relaxation oscillation circuit whose oscillation frequency is stable even at high frequencies.

[Means for solving problems]

In order to achieve such an object, the present invention provides a first constant current source whose emitter is connected to a first constant current source.
an NPN transistor and a second NPN whose emitter is connected to the emitter of the first NPN transistor
a first resistor connected between the transistor and the collector/power supply of the first NPN transistor;
a second resistor connected between the collector of the NPN transistor and the power supply; a third NPN transistor whose base is connected to the collector of the first NPN transistor and the collector to the power supply;
A fourth NPN transistor whose collector is connected to the power supply, and a fifth NPN transistor whose emitter is connected to the second constant current source.
a sixth NPN transistor whose emitter is connected to the second constant current source and whose collector is connected to the base of the second NPN transistor;
a third resistor connected between the emitter of the NPN transistor and the base of the fifth NPN transistor;
The emitter of the fourth NPN transistor and the sixth
The fourth transistor connected between the bases of the NPN transistor
A fifth resistor connected between the emitter of the third and NPN transistors and the collector of the fifth NPN transistor, and the collector of the fifth NPN transistor and the collector of the sixth NPN transistor. a sixth resistor, a fifth and a sixth resistor;
connected between the bases of the NPN transistor of
A current proportional to the current flowing through the connection point with the base of the sixth NPN transistor is caused to flow through the connection point with the base of the fifth NPN transistor.
a current mirror circuit consisting of seventh and eighth NPN transistors and voltage level shifting means, and a first PNP whose emitter is connected to a third constant current source, whose base is connected to the emitter of the third NPN transistor, and whose collector is connected to ground. a second PNP transistor whose emitter is connected to a third constant current source, whose base is connected to the emitter of the fourth NPN transistor and whose collector is connected to the base of the first NPN transistor;
a fourth constant current source connected between ground;
A charge/discharge capacitor is provided between the collector of the PNP transistor and ground.

[Effect]

In the present invention, the transistor controlling charging and discharging does not perform saturation operation.

〔Example〕

A first embodiment of the relaxation oscillation circuit according to the present invention will be described below.
As shown in the figure. In FIG. 1, I1 to I4 are the first to fourth constant current sources of constant current sources i1 to i4, and N1 to N
8 is the first to eighth NPN transistors, P1 is the first PNP transistor, P2 is the second PNP transistor for controlling charging and discharging, R1 to R6
are first to sixth resistors with resistance values r1 to r6, R7 is a resistor with a resistance value r7 which constitutes the first voltage level shifting means, R8 is a resistor with a resistance value r8 which constitutes the second voltage level shifting means, CT is a charge/discharge capacitor,
BT is a DC power supply with a voltage of _Vcc , T1 is a power supply terminal to which a DC power supply of a voltage of _Vcc is supplied, T2 is a grounding terminal connected to the ground, T3 is an output terminal from which a triangular wave oscillation signal is output, A to F are nodes. Note that the seventh and eighth NPN transistors 7 and 8 and the resistor R
7 and R8 constitute a current mirror circuit.

Next, the operation of the relaxation oscillation circuit configured as described above will be explained using the operating waveforms shown in FIG. 4.
First, consider the case where the potential at node F (the dotted line L4 indicates the potential at node A) shown in FIG. 4f is higher than the potential at node A shown in FIG. 4a. At this time, the NPN transistor N1 is on and the NPN transistor N2 is off, so the potential at node B shown in FIG. 4b is set to VB, and the potential at node C shown in FIG. 4c is set to VC.
Assuming that the potential at node D shown in FIG. 4d is VD and the potential at node E shown in FIG. 4e is VE, the following relationship holds true.

VB＜VC …(1) VD＜VE …(2) Therefore, NPN transistor N5 is off,
NPN transistor N6 is in an on state. In this case, the potential VA at node A is expressed by the following equation.

VA=V _cc −r1・i1−(r5+r6)・i2 −V _BE3 …(3) Here, V _BE3 is NPN transistor 3 base・
It is the voltage between emitters. As shown in equation (1), VB<
Since VC, PNP transistor P1 is on,
The PNP transistor P2 is off, and a discharge current of i4 flows from the charging/discharging capacitor CT, and the node F
The potential of decreases with time. When the potential at node F becomes lower than the potential at node A, NPN transistor N1 begins to turn off, and the potential at node B begins to rise.
Since the potential at node A also begins to rise, NPN
The degree to which transistor N1 is turned off increases. Due to this positive feedback phenomenon, the NPN transistor N1 is completely turned off and the NPN transistor N2 is completely turned on.

When the NPN transistor N1 is completely off and the NPN transistor N2 is completely on, the following relationship holds true.

VB＞VC …(4) VD＞VE …(5) Therefore, NPN transistor N5 is on,
NPN transistor N6 is in an off state. In this case, the potential VA at node A is expressed by the following equation.

VA=V _cc −r5・i2−V _BE3 …(6) In this case, the potential of node A is compared to the value of equation (3),
It is higher by r1・i1+r6・i2.

As shown in equation (4), since VB > VC, PNP
Transistor P1 is off, PNP transistor P
2 is on. Assuming that i3>i4, a charging current of i3-i4 flows through the charging/discharging capacitor CT,
The potential at node F increases with time. When the potential of node F becomes higher than the potential of node A, NPN transistor N1 starts to turn on, so the potential of node B starts to fall, the potential of node A also starts to fall, and further.
The degree to which the NPN transistor N1 is turned on increases. Due to this positive feedback phenomenon, the NPN transistor N1 is completely turned on and the NPN transistor N2 is completely turned off, returning to the initial state.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. The circuit in Figure 2 uses resistors R7 and R8 in Figure 1.
It is integrated with NPN transistor N9,
This embodiment provides the same effects as the first embodiment.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention. The circuit in Figure 3 uses resistors R7 and R8 in Figure 1.
The arrangement of the NPN transistors N7 and N8 is exchanged, and the same effect as in the first embodiment is achieved.

〔Effect of the invention〕

As explained above, the present invention includes the first to fourth constant current sources, the first to eighth NPN transistors, and the first to fourth constant current sources.
By providing the second PNP transistor, the first to sixth resistors, the first and second voltage level shift means, and the charge/discharge capacitor, the base input of the first and second PNP transistors is connected to the positive feedback route. The second PNP transistor that controls charging and discharging does not need to operate in saturation mode, and the base of the PNP transistor with a large base diffusion capacitance can be replaced with an emitter follower with a low output impedance. Since the base diffusion capacitance can be charged and discharged quickly under control, response delay can be extremely reduced compared to conventional circuits, and a relaxation oscillation circuit with high precision even at high frequencies can be obtained.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the relaxation oscillation circuit according to the present invention, Fig. 2 is a circuit diagram showing a second embodiment of the invention, and Fig. 3 is a circuit diagram showing a third embodiment of the invention. 4 is a waveform diagram for explaining the operation of the circuit in FIG. 1, FIGS. 5 and 6 are circuit diagrams showing conventional relaxation oscillation circuits, and FIG. 7 is the circuit in FIG. 5. 8 is a waveform diagram for explaining the operation of the circuit of FIG. 6, and FIG. 9 is a waveform diagram for explaining the oscillation frequency accuracy in the conventional circuit. I1-I4...constant current source, N1-N8...
NPN transistor, P1, P2...PNP transistor, R1-R8...resistor, CT...charging/discharging capacitor, BT...DC power supply, T1...power terminal, T2...ground terminal, T3...output terminal, A ~
F...Node.

Claims (1)

[Claims] 1 The first emitter is connected to the first constant current source.
and the emitter is the first NPN transistor.
the second connected to the emitter of the transistor
an NPN transistor; a first resistor connected between the collector of the first NPN transistor and the power supply; a second resistor connected between the collector of the second NPN transistor and the power supply; 1st
a third NPN transistor whose base is connected to the collector of the second NPN transistor and whose collector is connected to the power supply; and a fourth NPN transistor whose base is connected to the collector of the second NPN transistor and whose collector is connected to the power supply.
a fifth NPN transistor whose emitter is connected to a second constant current source;
between a sixth NPN transistor whose emitter is connected to the second constant current source and whose collector is connected to the base of the second NPN transistor; and between the emitter of the third NPN transistor and the base of the fifth NPN transistor. the third resistor connected and the fourth
a fourth resistor connected between the emitter of the NPN transistor and the base of the sixth NPN transistor;
a fifth resistor connected between the collector of the fifth NPN transistor and the collector of the sixth NPN transistor; 6
connected between the bases of the NPN transistor of
A current proportional to the current flowing through the connection point with the base of the sixth NPN transistor is caused to flow through the connection point with the base of the fifth NPN transistor.
A current mirror circuit consisting of seventh and eighth NPN transistors and voltage level shifting means, an emitter connected to a third constant current source and a base connected to the third constant current source.
A first PNP transistor whose emitter is connected to the emitter of the NPN transistor and whose collector is connected to ground, and whose emitter is connected to a third constant current source and whose base is connected to the emitter of a fourth NPN transistor whose collector is connected to the first NPN transistor. a second PNP transistor connected to the base of the transistor;
a fourth constant current source connected between the collector of the second PNP transistor and ground; and a charging/discharging capacitor connected between the collector of the second PNP transistor and ground; A relaxation oscillation circuit characterized in that a triangular wave oscillation signal is output from a collector.